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MCC091 2013/KJ&LP
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Course PM MCC091
Introduction to Integrated Circuit Design
Academic year 20132014
Course web site
For the latest information always check the course web site, which is located in PingPong,
Chalmers learning management system. We publish as much as we can with open access, but
to access all information you must log in with your Chalmers login ID and you must be
registered for the course. The URL for the login page is https://pingpong.chalmers.se
The three sections below are taken from the syllabus that can be found at

The overall aim of the course is to introduce the student to the field of CMOS integrated
circuit design and to the use of industrial CAD tools and their role in the application-specific
integrated circuit (ASIC) design flow.

After the course the student should be able to
conceive, design, implement, and verify the functionality of basic digital and analog
CMOS building blocks in the context of standard-cell design.
critically and systematically integrate knowledge to model, simulate, predict and
evaluate CMOS circuit behavior, also with limited or incomplete information.
use simple models suitable for back-of-the-envelope hand calculations to predict and
evaluate circuit performance measures like power dissipation and critical path delays, and to
use such models for choosing the appropriate cell structure and driving capability.
carry out basic circuit design tasks within given constraints by applying suitable
methods, also when in a context where technical aspects that are not cost effective might
be sacrificed for simplicity and time-to-market aspects.
identify, formulate, and solve basic problems concerning subsystem structures such as
adders/ALUs, and to make layout/performance trade-offs.
use industrial-type design automation tools for designing basic CMOS circuit elements
following the design flow set up by such tools (including tools for schematic capture, circuit
simulation, layout, design rule checking (DRC) and layout-vs-schematic (LVS)).
describe the fundamental limitations of the available circuit level design automation
tools and the available CMOS technology platforms.
propose solutions to basic design problems and after having solved the problem, on paper or
in lab, communicate their conclusions and the rationale underpinning these conclusions.

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Introduction to CMOS integrated circuit design; basic building blocks, technology
platforms and circuit design tools.
Design flow including basic floor planning, schematic capture, circuit simulation, layout,
DRC and LVS. Hands-on design skill training using Cadence electronic design
automation tools.
The MOSFET as a digital switch and an analog small-signal amplifier
piecewise linear (PWL) current model with the MOSFET as a voltage-controlled
resistor or current-source
MOSFET two-port large-signal model - the MOSFET as a resistor, or current source,
MOSFET capacitance model - adding the intrinsic input capacitance and the parasitic
output capacitance to the two-port model,
SPICE technology files, second-order effects, technology scaling.
CMOS technology and fabrication. Front-end and back-end processing steps.
The inverter - the basic building block
Static properties - the voltage transfer characteristics (VTC) ,
- resistive load, pseudo-NMOS load, active CMOS load,
Dynamic properties
- large-signal two-port inverter model: input and output parasitic capacitance, output
driving capability,
- transistor sizing for improved driving capability,
- definition of propagation delay, rise/fall time, FO4 delay,
- simple RC delay formula, buffer sizing, process corners
The inverter as an analog amplifier
- biasing and small-signal voltage amplification, small-signal two-port model
- analog building blocks. Single stage CMOS amplifiers. Current mirrors.
Static CMOS logic gates. Building logic gates with MOSFET switches. NAND, NOR,
AOI, OAI, and XOR gates.
Sizing MOSFETs in a logic gate for equal rise and fall times.
Dynamic logic gate two-port model: input capacitance, output driving capability, and
output parasitic capacitance
Definition of logical effort.
Critical path delays. Path efforts. Sizing gates for minimum path delay.
Basic layout using standard-cell layout templates.
Case study: 4-bit digital comparator.
Interconnect and wire delay.
Two-port RC wire model
Elmore's formula for wire delay estimations.
The use of repeaters for delay optimization.
Latches and flip-flops. Set-up and hold time requirements.
Clock generation and clock distribution. Clock gating.
Power dissipation. Power distribution. Power gating.
Carry look-ahead and prefix-tree adders.

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Course organization
The course runs during study period 1 and gives 7.5 credit points. The course is organized as
a bottom-up sister course to the top-down organized DAT092 "Introduction to electronic
system design". The course takes you from the basic building block, the MOS Field Effect
Transistor, through CMOS logic gates to sub-systems like adders and data paths.
Technology-node-independent performance models for power and speed are derived, giving
you generic tools to estimate cost and performance properties of present and future CMOS
The course is organized with weekly lectures, home assignments, and one or two circuitdesign tasks organized as a series of hands-on laboratory exercises using industrial electronic
design automation (EDA) tools from Cadence. Each laboratory session is associated with a
pre-lab home assignment, the submission of which on time before the lab session is a
prerequisite for being allowed to the lab hall.

Scheduled times and activities

Mondays 8-11.45AM
Mondays 1.15-5PM
Tuesdays 1.15-4PM
Thursdays 1.15-5PM


Labs group 1
Labs group 2

weeks 4-7 room 4220
weeks 4-7 room 4220
weeks 1-7 room ED
weeks 1-7 room ED

We will not use all seven hours of lecture/ tutorial time each week. We will let you know of
any changes to the schedule on the course homepage in PingPong.
Hand-in problem sets & pre-lab preparations
There will be three hand-in problem sets and four pre-lab preparations for the labs: all in all 7
solution sets to hand in. You must hand in your solutions no later than the deadlines shown
in the table below. All submissions are individual because they are an integral part of the
assessment in the course. You may work together with one other student when you
complete the problem sets but each of you must hand in your own solution. If you worked
with another student this way, that person must be identified on your handed-in solution.
You must be able to explain your solution at our request. If we detect deficiencies in your
solutions you get a return and you will have revise and resubmit.
Lab sessions
The lab sessions will run in study weeks 4-7. They will take place in the CSE depts lab room
4220 on floor 4 in the EDIT building, one floor below the lecture hall ED. There will be two
lab sessions, both on Mondays. The labs will be performed in groups of two students, so
called lab pairs. The teachers will decide who gets assigned to which session and on the lab
pairs. The groups will be posted on the course web page no later than at the beginning of
study week 3. The labs are compulsory. If you fall ill, or other unforeseen things happen to
you very late, please send a text message or an e-mail to Lena and Kasyab.
If you have not submitted your prelab on time, you will not be allowed to do the lab.

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Submissions, feedback, returns and re-submissions

Your solutions to hand-in problems and prelab assignments shall be submitted via PingPong.
Only submissions through PingPong will be considered since we are several teachers who
cooperate on the grading and feedback. Your solutions shall be submitted as pdf files except
when you are expected to submit an excel file. If your hand-in solution comprises more than
one file, you shall zip them into one file. We prefer typed solutions since they are easier to
read; however we accept hand-written solutions (except when we want you to submit an
excel file), but then you to scan your solution and submit it as a pdf file. If you write by hand,
you have to write legibly so we can read it.
Please, note that the assignment deadlines are not shown in PingPong - this is intentionally
so. This way any late submission and revisions can be submitted to the same inbox. Instead,
we shall use the timestamp on your submission to decide whether your submission was
submitted on time or not.
1 Hand-in set 1
2 Hand-in set 2
3 Pre-lab 1
4 Pre-lab 2
5 Pre-lab 3
6 Pre-lab 4
7 Hand-in set 3

Mon Sept 9 11.59PM (midnight)
Mon Sept 16 11.59PM (midnight)
Fri Sept 20 1PM
Fri Sept 27 1PM
Fri Oct 4 1PM
Fri Oct 11 1PM
Fri Oct 18 11.59PM (midnight)

Feedback on your submission will be given in PingPong, your submission will either be
approved or rejected; if rejected it must be revised and resubmitted in PingPong for approval.
If you submit your prelabs on time, we shall give you feedback no later than at the beginning
of your lab session. For solutions to hand-in problem sets that you hand in on Mondays, you
will receive feedback no later than by the start of the lecture on the following Thursday. You
can follow your progress in PingPong. You will be able to see if you passed or if you got a
return and have to revise, as well as the number of bonus points you have.
If you get a return, we want your resubmission within one week from when you received our
feedback. The final deadline for any resubmissions or late submissions that are to be
included in the examination for period 1 2013 is Monday November 11 at 8AM. After
that we will not grade any submissions until January 2014 unless there are special
circumstances such as illness.

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The main textbook is Weste and Harris: Integrated Circuit
Design 4th Edition.
It is available at the Chalmers bookstore, Cremona, and at DC in
the EDIT building. This book is the international edition of the
more expensive hardback book CMOS VLSI Design 4th
edition.There is a companion web site for the book at
For the analog part we will use a couple of sections from the
book: Allen & Holburg: CMOS Analog Circuit Design 2nd
Edition. It is available as an e-book from the Chalmers Library so you do not have to buy an
entire book for this part. If you already have Sedra & Smith: Microelectronics Circuits, 5th or
6th Edition, used in previous courses at Chalmers, that book can also be used for most of the
analog part. It is however not available as an e-book.
Live links and reading instructions will be made available on the course web site.

Lecturer and Kjell Jeppson, phone: 772 1856, office: room B528 in MC2 building.

Lena Peterson
lenap@chalmers.se phone: 772 1822, or 0706-268907
office: room 4113 (EDIT building floor 4 V, facing Rnnvgen)

Lab teaching Kasyab Subramanian

kasyab@chalmers.se room 4447 (EDIT building floor 4V)
Jesper Johansson: jjesper@student.chalmers.se
Christoffer Fougstedt: chrfou@student.chalmers.se

Consultation hours
We have scheduled consultation times that should fit with the deadlines for the pre-lab and
hand-in problem sets. Lena you can find in her office, 4113. Kjell can be found in room
4128, which is the meeting room in the same corridor.
Week 2:
Week 3:
Week 4:
Week 5:
Week 6:
Week 7:

Mon Sept 9 3-4PM (Lena)

Thu Sept 12 right after lecture (Lena)
Mon Sept 16 3-4PM (Lena)
Fri Sept 20 9-9.45AM (Lena)
Fri Sept 27 2-3PM (Kjell)
Fri Oct 4 9-10AM (Lena)
Fri Oct 11 9-9.45AM (Lena)
Fri Oct 18 2-3PM (Lena & Kjell)

In the PingPong calendar for the course, the consultation times are entered as events. Some
of these times we may have to change due to unforeseen events. In that case, notices will be
posted in the message board on the course PingPong page.

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The courses 7.5 credits are divided into three course elements (Sw. kursmoment):
Course element
Credits What you have to do to earn these credits
0111 Written examination
Pass the final exam
Pass the four pre-lab problem sets and pass the
0211 Laboratory
four in-lab sessions
0311 Home assignments
Pass the three hand-in problem sets
Your grade is determined by the final exam (for details, see below).
The final exam
The final exam is a four-hour closed-book exam. Allowed aids are pen and paper and a
calculator. Parameter sheets and design rule sheets are also allowed when needed. They will
be included with the exam when needed so you do not have to bring your own.
The exam comprises six problems each with a maximum score of 10 points, thus in all 60
points. You need at least 50 points to earn the grade 5, 40 points for the grade 4 and 30 points
for the grade 3. If you have less than 30 points you fail the exam (usually recorded as U in
the grading records). Any bonus points (see below) will be added to your score before the
resulting higher grade is determined once you have reached 30 points on the exam. So, bonus
points cannot be used to pass the course but can give you a higher grade.
Bonus points
Good hand-in problem-set and prelab solutions submitted on time will earn you bonus points
- one point per hand-in and prelab problem set. All in all, you can earn seven bonus points.
To earn you a bonus point, a hand-in or prelab problem-set solution must be
1. handed in on time
2. complete
3. legibly written
4. comprehensible (that is, we must understand what you mean)
5. substantially correct (that is only minor mistakes)
Your submissions should be written in English. Bonus points will be shown in PingPong for
each assignment as Mark=1 or Mark=0. Bonus points are valid for one year.

A 7.5-credit course is to correspond to 1/8 of an academic year, i.e. to a work load of
1600/8=200 hours. During the eight weeks of a study period this corresponds to 25 hours a
week. Hence, with two courses running in parallel the nominal work load is 50 hours/week.
The time scheduled for this course 65 hours, 16 hrs. for lab sessions and 49 hrs. for lectures
and exercises. Estimated time for the home assignments are 35 hours (5 hrs./assignment).
The remaining 100 hours are allotted for self-studies, reading textbooks, etc.

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Overview of scheduled activities & deadlines

The classroom time slots are Tuesdays 1.15-4PM and Thursdays 1.15-5PM, both in lecture
room ED. All four hours may not be used every Thursday, especially not in weeks 4-7 when
there are lab sessions. Lab slots are Monday 8-11.45AM & 1.15-5PM in study weeks 4-7 in
lab room 4220. This is a preliminary schedule; there may be some changes. These will be
posted on the course web site.
Week 1 (36)

Tues 3/9
Thurs 5/9



Week 2 (37)

Mon 9/9
Tues 10/9
Thu 12/9


Deadline hand-in 1

Week 3 (38)

Mon 16/9
Tues 17/9
Thur 19/9
Fri 20/9


Deadline hand-in 2
Deadline prelab 1

Week 4 (39)

Mon 23/9
Mon 23/9
Tues 24/9
Thur 26/9
Fri 27/9


Lab 1 group 1
Lab 1 group 2
Deadline prelab 2

Week 5 (40)

Mon 30/9
Mon 30/9
Tues 1/10
Thur 3/10
Fri 4/10


Lab 2 group 1
Lab 2 group 2
Deadline prelab 3

Week 6 (41)

Mon 7/10
Mon 7/10
Tues 8/10
Thur 10/10
Fri 11/10


Lab 3 group 1
Lab 3 group 2
Deadline prelab 4

Week 7 (42)

Mon 14/10
Mon 14/10
Tues 15/10
Thur 17/10
Fri 18/10


Lab 4 group 1
Lab 4 group 2
Deadline hand-in 3

Exam week

Mon 21/10 8.30-12.30 Final exam in V building