IEEE SPONSORED 2ND INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEM

(ICECS 2015)

Analysis of Energy Efficient PTL based Full Adders

using different Nanometer Technologies
Deepa

Sampath Kumar V.

M.Tech. (VLSI)
Department of Electronics and Communication
JSS Academy of Technical Education-NOIDA, India
rmdeepa@yahoo.com

Asst. Professor
Department of Electronics and Communication
JSS Academy of Technical Education-NOIDA, India

Abstract Full adder can be designed using CMOS logic,

transmission gates, dynamic logic or pass transistor logic. This
paper presents Pass Transistor Logic based one bit full adders.
The PTL based adder designs considered were SERF adder,
9A adder, 13A adder, CLRCL adder and 8T adder.
Conventional 28T CMOS adder was also analysed. All the
designs were simulated using Tanner EDA tool. Simulations
were done at 180nm, 130nm and 90nm technologies. Transient
analyses were done at frequencies ranging from 100MHz to
500MHz. The load capacitance was varied between 50fF to
250fF. Performance analyses were done with respect to power,
delay and energy consumption obtained at 180nm, 130nm and
90nm technologies. At 180nm and 90nm, the 8T adder has
lower power delay product (PDP). At 130nm 13A adder has got
lower PDP when compared to all other adder designs. The 2bit, 4-bit and 8-bit ripple carry adders were designed at 180nm
technology to analyse the performance in real time
applications. 8T and 13A ripple carry adders were found to be
the best with respect to delay and energy consumption
respectively.

Dynamic logic circuits have clock tree and it increases the

circuit complexity. The power dissipation will be slightly
higher in dynamic logic circuits due to the presence of clock
tree.

Keywords Pass Transistor Logic (PTL), Complementary

Metal Oxide Semiconductor (CMOS), Power Delay Product
(PDP), Complementary and Level Restoring Carry Logic
(CLRCL), Static Energy Recovery Full (SERF) adder

I.

INTRODUCTION

Low power portable handheld devices are in demand

today. More emphasis is laid on low power and compactness
of designs. One bit full adder is the essential and basic
building blocks used in many VLSI circuits like ripple carry
adder and multiplier. One bit full adder can be designed
using many logic techniques like CMOS, Transmission Gate
(TG), dynamic logic and PTL [1].
In CMOS logic, we use both pull up and pull down
networks. It has got NMOS pull down network always
connected between output and ground. The PMOS pull up
network will be connected between power supply and output.
We require at least 28 transistors to build one bit full adder.
In TG based design one TG is built using 1NMOS and
1PMOS. The drawback of TG logic is we need
complementary controlling signals for its operation. At least
we require 20 transistors to build TG based full adder.

The PTL based technique uses less number of transistors

compared to all other design techniques [2]. PTL based adder
can be designed using only 10 or 8 transistors. The drawback
of PTL is degraded voltage swing at the output. There will be
multiple threshold drops at the output. The NMOS can pass
0signal well, but can never pass 1 signal accurately. There
will always be threshold loss and output signal of NMOS
will be (V DD -V tn ). The PMOS can pass 1 signal well but
can never pass 0 signal accurately. It is always |+V tp |. If
output voltage swing is not a major concern and we want to
design circuits with reduced design complexity then PTL is
best. This technique ensures both lower PDP and low
transistor count.
Energy consumption of any circuit is the power delay
product. Power dissipation and delay are two design criteria
which are conflicting in nature [3]. Designing circuits with
low power dissipation with higher speed is difficult task. So
the best performance measurement will be PDP. Energy
consumption is nothing but the average energy required by
the output signal to switch from high to low or vice versa. In
this paper we had considered five PTL based adder designs
and one conventional 28T CMOS adder for PDP
performance analysis.
II.

REVIEW

The first adder considered is 28T CMOS adder [3] [9].

There are 14 transistors in the NMOS net which is connected
between output and ground. Another 14 transistors in PMOS
net connected between power supply and output. This is
designed rewriting Sum and Carry equations as in (1) and
(2).
(1)
(2)

978-1-4788-7225-8/15/$31.00 2015 IEEE

310

CMOS full adder circuit can be seen in Figure 1.The

circuit has got full peak to peak voltage swing and smaller
delay. The main disadvantage of this circuit is higher power
dissipation and transistor count.
The next full adder is PTL based SERF adder [4]. It can
be designed using only 10 transistors. There is no direct path
to the ground in this adder and hence short circuit current is
not generated. We know that total power dissipation of any
circuit is as in (3)

P total =P switching +P short circuit +P leakage

(3)

The SERF adder doesnt contribute power dissipation due

to short circuit. So overall power dissipation is reduced. The
charge stored in the load capacitance is applied back to
control the gates, which otherwise will drain through ground
during logic low. The SERF adder can be designed as shown
in Figure 2.

Next PTL based adder is 9A adder[5]. Total of 41 adders

can be built using different combination xor/xnor gates. 9A
and 13A adders stand out best among all adders with low
power dissipation and high speed. 9A adder is built using
SER xnor and Groundless xnor gates[6] [7]. The G-xnor has
no direct path to ground and hence contributes to low power
dissipation. The 9A adder can be seen in Figure. 3
Next is the 13A adder [5].13A adder is designed with
combination of SER xnor and inverter type xnor as shown in
Figure 4. The main advantage of 13A adder is SER xnor
where static energy is recovered and thus the power
dissipation is reduced.
Another PTL based adder considered is Complementary
and Level Restoring Carry Logic (CLRCL) adder [8]. It is
built using two inverters and three PTL based multiplexers as
shown in Figure. 5. The inverters act as buffers and help to
propagate carry signal fast. One of the inverter produces the
complementary signal of Cout which is useful in generating
Sum signal. The inverters also help to restore swing of the
output signal.

Figure 1. 28 transistor CMOS full adder.

Figure 3. 9A PTL based full adder.

Figure 2. SERF PTL based full adder.

Figure 4. 13A PTL based full adder.
311

The 8T adder [9] is designed using 3 multiplexes and 1

inverter as shown in Fig. 6. The inverter acts buffer and
reduces propagation delay of Sum signal. It also provides
complement of Cout signal which is used to generate Sum
signal of 8T adder. The 8T adder is designed using Sum and
Carry signals as in (4) and (5)

(4)
(5)

III.

SIMULATION RESULTS AND PERFORMANCE

ANALYSIS OF FULL ADDERS

The simulations were carried out using Tanner EDA tool

at 180nm, 130nm and 90nm technologies. All the adder
designs were simulated to obtain power dissipation and
delay. Then power delay product (PDP) is calculated.
Simulations were done at 180nm technology with power
supply of 1.8V. Average power dissipation is obtained as
shown in (6). Propagation delay is the time between 50% of
fastest changing input to 50% of fastest changing output.

(6)
Power dissipation of all adder designs at 180nm
technology can be seen in TABLE I. The frequency of input
signals was varied from 100MHz to 500MHz. The output
load capacitance applied was 100fF. It is observed that as we
increase the frequency the power dissipation also increases.
It was analysed from the table that, at lower frequencies 13A
adder has the lower power dissipation and at higher
frequencies CLRCL adder has the low power dissipation.
The 28T CMOS adder has got highest power dissipation
among all adder designs.
TABLE I.

POWER DISSIPATION OF ALL ADDER

DESIGNS AT 180NM TECHNOLOGY

Power Dissipation(uW)

Figure 5. CLRCL PTL based full adder.

Figure 6. 8T PTL based full adder.

FA Cell
28T

100M
Hz
46.61

150
MHz
74.1

200
MHz
97.28

300
MHz
144.8

500
MHz
227

SERF

44.84

65.98

83.56

121.5

175.8

9A

39.58

58.35

77.38

107.9

145.8

13A

34.73

51.08

64.48

92.62

127.9

CLRCL

47.69

58.78

64.87

84.26

123.4

8T

48.02

59.62

67.69

92.68

134.8

All the adder designs were simulated to find out delay at

various load capacitances ranging from 50fF to 250fF at
frequency of 200MHz. The TABLE II shows delay of all
adders at 180nm technology. When lower output load was
applied, 8T has got less delay and at higher output load 28T
CMOS adder has got lesser delay. The power delay product
is obtained for all adder designs as shown in Figure 7. PDP is
calculated for various output loads ranging from 50fF to
250fF at frequency of 200MHz. 8T adder has got lower
energy consumption at low output loads but not at higher
load 200fF and 250fF.

312

TABLE II.

DELAY OF ALL ADDER DESIGNS AT 180NM

TECHNOLOGY

Delay(ns)
FA Cell

50fF

100fF

150fF

200fF

250fF

28T

0.255

0.355

0.472

0.581

0.69

SERF

0.488

0.747

0.961

1.2

1.46

9A

0.274

0.488

0.671

0.869

1.07

13A

0.412

0.591

0.742

0.852

1.02

CLRCL

0.394

0.644

0.894

1.14

1.4

8T

0.244

0.279

0.348

0.697

1.05

frequencies. The delay is obtained by varying load

capacitance from 50fF to 250fF with frequency of 200MHZ
as in TABLE IV. The 8T adder operates at high speed at
lower output loads otherwise 28T CMOS adder is best.
The energy consumption of all adder designs at 130nm
technology is as shown in Figure 8. The energy consumption
of 8T adder is lowest at load capacitance of 50fF, otherwise
13A adder is best. SERF adder has got the highest energy
consumption despite of its energy recovery concept.
TABLE III.

POWER DISSIPATION OF ALL ADDER

DESIGNS AT 130NM TECHNOLOGY

Power Dissipation(uW)
FA Cell

100
MHz

150
MHz

200
MHz

300
MHz

500
MHz

28T

24.4

38.76

50.9

75.61

125.95

SERF

37.17

49

64.41

82.63

116.87

9A

31.91

42.1

55.72

71.31

103.6

13A

17.74

25.37

32.33

45.35

69.66

CLRCL

37.86

54.44

60.21

71.69

96.13

8T

34.18

44.67

49.85

63.34

86.65

TABLE IV.

DELAY OF ALL ADDER DESIGNS AT 130NM

TECHNOLOGY

Figure 7. Comparison of energy consumption of all adder

designs for various output loads at 180nm technology.
The adder designs were simulated at lower technologies
like 130nm and 90nm. At lower technologies we can work at
lower supply voltage. The power dissipation is proportional
to supply voltage as shown in (7). If supply voltage is
reduced then power dissipation automatically reduces. The
feature size of the transistor also reduces at lower
technologies and accordingly internal capacitances and
resistances also reduce. These features help to produce better
results at lower technologies

(7)

Delay(ns)
FA Cell

50fF

100fF

150fF

200fF

250fF

28T

0.186

0.236

0.304

0.355

0.422

SERF

0.396

0.503

0.701

0.884

1.07

9A

0.236

0.321

0.456

0.608

0.761

13A

0.288

0.316

0.398

0.522

0.618

CLRCL

0.209

0.313

0.418

0.523

0.627

8T

0.181

0.252

0.322

0.413

0.463

P avg = V2 DD *Cload*f

All adders were simulated at 130nm technology at supply

voltage of 1.3V. The power dissipation of all adder designs is
less as compared to 180nm technology. Here also the
frequencies are varied from 100MHz to 500MHz as shown in
TABLE III. Load of 100fF was applied in all the cases. The
13A adder has got low power dissipation at all the specified

Simulations were carried at 90nm technology at supply

voltage as low as 1V. The power dissipation of all adders
was very low as compared to 180nm and 130nm as shown in
TABLE V. 13A adder has got lowest power dissipation and
28T CMOS adder has got the highest power dissipation at all
the frequencies. 9A adder also has low power dissipation.

313

TABLE VI.

DELAY OF ALL ADDER DESIGNS AT 90NM

TECHNOLOGY

Delay(ns)

Figure 8. Comparison of energy consumption of all adder

designs for various output loads at 130nm technology.
TABLE V.

FA Cell

50fF

100fF

150fF

200fF

250fF

28T

0.178

0.275

0.385

0.467

0.563

SERF

0.121

0.221

0.302

0.393

0.494

9A

20.168

0.337

0.487

0.637

0.787

13A

0.19

0.317

0.449

0.562

0.718

CLRCL

0.145

0.27

0.415

0.436

0.54

8T

0.076

0.106

0.198

0.366

0.564

POWER DISSIPATION OF ALL ADDER

DESIGNS AT 90NM TECHNOLOGY

Power Dissipation (uW)

FA Cell

100

150

200

300

500

MHz

MHz

MHz

MHz

MHz

28T

15.36

24.31

31.92

47.27

78.81

SERF

12.13

20.22

25.5

38.46

60.97

9A

6.97

10.98

14.34

20.96

34.16

13A

5.26

8.67

10.88

16.27

26.91

CLRCL

12.6

17.92

19.57

24.65

35.18

8T

12.7

18.65

21.45

27.85

37.45

Delay for all the adder designs was obtained by varying

output load at frequency of 200MHz as shown in the TABLE
VI. Except for load of 250fF, at all other loading conditions
the 8T adder has got the lowest delay. At 250fF SERF adder
has got the lowest delay of 0.494ns and 9A adder has got
highest delay of 0.787ns.
When we observe tables for power dissipation and delay
at different nanometer technologies, we see that both delay
and power dissipation have conflicting criteria. If power
dissipation of any adder is low at particular technology then
its delay is high. We are unable to decide which adder design
is best at particular technology. So PDP is best measurement.
The variation of PDP of all adder designs at 90nm can be
observed from Figure 9. It shows that at lower output load
capcitance 8T adder has lowest PDP. 13A adder has got the
lower PDP for ouput load capacitance of 200fF and 250fF.

Figure 9. Comparison of energy consumption of all

adder designs for various output loads at 90nm technology.
IV.

SIMULATION RESULTS AND PERFORMANCE

ANALYSIS OF RIPPLE CARRY ADDERS

All the single bit adders can be used for constructing

ripple carry adders. The ripple carry adders are built using
one bit full adders through logic chaining. The ripple carry
adders provide performance analysis of full adders in real
time applications. Full adders are used to build 2-bit, 4-bit
and 8-bit adders. Simulations were done at 180nm
technology with power supply of 1.8V. Six different input
patterns are applied to each full adder [5]. The longest delay
of each adder is obtained. Adders were cascaded to build
ripple carry adders [8] at frequency of 200MHz and load
capacitance of 100fF. Average power dissipation of 2-bit, 4bit and 8-bit are obtained as in TABLE VII. The power
dissipation of each adder increases as number of stages
increase. The power dissipation of CLRCL adder is highest
among 2-bit and 4-bit adders. The power dissipation of 13A
is lowest in all three cases. The power dissipation of 8-bit
CLRCL adder has highest power dissipation of 3.432mwatts.

314

TABLE VII.POWER DISSIPATION AND DELAY OF ALL RIPPLE

CARRY ADDER DESIGNS
FA

2-bit

Cell

Power

4-bit

Delay

Power

8-bit
Delay

Power
(mW)

Delay

(mW)

(ns)

(mW)

(ns)

28T

0.199

3.14

0.435

5.27

SERF

0.098

4.98

0.232

6.59

0.566

9.98

9A

0.148

3.99

0.277

4.428

0.679

5.23

13A

0.023

1.502

0.121

2.078

0.348

3.274

CLRCL

0.792

2.042

1.654

4.657

3.432

8.435

8T

0.43

1.178

1.00

1.396

2.44

1.51

0.835

(ns)
7.51

The transistor count of 28T CMOS ripple carry adder is

very high among all ripple carry adders. So PTL based
adders are best suited for designing ripple carry adders. Carry
delay analysis from Figure 10 shows that 8T has got lesser
delay in all 3 cases. Energy consumption is obtained for all
adder designs and we can see from Figure 11, that 13A adder
has got lowest energy consumption and 8T adder is the
second best.

V.

The five PTL based adder designs and a 28T CMOS

adder design are presented in this paper. The results show
that, among all the PTL based adders the power dissipation
of 13A adder was lowest and best suited for low power
applications. When delay is taken into consideration 8T has
lowest delay among all the adders. 13A has lowest energy
consumption at 130nm technology. At 180nm and 90nm 8T
adder has lowest energy consumption. 2-bit, 4-bit and 8-bit
ripple carry adders were designed. 8T ripple carry adder was
fastest among all ripple carry adders, when analyzed for
worst case carry delay. 13A ripple carry adder has got very
low energy consumption as 2-bit, 4-bit and 8-bit ripple carry
adder. The transistor count of 28T CMOS ripple carry adder
is very high among all ripple carry adders. So PTL based
adders are best suited for designing ripple carry adders.
Overall 13A and 8T adders can be considered as best energy
efficient PTL based adders.
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Figure 10. Comparison of worst case analysis of carry

delay in PTL based ripple carry adder designs

CONCLUSION

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Figure 11. Comparison of energy consumption of ripple

carry adder designs
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