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Code i 9EF,-24

Examination,

D.4Lay

2012

co

II Semester Diploma

Register
Number

ELECTRONTCS

-I

Time:3 Hours

Answer any six

full

questions taking

Section.

questions from each

-I

controlled d.evice.

*ri.*rsal

5x

=5

gate.

ia
w

" of (1000), is
2's complement
(iv) Zener diode is
biased.
A trivalent impurities has
varence electrons.
Explain the working of a t ansisto;; a

(iiD

(b)

SECTION

two full

ik

l. (a) Fill in the blanks :


(D JFET is a _
(ii)
ir

lo

(2)

1Max. Marks : 100

ib

Instructions;

I
(l) Section -lis compulsory.

g.

ELECTRICAL & ELECTRONICS ENGINEERING BOARD

always

(v)

switch.

ed

SECTION
- - II
2. (a) Explain Intrinsic and Extrinsic semiconductors.

5
5

(b) Explain atomic structure of Germanium atom.


(c) Draw and explain the V-I characteristic of zener diode under reverse bias

3.

.p

condition.

(a)

(b)
(c)

Explain thermistor and_draw its typical resistance v/s Temperature


curve.
Explain the working of pNp transistor.
Explain zener diode as a voltage regulator.

(a)

4.

s.

(b)
(c)

(a)

(b)
(c)

I
5

Define alpha and beta of a transistor in CB configuration..


Write the expression
for relationship between o and
B.
I
Explain the working of JFET.
5
Explain the working of UJT.
I

SECTION _ III
Explain with sketch the working of (i) LDR (ii) LED.
Explain photo electric emission.
Sketch the following packages :

(i) ro

(ii) Flat (iii) DrL

I
4
6

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9EF,-24
Convert following :
(i) (25)ro to BinarY

(ii)
(b)

Find 2's complement of the following

(c)

Subtract using 2's complement method.


(15)ro - (28)ro

(D 11011 (ii)

100101

(1)

(b)

Convert the following binary to hexadecimal


(1) 1101 1001 (2) i100 110111
(ii) Convert following hexadecimal to binary :
(2) ED
(1) eF
(110),
bY
Divide (11011011)2

(c)

Multiply (1110)2 and (1010)2


Draw logic symbol and truth table for (i) EXOR (ii) NOR and explain.

(a)

lo

ib

.p
ed
ia

(b)

SECTION _ IV
Explain the following laws of Boolean algebra
(i) Commutative law
(iD Associative law
(iiD Distributive law
Simplify the following :

ik

(a)

7.

(357)8 to decimal

(a)

g.
co

6.

(D ae+A+es
(ii) (A+B+c).(A+B)

9.

(a)

(b)

10.

(c)
(a)

Realise the following gates using NOR

(i) AND

(ii)

oR

Explain the following general characteristic of logic families


(i) Threshold voltage
(ii) Noise margin
(iii) Propagationdelay
State De Morgan's theorem.
Solve the following using K-map

(i) Y: ABC + agc


(ii) Y: ABC + ABC
(b)
(c)

(iii) Y :ABC+

aBC +ABC +ABe


Explain how to interface TTL IC with Relays.
List any four important characteristics of TTL family.

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