A Top Down Approach To Mixed Signal SoC Verification

A Top-Down Approach to
Mixed-Signal SoC Verification
Sudarshanam Kommanaboyina
Microchip Technology India Pvt. Ltd.
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Bangalore, India
Copyright 2011 Magma Design Automation, Inc.
Agenda
Challenge
Traditional flow to simulate analog, digital blocks
Mixed-signal simulation
Co-Sim observations
Feasibility of Finesim for Co-Sim
Example
2
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Challenge
Mixed-signal SoC design

Polarity issues at the interface between
analog and digital blocks
Functional issues at the interface
Approach suggested to avoid re-spin
3
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Standalone Analog Simulations
en
Stimulus from analog testbench

or
reset_n
start
trim[4:0]
sel[2:0]
control[4:0]
an_in1
an_in2
an_in3
Stimulus from RTL simulations
4
A
N
A
L
O
G
S
P
I
C
E
N
E
T
L
I
S
T
an_out1
an_out2
an_out3
an_out4
an_out5
dig_out1
dig_out2
dig_out3
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Observations
Analog stimulus generated from designers with human errors in
design can carry the same perception to analog testbench that may
result in polarity issues
Eg. Control signal polarity getting inverted at the analog-digital
interface
Stimulus from RTL simulation has controllability and it is possible
to catch the polarity issues
It is tedious to check the results manually from the above two
methods
Almost no verification done after integration of standalone blocks (
simulated in spice) causing possible functional failures
Eg. missing level shifter in multi-supply designs
5
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Full-Chip RTL Simulations

en
reset_n
start
trim[4:0]
B
R L
T O 1
sel[2:0]
L C
control[4:0]
K
an_in1
an_in2
an_in3
A
N
A
L
O
G
B
E
H
A
V
I
O
R
A
L
M
O
D
E
L
an_out1
an_out2
an_out3
an_out4
an_out5
dig_out1
dig_out2
dig_out3
6
B
R L
T O 2
L C
K
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Observations
Behavioral models of analog modules used
(Verilog/VHDL)
Uses full-chip testbench to simulate full-chip RTL +
analog behavioral models
Behavioral model may not match with analog spice
netlist since it cannot capture spice device/model
complexity
Generates stimulus for standalone analog simulations
which are then used to run block level spice sims
Not possible to catch polarity issues, functional bugs
at the interface
7
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Full-Chip Spice Simulations
N
E
T
L
I
S
T
B
L
O1
C
K
en
reset_n
start
trim[4:0]
sel[2:0]
control[4:0]
an_in1
an_in2
an_in3
A
N
A
L
O
G
N
E
T
L
I
S
T
S
P
I
C
E
an_out1
an_out2
an_out3
an_out4
an_out5
dig_out1
dig_out2
dig_out3
8
N
E
T
L
I
S
T
B
L
O 2
C
K
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Observations
Digital gates equivalent spice netlist + Analog spice netlist used
for full-chip simulation
Takes weeks to run in true-spice and several days in fastSpice
Very few test cases are run at this stage, may not be possible to
catch the interface bugs
No standard verification methodology exists currently confirming
the verification coverage/closure.
Bugs caught at this stage may postpone the tapeout
9
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Full-Chip Co-Sim Simulation
en
reset_n
start
trim[4:0]
B
R L
T O 1
sel[2:0]
L C
control[4:0]
K
an_in1
an_in2
an_in3
A
N
A
L
O
G
S
P
I
C
E
N
E
T
L
I
S
T
an_out1
an_out2
an_out3
an_out4
an_out5
dig_out1
dig_out2
dig_out3
10
B
R L
T O 2
L C
K
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Full-Chip Co-Sim Simulation (Contd)
RTL + Analog Spice netlist simulation

RTL simulation by QuestaSim
Analog spice simulation by Finesim
Digital-to-Analog (D2A) & Analog-to-Digital

(A2D) interface
Logic
1
0
x
D2A
vdd
gnd
xvdd
A2D
>vdig1
<vdig0
vdig0< signal V < vdig1
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Observations
Start Co-Sim by plug-and-play analog blocks as and when the

block gets ready, without waiting for all the blocks to get ready
Compared to full-chip Spice simulation, Co-Sim takes very less

time to simulate the whole chip as the digital blocks are in RTL
form
Eg. fastSpice Vs spice ~10-30X
Cosim
Vs spice ~100X
Functional bugs and polarity issues between analog and digital

blocks can be caught at the early stage of design
Uses the existing full-chip RTL test bench infrastructure to verify

analog modules under real conditions
Feasibility to choose among analog Spice, fastSpice modes,

verilogA models all spice or mixed spice+verilogA
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Feasibility of Finesim for Co-Sim

Features

Magma (Finesim)
Verilog support
Yes
System Verilog support
Yes
Changes to behavioral models
Required/optional
VerilogA
Yes
VerilogAMS
Underdevelopment
Spice netlist
Yes
All advanced features of Finesim can be used for Co-Sim

( multi-cpu simulations, spice mode, fast mode etc)
Finesim supports all major RTL simulation tool vendors
( Modelsim, Ncsim, VCS)
Finesim has a provision to specify the voltage levels to each pin
separately, supports multi-voltage domain
Also supports instance based replacement
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Co-Sim Example Using Finesim

module top;
module test1(
test1.sp
// logic/reg/wire declaration
input logic
in1 ,
vvdd VDD 0 dc 1.8
test1 inst_test1(
input logic
in2 ,
vvss VSS 0 dc 0
.in1 (out1 ),
input logic
in3 ,
.global vss vdd
.in2 (out2 ),
input logic [1:0] in4 ,
.inc ./model.inc
.in3 (in3
),
output logic
out1 ,
.inc finemix.sp
.in4 (in4
),
output logic
out2 ,
*Default name of spice instance netlist file
.out1 (out1 ),
output logic
out3 ,
.out2 (out2 ),
inout
inout1,
.subckt test1 in1 in2 in3 in4[0] in4[1]
+ out1 out2 out3 inout1 inout2
.out3 (out3 ),
inout
inout2
*Spice netlist
.inout1(inout1),
);
.ends test1
.inout2(inout2)
parameter finesim_a2d=avdd";
);
parameter finesim_d2a=dvdd";
*can specify any number of subckt
test2 inst_test2(
parameter finesim_d2a$in1="dvdd1";
.in1 (in1 ),
parameter finesim_d2a$in4[1]="dvdd1"; *or specify paths for other spice netlist
.in2 (in2 ),
parameter finesim_d2a$inout1="dvdd1";
.out1 (out1 ),
parameter finesim_a2d$inout1="avdd1"; .option post
.tran 1p 100ns
.out2 (out2 ),
parameter finesim_a2d$out1="avdd1";
initial $finesim_module;
.out3 (out3 )
endmodule
);
.end
initial
config.inc
module test2(
begin//{
.a2d avdd vl=0.9 vh=0.9
input logic in1 ,
//testbench
.d2a dvdd vl=0 vh=2.8 vx=1.4 tr=0.3n tf=0.3n
input logic in2 ,
end//}
.a2d avdd1 vl=1.4 vh=1.4
output logic out1 ,
initial
.d2a dvdd1 vl=0 vh=1.8 vx=0.9 tr=0.3n tf=0.3n
output logic out2 ,
$finesim_config(config.inc);
.finesim test1.sp
output logic out3
endmodule
.option dump_ie=1
);
.option port_map_by_name=1 bus_format=[%d]
assign out1 = in1 && in2;
.option minimize_ie=1
assign out2 = in1 || in2;
assign out3 = in2;
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endmodule
14
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Q&A
Note: The Microchip name and logo are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries.
All other trademarks mentioned herein are property of their respective companies.
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A Top Down Approach To Mixed Signal SoC Verification

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A Top-Down Approach to

Mixed-Signal SoC Verification

Mixed-signal SoC design

Standalone Analog Simulations

Stimulus from analog testbench

Stimulus from RTL simulations

Full-Chip RTL Simulations

Full-Chip Spice Simulations

Full-Chip Co-Sim Simulation

Full-Chip Co-Sim Simulation (Contd)

RTL + Analog Spice netlist simulation

Digital-to-Analog (D2A) & Analog-to-Digital

Start Co-Sim by plug-and-play analog blocks as and when the

Compared to full-chip Spice simulation, Co-Sim takes very less

Functional bugs and polarity issues between analog and digital

Uses the existing full-chip RTL test bench infrastructure to verify

Feasibility to choose among analog Spice, fastSpice modes,

Feasibility of Finesim for Co-Sim

System Verilog support

Changes to behavioral models

All advanced features of Finesim can be used for Co-Sim

Co-Sim Example Using Finesim

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