---------------------------------------------------------------------------------- Company:

-- Engineer:
--- Create Date:
11:49:30 01/27/2016
-- Design Name:
-- Module Name:
FS1_m - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FS1_m is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
d : out STD_LOGIC;
b : out STD_LOGIC);
end FS1_m;
architecture Behavioral of FS1_m is
begin
firstproc: process(x,y,cin)
begin
if(x='0' and y='0' and cin='0') then
d<= '0';b<='0';
elsif(x='0' and y='0' and cin='1') then
d<= '1';b<='1';
elsif(x='0' and y='1' and cin='0') then
d<= '1';b<='1';
elsif(x='0' and y='1' and cin='1') then
d<= '0';b<='1';
elsif(x='1' and y='0' and cin='0') then
d<= '1';b<='0';
elsif(x='1' and y='0' and cin='1') then
d<= '0';b<='0';
elsif(x='1' and y='1' and cin='0') then
d<= '0';b<='0';

else
d<= '1';b<='1';
end if;
end process;
end Behavioral;

---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
12:20:32 01/27/2016
-- Design Name:
-- Module Name:
mux2_1_m - structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux2_1_m is
Port ( a : in
b : in
s : in
f : out
end mux2_1_m;

STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC);

architecture structural of mux2_1_m is

component and_m is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;

y : out STD_LOGIC);
end component;
component or1_m is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component not_m is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end component;
signal s1,s2,c1:std_logic;
begin
g1:not_m port map (a=>s,b=>c1);
g2:and_m port map (a=>c1,b=>a,y=>s1);
g3:and_m port map (a=>s,b=>b,y=>s2);
g4:or1_m port map (a=>s1,b=>s2,y=>f);
end structural;

---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
11:22:15 02/03/2016
-- Design Name:
-- Module Name:
mux4_1_2_1 - structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux4_1_2_1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
o : out STD_LOGIC);
end mux4_1_2_1;
architecture structural of mux4_1_2_1 is
component mux2_1_m is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
f : out STD_LOGIC);
end component ;
signal x,y:std_logic;
begin
g1:mux2_1_m port map (a=>a,b=>b,s=>s(0),f=>x);
g2:mux2_1_m port map (a=>c,b=>d,s=>s(0),f=>y);
g3:mux2_1_m port map (a=>x,b=>y,s=>s(1),f=>o);
end structural;

---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
12:40:22 01/27/2016
-- Design Name:
-- Module Name:
mux4_1_m - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux4_1_m is
Port ( a : in
b : in
c : in
d : in
s : in
o : out
end mux4_1_m;

STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC_vector(1 downto 0);
STD_LOGIC);

architecture Behavioral of mux4_1_m is

begin
process(s,a,b,c,d)
variable temp:std_logic;
begin
if(s="00")then
temp:=a;
elsif(s="01")then
temp:=b;
elsif(s="10")then
temp:=c;
else
temp:=d;
end if;
o<=temp;
end process;
end Behavioral;

---------------------------------------------------------------------------------

-- Company:
-- Engineer:
--- Create Date:
12:51:15 01/27/2016
-- Design Name:
-- Module Name:
mux4_1case_m - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux4_1case_m is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
o : out STD_LOGIC);
end mux4_1case_m;
architecture Behavioral of mux4_1case_m is
begin
process(s,a,b,c,d)
variable temp:std_logic;
begin
case s is
when "00"=>temp:=a;
when "01"=>temp:=b;
when "10"=>temp:=c;
when others=>temp:=d;
end case;
o<=temp;
end process;
end Behavioral;

---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
12:06:30 02/03/2016
-- Design Name:
-- Module Name:
demux1_4_m - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity demux1_4_m is
Port ( a : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
q : out STD_LOGIC_vector(3 downto 0));
end demux1_4_m;
architecture Behavioral of demux1_4_m is
begin
first:process(a,s)
begin
if(s="00")then
q(0)<=a;
elsif(s="01")then
q(1)<=a;
elsif(s="10")then
q(2)<=a;
elsif(s="11")then

q(3)<=a;
end if;
end process;
end Behavioral;

---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
12:38:34 02/03/2016
-- Design Name:
-- Module Name:
dmux1_4case_m - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dmux1_4case_m is
Port ( a : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
q : out STD_LOGIC_vector(3 downto 0));
end dmux1_4case_m;
architecture Behavioral of dmux1_4case_m is
begin
first:process(a,s)
begin
case s is

when"00"=> q(0)<=a;
when"01"=> q(1)<=a;
when"10"=> q(2)<=a;
when others=> q(3)<=a;
end case;
end process;
end Behavioral;