Device Scaling: CMOS

Dipankar Pal,
Dept. of EEE & EI,
BITS-Pilani, K. K. Birla Goa Campus

MOSFET IN SMALL-GEOMETRY
Scaling of MOS concerns systematic reduction of
dimensions supported by available technology.
Features:
Geometric ratios are preserved.
Proportional scaling results in a reduction of silicon area.
Increases overall functional density of chip.
Total power dissipation is reduced in Constant Field scaling;
increased in Constant Voltage scaling
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

Trend in Scaling of technology

Year

1985

1987

1989

1991

1993

1995

1997

1999

Feature
Size (m)

2.5

1.7

1.2

1.0

0.8

0.5

0.35

0.25

Average down-scaling from a generation to next is by a factor (S: ~ 1.2 to 1.5); happens
every 2/3 years . Today 0.018 m (or 18nm) technology is common and widely used.

Scaling of a typical MOSFET by a factor of S

Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

Methods of Scaling
Constant Field Scaling (Full Scaling)
To scale by a constant factor S (> 1):
All horizontal and vertical dimensions of
divided by S.

Supplies scaled by same factor (S)

The extent of scaling (S) determined by

technology and minimum feature size.

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Components after Scaling (Quantitative)

C ' ox =

ox
'

t ox

= S.

ox
t ox

[(

= S .Cox

2
k 'n
I D (lin) =
. 2. V ' GS V 'T .V ' DS V ' DS
2
S .k n 1
I (lin)
=
. 2 . 2.(VGS VT ).VDS V 2 DS = D
2 S
S
'

k 'n '
I D ( sat ) =
. V GS V 'T
2
'

S .k n 1
I ( sat )
2
. 2 .(VGS VT ) = D
2 S
S

P = I D .VDS
Now,
P ' = I ' D .V ' DS =

1
P
.I D .VDS = 2
2
S
S

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Methods of Scaling
Constant Voltage Scaling
To scale by a constant factor S (> 1):

All horizontal and vertical dimensions divided by S.

Extent of scaling (S) determined by technology and minimum feature size.

Supplies kept unchanged.
Doping densities increased by a factor S2

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Components after Scaling (Quantitative)

'

[(

2
k
I D (lin) = n . 2. V ' GS V 'T .V ' DS V ' DS
2
S .k n
=
. 2.(VGS VT ).VDS V 2 DS = S .I D (lin)
2
'

k 'n '
I D ( sat ) =
. V GS V 'T
2
'

S .k n
2
.(VGS VT ) = S .I D ( sat )
2

P ' = I ' D .V ' DS = S .I D .VDS = S .P

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Shortcomings of Scaling - I
Gradual Channel Approximation (GCA) no more holds.
If channel length (L) on the order of Drain/ Source depletion
region (xdD/ xdS), or depth of Drain/ Source-junction(xj), the
device is called short channel device.

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Short Channel Effects

Limitation on electron drift characteristics
Reduction in threshold voltage
Electron Drift Characteristics
1. Increased channel electric fields (Ey ~ 105 V/cm) saturates

drift

velocity (vd(sat) ~ 107 cm/s). Even 90% vd(sat) saturates ID;

quadratic function of VGS no more valid.
2. Carrier velocity becomes a function of normal (vertical) component Ex.
Scattering of surface charges leads to collisions, surface mobility
drops.

n (eff ) =

n0
1 + .E x

n0

n0

ox
1 + (VGS VT )
1+
.(VGS Vc ( y ) )
t ox . Si
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

Short Channel Effects

Reduction in threshold voltage
1. Long-channel expression of VT no more valid.
2. Depletion region created by Drain (Source)-pn junction with bulk to be
considered.
3. Shape of Gate-induced channel is trapezoid (not rectangular)

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Estimation of VT for Short Channel device

VT 0 ( shortchannel ) = VT 0 VT 0

where 2nd term is error term due to charge

difference between rectangular and trapezoidal depletion region.

The trapezoidal bulk depletion channel-region contains charge QBO given by:
L + LD
QBO = 1 S
. 2.q. Si .N A . 2 F
2L

The junction depletion region depths are give by xdS =

kT N D .N A

. ln
where junction built-in voltage is 0 =
2

q
ni

2. Si
.0 and xdD =
q.N A

2. Si
.(0 + VDS )
q.N A

From the cross-sectional view of the junction depletion layer and depth of the channel
into the bulk, we can write:

(x

2 xdD

LD x j . 1 +
1 and

xj

2
2
+ xdD ) = x 2 dm + (x j + LD ) which leads to:

2x
LS x j . 1 + dS 1

xj

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Error Term in Threshold Voltage at Zero

Drain-Source Bias: VT 0
Finally from

LD and LS

we can get the charge

difference in the trapezoidal channel which leads to the

error term of threshold voltage at 0 Drain-Source bias:
x j
1
2xdS
2xdD
VT 0 =
2qSi N A 2F . . 1 +
1 + 1 +
1

Cox
2L
xj
x
j

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

Shortcomings of Scaling - II
In Narrow Channel, W is on the order of maximum depletion region
thickness (Xdm).

Effect: Increase in threshold voltage

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

VT0 IN NARROW Channel

The Gate-area overlaps on the large FOX-area in the
fringes.
An additional shallow depletion region forms.
For large W, this is negligible. But for comparable W
(and thin tox), VT goes up due to this depletion charge.
VT 0 (narrow channel ) becomes VT 0 + VT 0 where
VT 0

xdm
1
=
. 2q Si N A 2 F .
C ox
W

for an empirical parameter dependent on shape of

fringe given by =
for shape of quarter-circular arc.
2
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

Other limitations of small geometry

Two-dimensional electric field vector controls - cannot be decoupled.
Complications: e.g., for VGS < VT, potential barrier controlled both by VGS
and VDS . Increase in VDS lowers the barrier.
This Drain Induced Barrier Lowering (DIBL) leads to sub-threshold ID.
ID caused by DIBL is expressed as:
q

qDnWxc n0 kTr
I D (subthreshold )
.e .e
LB

q ( A.VGS + B .VDS )
kT

where xc is the sub-threshold channel depth, Dn is the electron diffusion

coefficient LB is the length of the barrier and r is a reference potential.
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

Punch Through
For large VDS, depletions region of drain extends
towards source.

For small geometry, the two depletion regions may

even merge.

This is called Punch Through which can damage the

device
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

PIN HOLES and Oxide Break-down

In practice
uniformly.

all

dimensions

cannot

be

reduced

If tox, e.g., is reduced by S; for very small geometry

localized non-uniform oxide growth called Pin-Holes
develop.
Another problem
Breakdown

with

very

thin

Ref: "CMOS Digital Integrated Circuits:

Analysis & Design", Kang, S. et al

tox

is

Oxide

Hot carrier generation

Constant voltage, increased doping and
geometry combine to increase electric field.

small

Increased electric field generates electrons and holes

at high kinetic energy called Hot Carrier.

Hot Carriers injected into gate-oxide damages oxide

interface charge distribution.
I-V characteristics change
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

Depiction of Hot carrier DAMAGE

At high VDS and in small geometries the effect is
observed.

Damage is localized on drain end.

Result is reduction of
degradation over a time.
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al

ID

and

general