IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO.

3, MARCH 2006

507

A Subthreshold Surface Potential Model for

Short-Channel MOSFET Taking Into Account
the Varying Depth of Channel Depletion Layer
Due to Source and Drain Junctions
Srimanta Baishya, Member, IEEE, Abhijit Mallik, Member, IEEE, and Chandan Kumar Sarkar, Senior Member, IEEE

AbstractAn analytical subthreshold surface potential model

for short-channel MOSFET is presented. In this model, the effect
of varying depth of the channel depletion layer on the surface
potential has been considered. The effect of the depletion layers
around the source and drain junctions on the surface potential,
which is very important for short channel devices is included in
this model. With this, the drawback of the existing models that
assume a constant channel depletion layer thickness is removed
resulting in a more accurate prediction of the surface potential. A
pseudo-two-dimensional method is adopted to retain the accuracy
of two-dimensional analysis yet resulting in a simpler manageable
one-dimensional analytical expression. The subthreshold drain
current is also evaluated utilizing this surface potential model.
Index TermsDepletion layer depth, drain-induced barrier lowering (DIBL), subthreshold, surface potential.

I. INTRODUCTION

HE DEVICE dimensions in CMOS technology, the dominant technology for integrated circuits (ICs), have been
scaled for quite some time now to achieve improved performance, particularly in terms of speed of operation, dynamic
power dissipation etc., in addition to increasing the packing density. In conformity with this, scaling of the power supply voltages is also necessary which, in turn, demands a reduction of
the threshold voltage. This, however, gives rise to a significant
increase in leakage current due to subthreshold conduction that
must be modeled accurately for robust circuit design. Modeling
of the leakage current is also important for dynamic circuits as
it determines the holding time of such circuits. Moreover, design of both digital and analog systems in which the devices
are operated in the subthreshold regime has evinced a lot of interest [1][10] due to the tremendous market demand for ex-

Manuscript received July 28, 2005; revised December 2, 2005. This work was
supported in part by the Department of Science and Technology, Government of
India, under Grant SR/S3/EECE/67/2004-SERC-Engg and in part by the Center
for Nanoscience and Technology, Jadavpur University, India. The review of this
paper was arranged by Editor C. McAndrew.
S. Baishya is with the Department of Electronics and Telecommunication
Engineering, Jadavpur University, Kolkata 700 032, India, on leave from the
National Institute of Technology, Silchar, India, under the Q.I.P. Programme
(e-mail: baishya_s@rediffmail.com).
A. Mallik is with the Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani 741 235, India
(e-mail: abhijit_mallik1965@yahoo.co.in).
C. K. Sarkar is with the Department of Electronics and Telecommunication
Engineering, Jadavpur University, Kolkata 700 032, India.
Digital Object Identifier 10.1109/TED.2005.864364

tremely low power applications. The analog circuits based on

the subthreshold operation of the devices have the additional
advantage of having significantly higher gain because of the
higher transconductance-to-current ratio of the devices in this
region [9].
One of the basic requirements for the analysis of MOS tranas many quantisistor is the evaluation of surface potential
ties of interest, implicitly or explicitly, depend upon it. Some of
the MOSFET models as reported in the literature [1], [10][13]
are based on surface potential. For a long-channel device, the
existing models for the surface potential meet the accuracy requirement. For such devices, the junction depletion layers along
the channel due to the source/substrate and drain/substrate junctions constitute a negligible portion of the channel. In weak inversion or depletion regime, the surface potential may be considered to remain constant over the large portion of the channel,
constituting the entire channel minus the above two junction depletion layers. We need to consider the surface potential only
over this portion to compute any quantity that depends upon
it. However, in the case of short-channel devices, the junction
regions are not negligibly small as compared to the channel
length; rather they constitute a significant portion of the channel.
A number of literatures are available on the modeling of the
small dimensional effect based on charge-sharing concept; but
in such developments, it has not been possible to justify rigorously all the steps [14]. A subthreshold surface potential model
for pocket implanted devices, which can also be used for conventional devices has been proposed in [3]. However, this model
on the varying depth of
does not consider the dependence of
the channel depletion layer due to the source and drain junctions.
An accurate prediction of the surface potential requires solution of Poissons equation in the entire channel region. In
general, this approach does not produce a simple analytical expression of finite number of terms in closed form. The ultimate
solution requires either approximation of the potential distribution [15], [16] or cut the infinite series to a finite number of
terms [2], [17]. Although the surface potential is accurately predicted by twodimensional (2-D) numerical solutions as done in
the device simulators, such tools are not suitable for use in circuit analysis as the computation time requirement is too large.
Therefore, a pseudo-2-D analysis applying Gausss law on the
surface of the channel is used as a compromise that produces
an analytical onedimensional (1-D) equation retaining the accuracy. Several such works for short channel uniformly doped

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Fig. 1.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 3, MARCH 2006

Fig. 2. Typical variation of depletion layer thickness in a long-channel

MOSFET.

MOSFET structure.

channel/pocket implanted device have been reported in the literature [1], [3], [18], [19] that assume a constant depletion layer
thickness in some of which the nonuniformity of the channel depletion layer depth is accounted for by using a fitting parameter.
In this paper, we present a subthreshold surface potential
model for MOS devices in which the effect of varying channel
depletion layer thickness is incorporated. The dependence of
the surface potential on the channel depletion layer around the
source and drain junctions has been incorporated in this model.
A pseudo 2-D analysis applying Gausss law on the surface is
used. The model can successfully generate the subthreshold
surface potential profiles for short channel MOSFET for wide
range of technology parameter values and bias potentials. The
usability of this model is not only limited to the short channel
devices, but can also be applied to long-channel devices.
II. MODEL DESCRIPTION
The MOSFET structure shown in Fig. 1 is used to develop
and implement the model. Applying Gausss law and neglecting
mobile charge carriers to a rectangular box in the channel depletion region of the MOSFET, the following equation can be
derived [3], [18]:
(1)
where
is the surface pois
tential with respect to interior of the substrate bulk,
is the source-to-body voltage,
the gate-to-source voltage,
[20] is the flat-band voltage,
is the gate oxide thickness,
is the oxide
is the channel doping density,
capacitance per unit area,
is the depletion layer depth, and
and
are the dielectric
permitivities of Si and SiO respectively.
If the channel is sufficiently long, then the source-channel and
the drain-channel junction depletion layers constitute a negligible portion of the entire channel length, and the surface potential profile over the channel outside the junction depletion layers
is sufficient to compute any quantity which depends on it. With
this consideration, when the device is in the weak inversion, the
surface potential profile may be considered to remain constant at
[14] and is dependent
only on the gate-to-body bias
, where
is the body effect coefficient and
is the thermal
voltage. However, for short-channel MOSFETs, the contribution of the two junction regions is no longer negligible and the

so called charge sharing effect has to be taken into account for

any modeling work. It is clear from (1) that the surface potential at a point depends on the depletion layer thickness which is
be modeled first
not constant. As such, it is required that
for an accurate prediction of the surface potential. If the channel
length is not too small and a reasonable amount of voltage is apwill typically vary with as
plied to source and/or drain,
shown in Fig. 2.
Unfortunately, the depletion layer depth around the source
and drain junctions is a complex function of substrate doping,
gate and source/drain bias voltages. A good model should
not only have a physically based approximate and simple
description for it but this should give an analytical solution of (1) also. Keeping these requirements in mind and
with
as
also considering the typical variation of
shown in Fig. 2, we propose an empirical model for this as
with the source and drain end values
and
respectively, where
is the junction depth,
and
are the depth of penetrations
of the depletion layers into the channel/substrate due to the
(between the
-source/drain and the
built-in potential
and
p-type channel/substrate) and the reverse bias
at the source and drain ends respectively,
is the drain-to-body bias,
is the effective channel length
defined as the distance from the edge of the source to the
edge of the drain as shown in Fig. 1. At the source end,
and as one moves toward the drain end it deat the point where
creases to
(curve 1) following this second order relation. Similarly, at the
and as one moves toward the
drain end,
at the point where
source end it decreases to
(curve 3) following a similar relation. Between the points
and
the depletion layer remains constant at
(curve 2). In general, the channel may be divided into three
regions as discussed in the later part of this section with the
with
depletion layer thickness modeled as
known values at the two ends in all the three regions. In a given
at
and
at
, then
region, if
and
. Solving them, we get
and
(2)

BAISHYA et al.: SUBTHRESHOLD SURFACE POTENTIAL MODEL FOR SHORT-CHANNEL MOSFET

In reality, in the vicinity of the two ends of the channel, a significant portion of the field lines emanating from source/drain
are mapped onto the space charges below the source/drain (outside the Gaussian box in the channel) and hence a reduced value
of the contribution to the surface integration (Gauss law) by the
two side walls needs to be considered. However, as we move
away from the two ends, this effect diminishes and finally, for a
typical long-channel device, it reduces to zero where
(central portion of the channel). In our analysis, this variation is modeled by considering a reduced value of the height of
and
). Further, this efthe side walls at the two ends (
fect becomes more prominent for higher source/drain bias. The
best fit of the model surface potential profile with ISE TCAD
is found for the bias dependent fitting parameter
for the source side and
for
the drain side. In other words, while computing and we use
and
, instead of,
and
respectively. Note that such a function for the fitting parameter is logical in the sense that it is dimensionally correct and also when
, exactly a symmetrical surface potential profile between the source and drain is produced.
in (1) we get
Using
(3)
The complete solution of (3) is given by

(4)
where is a substituted parameter defined as
and
are the two end values of the parameter in the given
region,
and
and
are the boundary
conditions.
Differentiation of (4) gives

(5)
As mentioned earlier, the channel in general, is required to be
divided into three regions with three different sets of parameters
and . However, at any point over the channel, the surface
potential and its derivative are continuous. Based on the channel
length, doping concentration and applied potentials, following
two cases for the three regions are required to be considered.
: This case arises when the channel
Case-1:
is sufficiently large.

509

Fig. 3. Typical variation of depletion layer thickness in a short-channel

MOSFET.

Region-I:
: The corresponding
and
.
values of are
The end potentials are
and
to be evaluated.
: Here the depletion
Region-II:
. The end potentials
layer thickness is constant and equal to
and
at both the ends are to be evaluated.
Region-III:
: The corresponding values
and
. The end
are
to be evaluated and
.
potentials are
: In general, this case arises when
Case-2:
the source and the drain regions are close to each other. The tips
of the two depletion layers (curve 1 and 3) due to source and
drain cross each other as shown in Fig. 3 and the DIBL comes
into effect. The crossing point is simply obtained by equating
,
the two corresponding equations as
and
correspond to the
where the parameters
the
curve 1 and 3 respectively. It is assumed that upto
depletion layer thickness is controlled by the source side and
beyond this it is affected by the drain side and nowhere in the
channel the thickness is constant in contrast to the long-channel
devices. This is nothing but short channel effect. Note that this
case may be treated by dividing the channel into two regions
only. However, to enable the use of the same set of solutions,
we divide the channel into three regions for this case as well.
This is done by either dividing the first part (0 to ) or second
part ( to ) arbitrarily into two regions. In our analysis we
have divided the first part into two regions as follows:
: The corresponding
Region-I:
values are
and
with
and
to be evaluated.
the end potentials
Region-II:
: The corresponding and the
end potential values are same as in region-I.
: The corresponding values
Region-III:
and
with the
are
end potentials
to be evaluated and
.
The complete solution needs to be obtained in all the three
regions. However, it may be noted that, if in a region
is constant, the corresponding parameters are
and
. But then,
becomes
indeterminate. Such a situation is handled by considering the
limiting values of the following product terms:
and
The general division of the channel into the following three
regions leads to the values of the various parameters, boundary
values and
as

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 3, MARCH 2006

Region-I:

Solving (6) and (7) using Cramers rule

:
(8)
Substituting the values of
and
from (8),
three regions may easily be computed.

Region-II:

in all the

III. RESULTS
:

Region-III:
:

Using (5) and applying the continuity of derivative of the potentials at the interface between the region-I and the region-II
we get
(6)
where
and

Similar application of the boundary conditions at the interface

between the region-II and the region-III gives
(7)
where
and

The polysilicon gate MOSFET structure shown in Fig. 1 with

a wide variation of the device dimensions with different technology parameters and biasing conditions is used to verify the
surface potential model against the 2-D numerical device simulator, DESSIS of ISE TCAD. The gate, source, and drain contacts of the MOSFET are made of n-type polysilicon and the
body contact is made of p-type polysilicon. The concentration
used for source and drain contacts are exactly the same as that
regions, so that the corresponding contact drops are exof
actly zero. In order to show the improvement of our model over
the existing ones, comparisons among the surface potential profiles produced by our model, the 2-D device simulator DESSIS
and the model in [3] are made. For the purposes of comparison,
the analytical subthreshold surface potential model for pocket
NMOSFETs in [3] is reduced to a subthreshold surface potential model for uniformly-doped NMOSFETs without using any
fitting parameters.
The 2-D device simulator DESSIS, measures any potential
with respect to the intrinsic Fermi level in the silicon [21]. Acinstead of , where
cordingly, we have also plotted
is the Fermi potential of the p-type substrate. The effective channel length is considered to be the length from the
source-channel metallurgical junction to the drain-channel metallurgical junction. The nonzero penetration of the depletion
layer to n -type source/drain has been ignored. The simulated
data of the surface potential profile are extracted at a depth of
around 0.5 nm from the bottom of the oxide layer.
Fig. 4 shows the surface potential profiles between the source
and drain of a MOSFET for three different technology nodes.
The different technology parameters used for the 130-, 100-,
and 70-nm nodes, for which the surface potential profiles are
shown in Fig. 4(a)-(c), are shown in Table I and chosen to be
within the scaling limits of the ITRS roadmap for analog devices
are shown for
[22]. The profiles for two different values of
each of the technology nodes. The channel doping concentracm while the
tion for all of the devices in Fig. 4 is
V. The
gate and source bias voltages used are
values of the effective channel length used are 100, 80, and
54 nm for the technology node of 130-, 100-, and 70-nm respectively. As evident from Fig. 4, a very good agreement of the
proposed model (solid curve) with the DESSIS (circular symbols) is observed and the agreement is much better than that
of the model in [3] (dotted curve) with DESSIS. The excellent
agreement of the potential minimum predicted by our model
with DESSIS indicates that the DIBL effect prediction by our
model will be far more accurate than that by the model in [3].
A close look at the Fig. 4 also reveals that the mismatch of the
previous model [3] with DESSIS increases as the channel length

BAISHYA et al.: SUBTHRESHOLD SURFACE POTENTIAL MODEL FOR SHORT-CHANNEL MOSFET

511

TABLE I
OXIDE THICKNESS AND JUNCTION DEPTH FOR MOSFETS
OF DIFFERENT TECHNOLOGY NODES

Fig. 4. Surface potential profiles for MOSFETs of three different

technology-nodes with parameter values as shown in Table I. The substrate
doping concentration is
= 6 10 cm and the bias voltages are
=
= 0 V for all the devices. The technology nodes are: (a) 130,
(b) 100, and (c) 70 nm. The model for pocket NMOSFET in [3] is reduced to a
uniformly doped model.

decreases. The reason for this is that, as expected, the error of assuming a constant channel depletion layer neglecting the effect
of source/drain junction on it becomes more and more severe
as one reduces the channel length. The success of our model
lies in the fact that even if a wide range of parameter variations
including the junction depth is made, the accuracy of the profile generated by our model as compared to DESSIS remains
unaltered.
Our model is also verified for variation of different technology parameters like the substrate concentration, channel
length and gate oxide thickness. This is done by varying these

parameters one at a time for the same device as in Fig. 4(b)

along with the same biasing conditions for source and gate
V. In Fig. 5(a), comparisons among the surface
and
potential profiles obtained from our model, DESSIS and model
in [3] for the same device as in Fig. 4(b) but with two other
and
cm
substrate concentrations
are shown. As can be seen from Fig. 5(a) also, that our model
agrees quite well with the DESSIS and the agreement is far
better than that of the model in [3] with DESSIS.
The model is verified against variation in channel length and
oxide thickness next. Fig. 5(b) shows the profiles for devices
and
nm, respectively, keeping all other pawith
rameters unchanged. The surface potential profiles for devices
and nm are shown in Fig. 5(c). It is very clear
with
from Fig. 5(b) and (c) that the agreement of our model with the
DESSIS is very good for different channel lengths as well as
oxide thicknesses.
Once again, a closer look at the surface potential profiles in
all of the figures (Figs. 4 and 5) reveals that, as expected, the
error introduced due to the assumption of constant depletion
layer thickness is more severe for higher applied drain potentials. This is established from the comparison of the surface potential profiles generated by our model and the model in [3] with
that of generated by DESSIS simulation. The accuracy of our
model is obviously due to better modeling of the depletion layer
thickness.
It is important that the prediction of a subthreshold model be
accurate enough for the entire subthreshold region and not for
V only. Our model is applied for nonzero
values
also to test its generality for the entire subthreshold region. The
plots shown in Fig. 6 are generated for the 130 nm technology
device with parameter values and substrate concentrations same
as in Fig. 4(a). Four different nonzero gate voltages (
, and
V) with the drain-to-source bias
V and body bias
V are used. A very good agreement
of our model results with DESSIS is observed in all the four
cases.
For a relatively long-channel device, our model generates the
potential profiles that are flat over a large portion of the channel
length as expected and shown in Fig. 7. A device with
nm,
cm
nm,
nm, and
V is used to generate these plots for
, and V. The good agreement of our model with DESSIS
establishes the fact that our model can be used for long-channel
devices also. Fig. 7 also shows the potential profiles generated
and
by our model for even longer channel lengths,

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 3, MARCH 2006

Fig. 6.

Surface potential profiles for nonzero values of V for a device with

;t
= 3:5 nm, X = 40 nm, V = 0 V,

= 100 nm, N = 6 2 10 cm
= 1 V.
and V
L

Fig. 7. Surface potential profiles for a long-channel device with L = 700 nm,
= 10 cm ; t = 50 nm, X = 250 nm, and V = V = 0 V.
N
Profiles generated by the model for V = 2 V when L is changed to 1500 and
2000 nm are also shown.

IV. PREDICTION OF SUBTHRESHOLD CURRENT

In this section, our surface potential model is used to predict
the subthreshold drain current of a MOSFET. The drift-diffusion model for drain current that is widely used for long-channel
MOSFETs, gives channel current density [4]
Fig. 5. Surface potential profiles for a device with X = 30 nm, V
=
= 0 V, and V = 1 V. All other device parameters are same as the device
V
in Fig. 4(b) except (a) N = 8 10 and 4 10 cm , (b) L = 100 and
150 nm, and (c) t = 2 and 4. The model for pocket NMOSFET in [3] is
reduced to a uniformly doped model.

(9)

nm and
V, other device parameters and bias potentials remaining the same. As the proximity of the source and
drain is reduced, that is, as the channel length is increased, the
decrease in the minimum value of the subthreshold surface po. For
tential due to DIBL effect starts reducing for a given
sufficiently long-channel length, no reduction in this minimum
value, that is, no DIBL occurs. This is clearly demonstrated by
the plots of our model. The excellent agreement of our model
with the device simulator DESSIS for all these variations prove
that the model is accurate enough for wide ranges of device dimensions, technology parameters and applied bias voltages.

In weak inversion, by applying Gausss law at the Si/SiO

interface, the effective channel conduction layer thickness can
be approximated by
(10)
where
and
is the threshold voltage. The
corresponding drain current is obtained as
(11)
where is the effective channel conduction layer thickness that
can be estimated as the distance from the interface to the locais the doping
tion where the potential has changed by
is the channel width.
dependant electron mobility and

BAISHYA et al.: SUBTHRESHOLD SURFACE POTENTIAL MODEL FOR SHORT-CHANNEL MOSFET

513

potential on the junction depth as per the scaling guide lines of

ITRS roadmap and demonstrated the same for three different
technology-node devices. The same model can be used to predict the surface potential for long-channel devices also.
ACKNOWLEDGMENT
The authors would like to thank Prof. V. Ramgopal Rao, IIT
Bombay, India, for his valuable comments and suggestions.

REFERENCES

Fig. 8.

6 2 10

cm

V plots for 130 nm MOSFET with L = 100 nm, N =

; t = 3:5 nm, X = 40 nm, and V = 0 V.

Vs

For long-channel MOSFETs, current computation using

(9)(11) does not produce any appreciable error due to reasons
explained earlier. In this derivation, the contribution of the
portion of the surface potential affected by the source/drain
junction depletion layers is neglected as they constitute a
negligible fraction. However, for short-channel devices, as this
assumption is no longer valid, (10) needs to be modified for
proper prediction of drain current.
We propose to replace by
empirically to predict the subthreshold drain current. With this modification, and using our surface potential
model, the subthreshold current prediction is shown in Fig. 8
for the device parameters as in Fig. 4(a) and the same substrate
doping concentration. The value of the threshold voltage used
is extracted from the device simulator DESSIS by defining the
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reaches
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we see from Fig. 8, the computed current values using our subthreshold surface potential model in (9) compares well with that
predicted by the DESSIS when the device is in weak inversion.
We have tested this for few other cases with different device
parameters and the results obtained were very similar to that
as shown in Fig. 8. Further investigations and necessary modifications of (10) are, however, required for its general acceptability to predict the subthreshold drain current for short channel
devices.
V. CONCLUSION
An improved analytical subthreshold surface potential has
been presented in this paper that accounts for its dependence on
varying depth of the channel depletion layer due to the source
and drain junctions. Our model can predict the surface potential
profile fairly accurately for a wide variation of the device parameters such as substrate concentration, channel length, gate oxide
thickness and also for the different biasing conditions. We have
also been able to accommodate the dependence of the surface

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[23] K. Goel, M. Saxena, M. Gupta, and R. S. Gupta, Two-dimensional analytical threshold voltage model for DMG epi-MOSFET, IEEE Trans.
Electron Devices, vol. 52, no. 1, pp. 2329, Jan. 2005.

Srimanta Baishya (M05) received the B.E. degree

in electrical engineering from Assam Engineering
College, Guwahati, India, and the M.Tech. degree
in electrical engineering from the Indian Institute of
Technology (IIT), Kanpur, India, in 1989 and 1994,
respectively. He is currently pursuing the Ph.D.
degree at Jadavpur University, Kolkata, India.
He is currently an Assistant Professor in the
Department of Electronics and Telecommunication
Engineering, National Institute of Technology (NIT),
Silchar, India. His research interests include the
MOS physics and modeling, technology, and characterizations.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 3, MARCH 2006

Abhijit Mallik (M01) received the M.Sc. degree

in electronics science from Calcutta University,
Calcutta, India, and the Ph.D. degree in electrical
engineering from the Indian Institute of Technology
(IIT), Bombay, India, in 1989 and 1994, respectively.
His doctoral thesis was on the study of reoxidized
nitrided oxide MOS devices for radiation-hard
applications.
He played a key role in developing a radiation
hard chip going up to 1 Mrad(Si) at the IIT Bombay.
He was a Postdoctoral Fellow with the Department
of Electrical Engineering, Yale University, New Haven, CT, from 1994 to 1995,
where he worked on the process development and interface characterization
of jet vapor deposited silicon nitride as an alternative gate insulator for ULSI
applications. He is currently an Assistant Professor in the Department of Electronics and Communication Engineering, Kalyani Government Engineering
College, Kalyani, India. His research interests are in the area of physics,
technology, characterization, and the modeling of CMOS devices.
Dr. Mallik is currently the Vice-Chairperson of IEEE EDS, Calcutta Chapter.

Chandan Kumar Sarkar (SM87) received the

M.Sc. degree in physics from the Aligarh Muslim
University, Aligarh, India, the Ph.D. degree from
Calcutta University, Calcutta, India, and the D.Phil.
degree from the Oxford University, Oxford, U.K. in
1975, 1979, and 1983 respectively.
He was a Research Fellow of the Royal Commission for the exhibition of 1851 at the Clarendon
Laboratory, Oxford University, from 1983 to 1985.
He was also a Visiting Fellow at the Linkoping
University, Linkoping, Sweden. He joined Jadavpur
University, Kolkata, India in 1987 as a Reader in Electronics and Telecommunication Engineering (ETCE) and became Professor and Head at the Physics
Department of the Bengal Engineering College, Howrah, (deemed University)
in 1996. Since 1999 he has been ra Professor and now Head of the ETCE
Department, Jadavpur University. He served as Visiting Professor in many universities and has published around 100 papers in referred journals. He is also a
distinguished Lecturer of the IEEE EDS.
Dr. Sarkar is the Chair of the IEEE EDS Chapter, Calcutta Section, India.