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ELECTRONICS & COMMUNICATION
Digital Electronics
Vol 6 of 10
R. K. Kanodia
Ashish Murolia
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Acknowledgements
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We wish you good luck !
R. K. Kanodia
Ashish Murolia
SYLLABUS
GATE Electronics & Communications
Boolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL,
TTL, ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, code converters,
multiplexers, decoders, PROMs and PLAs. Sequential circuits : latches and flip-flops,
counters and shift-registers. Sample and hold circuits, ADCs, DACs. Semiconductor memories.
Microprocessor(8085): architecture, programming, memory and I/O interfacing.
IES Electronics & Telecommunication
Transistor as a switching element ; Simplification of Boolean functions, Karnaguh map
, Boolean algebra, and applications; IC logic families : DTL, ECL, TTL, NMOS, CMOS
and PMOS gates and their comparison; Full adder , Half adder; IC Logic gates and their
characteristics; Digital comparator; Multiplexer Demultiplexer; Flip flops. J-K, R-S, T and
D flip-flops; Combinational logic Circuits; Different types of registers and counters Waveform
generators. Semiconductor memories.A/D and D/A converters. ROM an their applications.
**********
CONTENTS
CHAP 1
1.1
INTRODUCTION
1.2
1.2.1
1.2.2
2
2
1.3
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
NUMBER SYSTEMS
1.3.1
1.3.2
1.3.3
1.3.4
1.4
Decimal-to-Binary Conversion
5
Decimal-to-Octal Conversion
6
Decimal-to-Hexadecimal Conversion
7
Octal-to-Binary conversion 7
Binary-to-Octal Conversion 7
Hexadecimal-to-Binary Conversion 8
Binary-to-Hexadecimal Conversion 8
Hexadecimal-to-Octal and Octal-to-Hexadecimal Conversion 8
1.5.1
1.5.2
1.5.3
1.5.4
9
9
Binary
Binary
Binary
Binary
Addition
9
Subtraction
Multiplication
Division
9
1.6
COMPLEMENTS OF NUMBERS
1.7
1.7.1
1.7.2
1.7.3
1.8
1.9
10
Sign-Magnitude Representation
1s Complement Representation
2s Complement Representation
11
11
11
12
13
1.8.1
1.8.2
1.8.3
1.8.4
13
13
14
15
HEXADECIMAL ARITHMETIC
1.9.1
1.9.2
1.10
15
OCTAL ARITHMETIC
16
16
16
15
15
1.11
DECIMAL ARITHMETIC
17
BINARY CODES
1.13
17
18
20
BCD ARITHMETIC 20
21
21
1.15
22
1.16
GRAY CODE
23
25
EXERCISE 1.2
31
EXERCISE 1.3
33
SOLUTIONS 1.1
41
SOLUTIONS 1.2
53
SOLUTIONS 1.3
58
23
24
24
INTRODUCTION
2.2
BOOLEAN ALGEBRA
63
2.2.1
2.2.2
63
64
2.3
2.3.1
2.3.2
2.3.3
2.4
2.5
Logic Levels
Truth Table
63
64
66
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
2.4.10
2.4.11
2.4.12
2.4.13
68
Complementation Laws
66
AND Laws
66
OR Laws 66
Commutative Laws
67
Associative Laws
67
Distributive Law
67
Redundant Literal Rule
67
Idempotent Law
67
Absorption Law
67
Consensus Theorem
67
Transposition Theorem
68
De Morgans Theorem
68
Shannons Expansion Theorem
64
65
2.5.1
69
68
2.5.2
2.5.3
2.6
LOGIC GATES
2.6.1
2.6.2
2.7
Principal of Duality
69
Relation Between Complement and Dual
69
Logic Levels
70
Types of Logic Gates
UNIVERSAL GATE
2.7.1
2.7.2
70
75
75
77
2.8
2.9
2.9.1
2.9.2
2.10
69
79
80
80
84
EXERCISE 2.2
105
EXERCISE 2.3
107
SOLUTIONS 2.1
117
SOLUTIONS 2.2
144
SOLUTIONS 2.3
148
82
82
INTRODUCTION
3.2
3.2.1
3.2.2
3.3
Sum-of-Products (SOP)
Product-of-Sum (POS)
155
156
156
3.3.1
3.3.2
3.3.3
3.4
155
Minterm
157
157
S Notation
Converting SOP Form to Standard SOP Form
158
3.4.1
3.4.2
3.4.3
Maxterm 158
159
P Notation
Converting POS Form to standard POS Form
159
3.5
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
3.9
PLOTTING A K-MAP
3.9.1
3.9.2
3.9.3
162
Structure of K-map
163
Another Structure of K-map
Cell Adjacency
165
165
166
166
166
166
160
161
162
3.10
3.10.1
3.10.2
3.10.3
3.10.4
3.11
169
3.12
170
3.13
3.14
166
166
167
168
170
171
3.16
EXERCISE 3.1
173
EXERCISE 3.2
186
EXERCISE 3.3
188
SOLUTIONS 3.1
192
SOLUTIONS 3.2
223
SOLUTIONS 3.3
228
171
171
INTRODUCTION
4.2
4.3
ADDERS
4.3.1
4.3.2
4.4
232
233
235
Half-Subtractor
Full-Subtractor
235
236
4.5
237
4.6
238
4.6.1
4.6.2
4.6.3
238
239
239
Carry Generation
Carry Propagation
Look Ahead Expressions
4.7
SERIAL ADDER
240
4.8
COMPARATOR
241
4.8.1
4.8.2
4.9
4.10
MULTIPLEXER
4.9.1
4.9.2
4.9.3
4.9.4
231
232
Half-Adder
Full-Adder
SUBTRACTORS
4.4.1
4.4.2
231
241
242
244
2-to-1 Multiplexer
245
4-to-1 Multiplexer
245
Implementation of Higher Order Multiplexers using Lower Order Multiplexers
Applications of Multiplexers
247
DEMULTIPLEXER
247
248
249
247
DECODER 251
250
ENCODERS
253
PRIORITY ENCODERS
256
4.14
CODE CONVERTERS
257
4.15
PARITY GENERATOR
259
262
EXERCISE 4.2
281
EXERCISE 4.3
284
SOLUTIONS 4.1
291
SOLUTIONS 4.2
314
SOLUTIONS 4.3
318
252
253
253
254
260
260
INTRODUCTION
5.2
323
5.3
324
5.3.1
5.3.2
5.4
FLIP-FLOPS
5.5.1
5.5.2
5.5.3
5.5.4
5.6
5.4.1
5.4.2
5.5
323
327
S-R Flip-Flop
D-Flip Flop
J-K Flip-Flop
T Flip-Flop
327
328
329
331
TRIGGERING OF FLIP-FLOPS
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
325
326
332
Level Triggering
332
Edge Triggering
332
Edge Triggered S - R Flip Flop
Edge Triggered D Flip-Flop
Edge Triggered J - K Flip-Flop
Edge Triggered T -Flip-Flop
334
336
337
339
5.7
5.8
APPLICATION OF FLIP-FLOPS
5.9
REGISTER
5.9.1
5.9.2
343
Buffer Register
Shift Register
343
344
342
324
5.9.3
5.10
345
COUNTER 345
348
349
EXERCISE 5.1
352
EXERCISE 5.2
369
EXERCISE 5.3
372
SOLUTIONS 5.1
383
SOLUTIONS 5.2
402
SOLUTIONS 5.3
407
345
346
348
348
INTRODUCTION
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.4
Speed of Operation
414
Power Dissipation
415
Voltage Parameters
415
Current Parameters
416
Noise Immunity or Noise Margin
Fan-In
417
Fan-out
417
Operating Temperature
417
Speed Power Product
417
6.4.1
6.4.2
6.5
413
Circuit Operation
Drawbacks of RTL Family
413
416
418
418
418
6.5.1
Circuit Operation
419
6.6
6.7
6.8
6.8.1
6.8.2
6.8.3
Totem-pole Output
Open-collector Output
Tri-state Output
423
6.9
TTL SUBFAMILIES
6.10
419
421
422
422
423
424
425
428
428
427
414
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.12
NMOS Inverter
430
NMOS NAND Gate
431
NMOS NOR Gate
432
Characteristics of MOS Logic
433
6.13.1
6.13.2
6.13.3
6.13.4
6.13.5
6.14
429
429
6.12.1
6.12.2
6.12.3
6.12.4
6.13
I2L Inverter
428
428
I2L NAND Gate
I2L NOR Gate
429
Advantages of I2L
Disadvantages of I2L
CMOS Inverter
434
CMOS NAND Gate
434
CMOS NOR Gate
435
Characteristics of CMOS Logic
436
Advantages and Disadvantages of CMOS Logic
EXERCISE 6.1
439
EXERCISE 6.2
455
EXERCISE 6.3
458
SOLUTIONS 6.1
465
SOLUTIONS 6.2
485
SOLUTIONS 6.3
490
437
437
INTRODUCTION
7.2
7.2.1
7.3
7.4
7.5
496
496
497
497
7.4.1
7.4.2
7.4.3
499
Sample-and-hold circuit
498
Quantization and Encoding
Parameters of ADC
499
ADC CIRCUITS
500
ASTABLE MULTIVIBRATOR
7.6.1
7.6.2
7.6.3
7.7
495
496
ANALOG-TO-DIGITAL CONVERTER
7.5.1
7.5.2
7.5.3
7.5.4
7.6
Parameters of DAC
DAC CIRCUITS
7.3.1
7.3.2
495
503
504
507
507
7.7.1
7.7.2
508
510
433
7.8
SCHMITT TRIGGER
7.8.1
7.8.2
511
EXERCISE 7.1
515
EXERCISE 7.2
532
EXERCISE 7.3
535
SOLUTIONS 7.1
541
SOLUTIONS 7.2
564
SOLUTIONS 7.3
568
512
513
CHAPTER 8 MICROPROCESSOR
8.1
INTRODUCTION
8.2
MICROCOMPUTER
8.2.1
8.2.2
8.2.3
8.3
8.6
572
FETCH
573
EXECUTE
572
573
MICROPROCESSOR ARCHITECTURE
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
571
Memory
572
Input-Output Interfacing
System Bus
572
MICROPROCESSOR OPERATION
8.3.1
8.3.2
8.4
571
System Bus
573
Arithmetic Logic Unit (ALU)
Registers
574
Program Counter (PC)
574
Flags
574
Timing and Control Unit
573
573
574
574
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
576
INSTRUCTION SET
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
577
EXERCISE 8.1
589
EXERCISE 8.2
602
EXERCISE 8.3
605
SOLUTIONS 8.1
609
SOLUTIONS 8.2
621
SOLUTIONS 8.3
625
577
579
581
584
587
***********
Sample Chapter of
Digital Electronics
Page 63
Chap 2
CHAPTER 2
2.1
i. n
INTRODUCTION
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This chapter, concerned with the basic study of Boolean algebra and
simplification theory, includes the following topics:
Various types of logic gates: AND, OR, NOT, NAND, NOR, XOR,
XNOR gates.
.
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2.2
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BOOLEAN ALGEBRA
2.2.1
Logic Levels
Boolean logic variable 0 or 1 is not used to represent actual numbers
but it is used to represent the state of voltage variable called logical
level. Commonly used representation of logic levels are shown in Table
below.
Table 2.1: Representation of Logic Levels for Boolean Variables
Logic 0
Logic 1
False
True
Open switch
Close switch
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Boolean Algebra and
Logic Simplification
2.2.2
Logic 0
Logic 1
Low
High
No
Yes
OFF
ON
Truth Table
A truth table represents the relation between all inputs and possible
outputs of any logic device or logic circuit in a tabular form. The
number of inputs may vary from one to many depending upon the
device or complexity of the circuit. Number of output also varies in this
way and may be one or more. For different digital circuits, some of the
examples of truth table are given below.
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Table 2.2: Examples of Truth Tables for 1-input, 2-input and 3-input
Circuits
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2.3
2.3.1
2.
AND operation
3.
NOT operation
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Page 65
Chap 2
Boolean Algebra and
Logic Simplification
Input
Output
Y = A+B
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NOTE :
The minimum number of inputs for OR operation is two. The number of outputs
is always one, irrespective of the number of inputs.
2.3.2
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Input
Output
Y = AB
NOTE :
The minimum number of inputs for AND operation is two. The number of output
is always one, irrespective of the number of inputs.
2.3.3
Logical NOT
NOT is the simplest of the three basic operations of Boolean algebra.
It is also known as inversion and complement. The NOT operation is
indicated by a bar - over the variable. If A is a variable, then NOT
of A is expressed as A . The truth Table of the NOT operation is shown
in Table 2.5.
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Chap 2
Boolean Algebra and
Logic Simplification
Input
Output
Y=A
NOTE :
Logical NOT is the only Boolean operation which must be performed with only
one operand or one input. Note that in some texts, the NOT operation is also
presented as Al .
2.4
2.4.1
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Complementation Laws
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2.
If A = 0 , then A = 1
3.
If A = 1, then A = 0
4.
5.
2.4.2
AND Laws
The four AND laws are as follows:
1. Null Law: A : 0 = 0
2.4.3
2.
Identity Law: A : 1 = A
3.
A:A = A
4.
A:A = 0
OR Laws
The four OR laws are as follows:
1. Null Law: A + 0 = A
2.
Identity Law: A + 1 = 1
3.
A+A = A
4.
A+A = 1
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2.4.4
Commutative Laws
Commutative law states that the order of the variable in OR and AND
operations is not important. The two commutative laws are
Page 67
Chap 2
Boolean Algebra and
Logic Simplification
A+B = B+A
A:B = B:A
2.4.5
Associative Laws
Associative law states that the grouping of variables in AND or OR
expression does not affect the result. There are two associative laws.
A + _B + C i = _A + B i + C
A : _B : C i = _A : B i : C
2.4.6
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Distributive Law
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A _B + C i = AB + AC
A + BC = _A + B i_A + C i
2.4.7
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This law states that ORing of a variable with the AND of the
complement of that variable with another variable, is equal to ORing
of the two variables, i.e.
A + AB = A + B
Another theorem based on this law is
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2.4.8
A _A + B i = AB
Idempotent Law
Idempotence means the same value. There are two idempotent laws
A : A : A :g: A = A
A+A+A+g+A = A
2.4.9
Absorption Law
There are two absorption laws
A+A:B = A
A : _A + B i = A
2.4.10
Consensus Theorem
There are two consensus theorems,
AB + AC + BC = AB + AC
_A + B i_A + C i_B + C i = _A + B i_A + C i
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2.4.11
Transposition Theorem
There are two transposition theorems, the first is given as
AB + AC = _A + C i_A + B i
_A + B i : _A + C i = A : C + A : B
2.4.12
De Morgans Theorem
De Morgans theorem gives two of the most powerful laws in Boolean
algebra. These theorems are very useful in simplification of Boolean
expressions,
A+B = A B
AB = A + B
2.4.13
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2.5
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5. Look for pairs of terms which have the same variables, except in
one term a variable is complemented and in other term is it not.
Such terms can be combined into a single terms. For example,
Page 69
Chap 2
Boolean Algebra and
Logic Simplification
2.5.1
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1. Change all the ANDs to ORs and all the ORs to ANDs i.e.,
change all : to + and all + to :
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2.5.2
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Principal of Duality
2.5.3
The above relation states that the dual can be obtained by complementing all the
literals in complement function f ^A, B, C, ....h .
2.6
LOGIC GATES
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Chap 2
Boolean Algebra and
Logic Simplification
2.6.1
Logic Levels
Inputs and outputs of logic gates can occur only in two levels. These
two levels are termed HIGH and LOW, or TRUE and FALSE, or ON
and OFF, or simply 1 and 0. There are two different ways to assign a
signal value to logic level such as positive logic and negative logic.
1. Positive Logic: If higher of the two voltage levels represents a logic
1 and the lower of the two levels represents a logic 0, then the
logic system is referred to as a positive logic system. Figure 2.1
shows the positive logic system.
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2.6.2
AND gate,
3.
NOT gate
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Other logic gates that are derived from these basic gates are
1. NAND gate,
Page 71
Chap 2
Boolean Algebra and
Logic Simplification
2.
NOR gate,
3.
EXCLUSIVE-OR gate,
4.
EXCLUSIVE-NOR gate
AND Gate
An AND gate is a logic circuit with two or more inputs and one output
that performs ANDing operation. The output of an AND gate is HIGH
only when all of its inputs are in the HIGH state. In all other cases, the
output is LOW. For a positive logic systems, it means that the output
of the AND gate is a logic 1 only when all of its inputs are in logic 1
state. In all other cases, the output is logic 0. The logic symbol and
the truth table of a two-input AND gate are shown in Figure 2.3 and
Table 2.6 respectively.
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Input
Output
Y = AB
OR Gate
An OR gate is a logic circuit with two or more inputs and one output
that performs ORing operation. The output of an OR gate is LOW
only when all of its inputs are LOW. For all other possible input
combinations, the output is HIGH. For a positive logic system, the
output of an OR gate is a logic 0 only when all of its inputs are at
logic 0. For all other possible input combinations, the output is a logic
1. The logic symbol and the truth table of a two-input OR gate are
shown in Figure 2.4 and Table 2.7 respectively.
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Chap 2
Input
Output
Y = A+B
NOT Gate
A NOT gate, also called an inverter is a one-input, one-output logic
circuit whose output is always the complement of the input. That is,
a LOW input produces a HIGH output, and vice versa. It means that
for a positive logic system, a logic 0 at the input produces a logic 1
at the output, while a logic 1 at the input produces a logic 0 output.
It is also known as a complementing circuit or an inverting circuit. The
logic symbol and the truth table of an inverter are shown in Figure 2.5
and Table 2.8 respectively.
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Input
Output
Y=A
NAND Gate
The term NAND implies NOT-AND. A NAND gate is equivalent to
AND gate followed by a NOT gate. The standard logic symbol for a
2-input NAND gate is shown in Figure 2.6. This symbol is same as
AND gate symbol except for a small circle (bubble) on its output. This
circle represents the NOT function.
The truth Table 2.9 of a NAND gate is obtained from the truth
Table of an AND gate by complementing the output entries. The
output of a NAND gate is a logic 0 when all its inputs are a logic 1.
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For all other input combinations, the output is a logic 1. NAND gate
operation is logically expressed as
Page 73
Chap 2
Boolean Algebra and
Logic Simplification
Y = A:B
Table 2.9: Truth Table of a 2-input NAND Gate
Input
Output
Y = AB
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NOR Gate
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The truth Table 2.10 of a NOR gate is obtained from the truth
Table of an OR gate by complementing the output entries. The output
of a NOR gate is a logic 1 when all its inputs are logic 0. For all other
input combinations, the output is a logic 0. The output of a two-input
NOR gate is logically expressed as
Y = A+B
Input
Output
Y = A+B
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Boolean Algebra and
Logic Simplification
Input
Output
Y = A5B
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From the truth table it can be stated that, the output of an EXOR gate is a logic 1 when the two inputs are at different logic and a
logic 0 when the two inputs are at the same logic.
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NOTE :
1.
2.
The exclusive-OR and equivalence gates both can be extended to more than
two inputs. However, multiple-input exclusive OR gates are uncommon from
the hardware standpoint.
For a multiple output-input EX-OR logic function we can conclude that the
output of a multiple-input EX-OR logic function is a logic 1 only when an
odd number of input variables are 1.
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Input
Output
Y = A9B
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Boolean Algebra and
Logic Simplification
1.
2.
Likewise Ex-OR gates, three or more variable Ex-NOR gates also do not exist.
Normally, multiple-input EX-NOR logic functions can be implemented using
more than one 2-input Ex-NOR gates.
For a multiple output-input EX-NOR logic function we can conclude that the
output of a multiple-input EX-NOR logic function is a logic 1 only when
an even number of input variables are 0. Note if all inputs are 0, then also
output will be 1.
2.7
i. n
UNIVERSAL GATE
o
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a
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d
NAND and NOR gates are known as universal gates because any of
these two gates is capable of implementing all other gate functions.
2.7.1
o
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The NAND gate can be used to implement the NOT function, AND
function, the OR function and other functions also as explained below.
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Page 76
Chap 2
Boolean Algebra and
Logic Simplification
A=A
in
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= A:B
A=A
The above equation is implemented using only NAND gates, as
shown in the Figure 2.13.
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X=X
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Page 77
Chap 2
Boolean Algebra and
Logic Simplification
i. n
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2.7.2
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Page 78
Chap 2
Boolean Algebra and
Logic Simplification
in
.
o
= A:B
A=A
(DeMorgans Theorem)
= A+B
The above equation is implemented using only NOR gates as
shown in the Figure 2.18.
c
.
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d
o
Y = A:B
= A+B
n
.
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(DeMorgans Theorem)
= A+B
A=A
The above equation is implemented using only NOR gates, as
shown in the Figure 2.19.
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Digital Electronics
Page 79
Chap 2
Boolean Algebra and
Logic Simplification
_AA = BB = 0i
= A _A + B i + B _A + B i = A _A + B i + B _A + B i
= _A + A + B i + _B + A + B i
= _A + A + B i + _B + A + B i
_X = X i
The above expression can be realized using five NOR gates as
shown in Figure 2.20.
i. n
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2.8
We have discussed the five basic logic gates (AND, OR, INVERTER,
NAND, and NOR) and the standard symbols used to represent them
in a logic circuit diagram. Most of the logic networks use standard
symbols. But in some networks an alternative set of symbols is used in
addition to the standard symbols. Table 2.13 shows the alternate set of
symbols for the five basic gates.
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Chap 2
Boolean Algebra and
Logic Simplification
Logic
Normal Symbol
Alternate symbol
NOT
AND
OR
NAND
NOR
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Step 1:
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Step 2:
Step 3:
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2.9
2.9.1
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Step 1:
Step 2:
Page 81
Chap 2
Boolean Algebra and
Logic Simplification
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Step 3:
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2.9.2
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Chap 2
Boolean Algebra and
Logic Simplification
2.10
TO
CONVERT
LOGIC
DIAGRAM
TO
BOOLEAN
Step 1:
Step 2:
Step 3:
The outputs of the OR gate and AND gate are the inputs
of right-most AND gate. Therefore, the expression for
this AND gate is _A + B i : CD , which is the final output
expression for the entire circuit.
in
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Since, NAND logic and NOR logic are universal logic system, digital
circuits which are first computed and converted to AOI logic may then
be converted to either NAND logic or NOR logic depending on the
choice.
2.10.1
NAND-NAND Logic
A logic network can be converted into NAND-NAND gate network by
going through following steps:
METHODOLOGY: TO OBTAIN NAND-NAND GATE NETWORK
Step 1:
Step 2:
Step 3:
Step 4:
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Digital Electronics
NOR-NOR Logic
The procedure of converting an AOI logic to NOR-NOR logic is same
as above except steps 2 and 4.
Page 83
Chap 2
Boolean Algebra and
Logic Simplification
Step 1:
Step 2:
Step 3:
Step 4:
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EXERCISE 2.1
Page 84
Chap 2
Boolean Algebra and
Logic Simplification
MCQ 2.1.1
in
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(A) (A + B ) (C + D ) (E + F)
(B) AB + CD + EF
(C) (A + B) (C + D) (E + F)
c
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(D) AB + CD + EF
MCQ 2.1.2
d
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MCQ 2.1.3
(A) MNQ
(B) N (Q + M )
(C) M (Q + N )
(D) Q (M + N )
(A) AB + (C + D) E
(B) AB (C + D) E
(C) AB + CD + E
(D) AB + CDE
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MCQ 2.1.4
Digital Electronics
MCQ 2.1.5
Page 85
Chap 2
Boolean Algebra and
Logic Simplification
(D) XY
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(A) A + B + C
(B) ABC
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(C) AB + BC + AC
MCQ 2.1.6
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(C) (A + B ) (A + C )
MCQ 2.1.7
MCQ 2.1.8
(D) (A + B ) (A + C )
(A) AB
(B) AB
(C) AB
(D) 0
(A) AB + AB + C
(B) AB + AB + C
(C) AB + AB + C
(D) AB + AB + C
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Chap 2
MCQ 2.1.9
MCQ 2.1.10
MCQ 2.1.11
(A) ABC
(B) ABC
(C) ABC
(D) 0
in
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(A) ABC
(B) AB (C + B)
(C) ABC
(D) AB (C + B)
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(A) ABC
(B) ABC
(C) 0
(D) ABC
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MCQ 2.1.12
(B) BC + ABC
(C) BC
(D) ABC
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MCQ 2.1.13
MCQ 2.1.14
Digital Electronics
A + BC is equivalent to
(A) (A + B) (A + C )
(B) A + B
(C) A + C
(D) (A + B ) (A + C )
o
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(C) (A + B) (B + C )
.
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(A) (A + B ) (B + C )
(B) (A + B ) (B + C )
(D) Above all
MCQ 2.1.16
Page 87
Chap 2
MCQ 2.1.15
(A) B (A + C) (A + C )
(B) B (A + C ) (A + C )
(C) B (A + C ) (A + C )
(D) B (A + C ) (A + C )
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Chap 2
MCQ 2.1.17
MCQ 2.1.18
MCQ 2.1.19
(D) AB
in
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(B) A + B
(C) AB + AB
c
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(D) A B + AB
MCQ 2.1.20
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(C) 0
MCQ 2.1.21
MCQ 2.1.22
d
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If XY + XY = Z then XZ + X Z is equal to
(B) Y
(A) Y
If XY = 0 then X 5 Y is equal to
(A) X + Y
(B) X + Y
(C) XY
(D) XY
If A = 0 in logic expression Z = [A + EF + BC + D] [A + DE + BC + DE ]
, then
(A) Z = 0
(B) Z = 1
(C) Z = BC
MCQ 2.1.23
(D) 1
(D) Z = BC
(D) 0
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MCQ 2.1.24
Digital Electronics
Page 89
Chap 2
Boolean Algebra and
Logic Simplification
(A) A = 0, B = 0
(B) A = 1, B = 0
(C) A = 0, B = 1
i. n
(D) Either A = 1 or B = 1
MCQ 2.1.25
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MCQ 2.1.26
The output of logic circuit is HIGH whenever A and B are both HIGH
as long as C and D are either both LOW or both HIGH. The logic
circuit is
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Chap 2
MCQ 2.1.27
MCQ 2.1.28
in
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(C) 4 units
MCQ 2.1.29
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MCQ 2.1.30
(D) 6 units
(D) 6 units
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MCQ 2.1.31
Digital Electronics
Page 91
Chap 2
Boolean Algebra and
Logic Simplification
MCQ 2.1.32
(A) X
(B) X
(C) 0
(D) 1
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MCQ 2.1.33
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Chap 2
MCQ 2.1.34
MCQ 2.1.35
(A) M1 = (P OR Q) XOR R
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(C) 6
MCQ 2.1.36
in
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(D) 7
d
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(B) The more negative of the two logic levels represents a logic 0
state
(C) All input and output voltage levels are negative
(D) The output is always complement of the intended logic function
w
MCQ 2.1.37
IES EE 1992
MCQ 2.1.38
IES EC 2002
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Sample Chapter of
MCQ 2.1.39
Digital Electronics
Match List-I with List-II and select the correct answer using the codes
given below the lists.
List - I
List - II
a.
A5B = 0
1.
A=
YB
b.
A+B = 0
2.
A=B
c.
A:B = 0
3.
A = 1 or B = 1
d.
A5B = 1
4.
A = 1 or B = 0
MCQ 2.1.40
IES EE 1999
a
3
2
3
2
b
2
3
2
3
c
1
4
4
1
d
4
1
1
4
i. n
Codes :
(A)
(B)
(C)
(D)
Page 93
Chap 2
o
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.
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(2) A NOR gate is equivalent to an AND gate with its inputs inverted.
(3) A NAND gate is equivalent to an OR gate with its output inverted.
(4) A NOR gate is equivalent to an AND gate with its output inverted.
MCQ 2.1.41
(D) 1 and 4
The output (X ) waveform for the combination circuit shown below for
the inputs at A and B (waveform shown in the figure) will be
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Chap 2
Boolean Algebra and
Logic Simplification
in
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MCQ 2.1.42
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MCQ 2.1.43
Digital Electronics
Page 95
Chap 2
Boolean Algebra and
Logic Simplification
i. n
i
d
o
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o
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MCQ 2.1.44
MCQ 2.1.45
(D) M + B
(A) Ex-NOR
(B) AND
(C) Ex-OR
(D) NOR
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Chap 2
MCQ 2.1.46
MCQ 2.1.47
The elevator door should open if the elevator is stopped, it is level with
the floor, and the timer has not expired, or if the elevator is stopped,
it is level with the floor, and a button is pressed. If
D " Elevator door opens ; S " Elevator is stopped ;
F " Level with floor ; T " Timer expired ; B " Button pressed
Which of the following Boolean expression represents the above
condition ?
(A) D = SFT l + SFB
(B) D = SFT l B
(C) D = SF + T l B
(D) D = (S + F ) T l B
MCQ 2.1.48
in
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MCQ 2.1.49
(A) AD (B + C ) + A D
(B) AD (B 5 C ) + A D
(C) AD (B 5 C ) + A D
(D) A D (B 5 C ) + AD
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MCQ 2.1.50
Digital Electronics
Page 97
Chap 2
Boolean Algebra and
Logic Simplification
(C) AD
(D) A + D
MCQ 2.1.51
i. n
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n
(A) NOR
.
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(C) Ex-OR
MCQ 2.1.52
IES EE 1995
i
d
o
c
.
a
(B) NAND
(D) OR
(A) L = (A + B) (C + D) E
(B) L = AB + CD + E
(C) L = E + (A + B) (C + D)
(D) L = (AB + CD) E
MCQ 2.1.53
IES EE 2005
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Chap 2
MCQ 2.1.54
MCQ 2.1.55
IES EC 1996
in
.
o
c
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d
o
(A) AB + AC = AC + AB
(B) (A + B) + (A + C) = (A + C) (A + B)
n
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(C) (A + B) (A + C) = AC + AB
(D) AB + AC = AB + AC + BC
MCQ 2.1.56
MCQ 2.1.57
IES EE 2004
MCQ 2.1.58
(D) A [B _A + C i] D
(D) 1
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MCQ 2.1.59
Digital Electronics
Page 99
Chap 2
Boolean Algebra and
Logic Simplification
i. n
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d
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MCQ 2.1.60
IES EC 1992
o
c
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Chap 2
Boolean Algebra and
Logic Simplification
MCQ 2.1.61
in
.
o
c
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d
o
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.
w
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Which of the following give correct values of A0, A1, A2, A3, A4, A5, A6,
A7, A8 , and A9 in order to move motor ?
(A) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = A8 = A9 = 1
(B) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A9 = 1; A7 = A8 = 0;
(C) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = 1 ; A8 = A9 = 0
(D) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = A8 = 1 ; A9 = 0
MCQ 2.1.62
When two gates with open collector outputs are tied together as shown
in the figure, the output obtained will be
(A) A + B + C + D
(B) A + B + C + D
(C) (A + B ) + (C + D )
(D) (A + B) + (C + D)
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Digital Electronics
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Chap 2
Boolean Algebra and
Logic Simplification
(C) F D
(D) F
i. n
(B) 2
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(C) 3
(D) 4
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(A) 1
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MCQ 2.1.64
GATE EE 2002
For the circuit shown in Figure, the Boolean expression for the output
Y in terms of inputs P , Q , R , and S is
(A) P + Q + R + S
(B) P + Q + R + S
(C) (P + Q ) (R + S )
(D) (P + Q) (R + S)
MCQ 2.1.65
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Boolean Algebra and
Logic Simplification
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MCQ 2.1.66
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Page 103
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Boolean Algebra and
Logic Simplification
i. n
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o
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MCQ 2.1.67
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Chap 2
Boolean Algebra and
Logic Simplification
in
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MCQ 2.1.68
d
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(B) Identical
(C) Complementary
(D) Dual
***********
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EXERCISE 2.2
QUES 2.2.1
IES EC 2003
QUES 2.2.2
IES EC 2006
Page 105
Chap 2
Boolean Algebra and
Logic Simplification
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QUES 2.2.3
QUES 2.2.4
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QUES 2.2.5
QUES 2.2.6
In circuit shown below, for what input at the terminal A the output
is X = 1 ?
QUES 2.2.7
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Chap 2
QUES 2.2.8
QUES 2.2.9
QUES 2.2.10
QUES 2.2.11
QUES 2.2.12
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EXERCISE 2.3
MCQ 2.3.1
K
SHASHIDHAR
214/12
MCQ 2.3.2
K
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214/13
MCQ 2.3.3
K
SHASHIDHAR
214/14
MCQ 2.3.4
Page 107
Chap 2
Boolean Algebra and
Logic Simplification
The NAND gate can perform the invert function if the inputs are
(A) Connected together
(B) Left open
(C) Either (A) or (B)
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(C) OR
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(D) NOR
(D) NOR
K
SHASHIDHAR
214/15
MCQ 2.3.5
K
SHASHIDHAR
214/16
(D) NAND
In positive logic,
(A) a HIGH = 1, a LOW = 0
(B) a LOW = 1, a HIGH = 0
(C) Only HIGHs are present
(D) Only LOWs are present
MCQ 2.3.6
K
SHASHIDHAR
214/17
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Chap 2
Boolean Algebra and
Logic Simplification
MCQ 2.3.7
K
SHASHIDHAR
214/18
MCQ 2.3.8
K
SHASHIDHAR
214/19
MCQ 2.3.9
K
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214/20
MCQ 2.3.10
K
SHASHIDHAR
214/21
(D) 8
(D) 8
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MCQ 2.3.11
K
SHASHIDHAR
214/22
(B) A = 0 , B = 0 , C = 0
(C) A = 1, B = 1, C = 1
(D) A = 1, B = 0 , C = 1
MCQ 2.3.12
K
SHASHIDHAR
214/23
(B) A = 0 , B = 0 , C = 1
(C) A = 0 , B = 1, C = 1
(D) All of the above
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MCQ 2.3.13
K
SHASHIDHAR
215/25
MCQ 2.3.14
K
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215/27
Digital Electronics
(A) 1
(B) 2
(C) 7
(D) 8
K
SHASHIDHAR
215/32
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Boolean Algebra and
Logic Simplification
(A) 2
(B) 4
(C) 6
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(D) 8
MCQ 2.3.15
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(A)
(B)
(C)
(D)
negative-OR gate
negative-AND gate
negative-NAND gate
none of the above
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MCQ 2.3.16
K
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MCQ 2.3.17
K
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MCQ 2.3.18
K
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216/38
How many two-input NOR gates does it take to produce a twoinput NAND gate ?
(A) 1
(B) 2
(C) 3
(D) 4
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Chap 2
Boolean Algebra and
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MCQ 2.3.19
V K PURI
94/1
MCQ 2.3.20
V K PURI
95/13
MCQ 2.3.21
V K PURI
95/16
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MCQ 2.3.22
B.R. GUPTA
73/521
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A buffer is
(A) always non-inverting
(B) always inverting
MCQ 2.3.23
B.R. GUPTA
83/522
MCQ 2.3.24
B.R. GUPTA
85/522
(A) AND
(B) OR
(C) NAND
(D) NOR
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MCQ 2.3.25
B.R. GUPTA
94/522
Digital Electronics
MCQ 2.3.26
MAINI
1/102
MAINI
4/103
(D) Ex-NOR
i. n
In general, logic gates whose all output entries are logic 1 except for
one entry that is logic 0 are
(A) AND, OR
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(C) NAND, OR
MAINI
8/103
For a certain two-input logic gate, the output is 1 for like inputs and
0 for unlike inputs. The logic gate is
(A) Ex-OR
(B) NAND
MCQ 2.3.28
Page 111
Chap 2
(C) NOR
MCQ 2.3.27
MCQ 2.3.29
MAINI
4/200
MCQ 2.3.30
MAINI
5/200
Complement of complement of Al : B + A : B l is
(A) A : B + Al : B l
(B) _Al + B i : _A + B li
(C) Al : B + A : B l
(D) None of these
MCQ 2.3.31
The operation A : A =
(A) A 2
(B) 2A
(C) 1
(D) A
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Chap 2
Boolean Algebra and
Logic Simplification
MCQ 2.3.32
Chakravorty
M4.10/111
MCQ 2.3.33
Chakravorty
M4.11/111
MCQ 2.3.34
Chakravorty
M4.12/111
MCQ 2.3.35
Chakravorty
M6.1/170
The operation A + A =
(A) A 2
(B) 2A
(C) 0
(D) A
The operation A + A =
(A) 1
(B) A
(C) 0
(D) A
The operation A : A =
(A) 1
(B) A
(C) 0
(A) A
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MCQ 2.3.36
d
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Chakravorty
M6.6/171
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MCQ 2.3.37
in
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(B) OR gate
Chakravorty
M6.7/171
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Digital Electronics
Page 113
Chap 2
Chakravorty
M6.8/171
MCQ 2.3.39
(B) OR gate
i. n
Chakravorty
M6.9/171
i
d
(B) OR gate
(C) NAND gate
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MCQ 2.3.40
MANDAL
1/72
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MCQ 2.3.41
MANDAL
2/72
MCQ 2.3.42
MANDAL
3/72
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Chap 2
Boolean Algebra and
Logic Simplification
MCQ 2.3.43
MANDAL
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MCQ 2.3.44
ANAND KUMAR
10/21
MCQ 2.3.45
ANAND KUMAR
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ANAND KUMAR
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w
(B) AND and NOT gates are necessary and sufficient for realization of
any logic function.
(C) NAND gates are not sufficient to realize any logic function.
(D) NOR gates are sufficient to realize any logic function.
MCQ 2.3.47
For the gate shown in the figure, the output will be HIGH
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Sample Chapter of
MCQ 2.3.48
ANAND KUMAR
25/67
Digital Electronics
Page 115
Chap 2
Boolean Algebra and
Logic Simplification
MCQ 2.3.49
ANAND KUMAR
63/137
ANAND KUMAR
65/138
o
c
.
a
MCQ 2.3.51
i
d
o
n
.
w
w
(D) X-OR
(D) AB
MCQ 2.3.52
ANAND KUMAR
2/192
MCQ 2.3.53
A + AB + A BC + A B C D + .... =
(A) A + B + C + ...
(B) A + B + C + D + ...
(C) 1
(D) 0
The number of table entries needed for a five input logic circuit is
(A) 4
(B) 8
(C) 16
MCQ 2.3.54
ANAND KUMAR
15/192
i. n
(C) NOR
MCQ 2.3.50
ANAND KUMAR
1/192
(D) 32
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Boolean Algebra and
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MCQ 2.3.55
ANAND KUMAR
16/192
MCQ 2.3.56
SEDHA
7/118
MCQ 2.3.57
in
.
o
c
.
ia
d
o
MCQ 2.3.58
SEDHA
1/183
MCQ 2.3.59
SEDHA
15/184
MCQ 2.3.60
KHARATE
7/197
n
.
w
w
(D) numbers
X + XY is reduced to
(A) X
(B) X + Y
(C) X + Y
(D) X + Y
***********
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Sample Chapter of
Digital Electronics
SOLUTIONS 2.1
SOL 2.1.1
Page 117
Chap 2
Boolean Algebra and
Logic Simplification
i. n
o
c
.
a
i
d
o
n
i.e.
AND-Invert = Invert-OR
By converting AND Invert logic to equivalent Invert-OR logic in the
given circuit diagram, we get
.
w
w
SOL 2.1.2
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Page 118
Chap 2
Boolean Algebra and
Logic Simplification
i.e.
AND-Invert = Invert-OR
Applying the property, we have the modified logic circuit as
in
.
o
c
.
ia
d
o
X = MNQ + MNQ + M NQ
n
.
w
w
w
SOL 2.1.3
= MQ _N + N i + M NQ
= MQ + M NQ
= Q _M + M N i
= Q _M + N i
or
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Page 119
Chap 2
Boolean Algebra and
Logic Simplification
SOL 2.1.4
i. n
o
c
.
a
o
n
i
d
SOL 2.1.5
.
w
w
= _X + Y i_XY + X Y i
= XY + XY
= XY
Z = A + _AB + BC i + C
= A+A+B+B+C+C
= A+B+C
4
= ABC
From the above logic function, we can observe that options (A) and (B)
are matched. Now, we check the expression given in option (C).
Z = AB + BC + AC
= A+B+B+C+A+C
= A+B+C
Hence, all the options are same, and equal to the output Z of the given
logic circuit.
SOL 2.1.6
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AB + AC + BC
S
Page 120
Chap 2
= AB + AC
redundant
term
Hence,
SOL 2.1.7
SOL 2.1.8
Y = _A 5 B i : C
c
.
ia
= _AB + AB i : C
= _AB + AB i + C
= _AB + A B i + C
= A B + AB + C
SOL 2.1.9
in
.
o
d
o
n
.
w
w
{A + A = 1}
{B : B = 0 }
w
SOL 2.1.10
SOL 2.1.11
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SOL 2.1.12
Digital Electronics
SOL 2.1.13
Page 121
Chap 2
Boolean Algebra and
Logic Simplification
{A + A = 1}
i. n
SOL 2.1.14
A+C
_A + B i_A + C i
A + BC
A+B
o
n
0
.
w
w
i
d
o
c
.
a
= A+B+C
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Page 122
Chap 2
SOL 2.1.15
SOL 2.1.16
AC + BC = AC _B + B i + BC _A + A i
AC + BC = ABC + ABC + ABC + ABC
SOL 2.1.17
in
.
o
c
.
a
= A + A 8B + B #C + C _D + DE i-B
Using redundant literal rule, we have
...(1)
i
d
A + AB = A + B
or
A + A _B + C i = A + B + C
Applying this rule in equation (1), we get
o
n
.
w
w
A + AB + A BC + A B C D + A B C DE
w
SOL 2.1.18
= A + A 7B + B #C + C _D + E i-A
= A + A #B + B _C + D + E i= A + A _B + C + D + E i
= A+B+C+D+E
Y = AB + AC 7_A + B i_A + C iA
= AB + AC _A + A C + A B + B C i
= AB
SOL 2.1.19
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SOL 2.1.20
Page 123
Chap 2
Boolean Algebra and
Logic Simplification
o
c
.
a
= Y _X + X i
=Y
SOL 2.1.21
i
d
o
n
.
w
w
i. n
X 5 Y = XY + XY
X5Y = X9Y
So, by using the given condition, we get
w
or
SOL 2.1.22
X 5 Y = XY + XY = _XY + X Y i
X5Y = X Y = X+Y
(XY = 0 )
Z = 7A + EF + BC + DA7A + D E + BC + D F A
= 7A + BC + EF + DA7A + BC + D _E + F iA
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Chap 2
SOL 2.1.23
SOL 2.1.24
in
.
o
F = _Y + X i Y
= Y + XY = Y _1 + X i = Y
= A + _A + B i
= A : _A + B i
= AA + AB
= AB
Thus, we may conclude that
F = 1 for A = 0 and B = 1
c
.
ia
d
o
SOL 2.1.25
n
.
w
w
1. For B = C :
P = B5C = 0
and
X = A+0 = A
i.e. Output X will equal A when control input B and C are the same.
2. For B ! C :
P = B5C = 1
and
X = A+1 = 1
i.e. X will remain HIGH when B and C are different.
Hence, the circuit satisfies both the requirements.
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Sample Chapter of
SOL 2.1.26
Digital Electronics
Page 125
Chap 2
Boolean Algebra and
Logic Simplification
Given that C and D are either both LOW or both HIGH. For the
circuit given in option (A), if C and D inputs are either both high
or both low, i.e. C = D applied to XNOR gate then
C 9 D = 1 for C = D
i.e. another input of last AND gate will be High.
i. n
Thus, the circuit given in option (A) is HIGH whenever A and B are
both HIGH as long as C and D are either both LOW or both HIGH.
SOL 2.1.27
o
c
.
a
i
d
o
n
.
w
w
*Maximum Discount*
Page 126
Chap 2
Boolean Algebra and
Logic Simplification
SOL 2.1.28
in
.
o
c
.
ia
SOL 2.1.29
d
o
n
.
w
w
Z = ABC
To implement the function using using only NAND gates, we draw the
logic circuit as
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Sample Chapter of
SOL 2.1.30
Digital Electronics
3.
4.
Page 127
Chap 2
Boolean Algebra and
Logic Simplification
So there can not be both input High to NAND. Therefore, LED does
not emit light irrespective of the switch positions.
SOL 2.1.31
i. n
i
d
o
n
SOL 2.1.32
.
w
w
o
c
.
a
Output of gate 2 = X0 X1 + X2
Output of gate 3 = _X0 X1 + X2i X3
= X0 X1 X3 + X2 X3
Similarly, we may deduce
Output of gate 4 = X0 X1 X3 + X2 X3 + X4
Output of gate 5 = _X0 X1 X3 + X2 X3 + X4i X5
= X0 X1 X3 X5 + X2 X3 X5 + X4 X5
Hence, the output of gate n would be
F = X0 X1 X3 X5 .........Xn + X2 X3 X5 .........Xn + X4 X5 X7 ..........Xn + ........ + Xn - 1 Xn
SOL 2.1.33
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Chap 2
Boolean Algebra and
Logic Simplification
SOL 2.1.34
and
and
Hence,
SOL 2.1.35
in
.
o
c
.
ia
Z = X : Y = _PQ i_P + Q i
= _P + Q i_P + Q i
= PQ + PQ = P 5 Q
M1 = Z 5 R
d
o
M1 = _P 5 Q i 5 R
M1 = _P XOR Q i XOR R
n
.
w
w
Now, we may prove that the above logic circuit implements an XOR
gate
Z = $_XY i X . : $_XY i Y .
= _XY i X + _XY i Y
= _X + Y i X + _X + Y i Y
= XY + XY = X 5 Y
Thus, 4 NAND gates are required
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Sample Chapter of
SOL 2.1.36
SOL 2.1.37
Digital Electronics
Page 129
Chap 2
Boolean Algebra and
Logic Simplification
i. n
.
w
w
o
c
.
a
i
d
o
n
SOL 2.1.38
SOL 2.1.39
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Page 130
Chap 2
SOL 2.1.40
in
.
o
SOL 2.1.41
c
.
ia
X = _A + B i : B = _A + B i + B
= ^A + B h + B = A + B
Output waveform for the given input waveforms is
d
o
n
.
w
w
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Sample Chapter of
SOL 2.1.42
Digital Electronics
Page 131
Chap 2
Boolean Algebra and
Logic Simplification
X = AB + A B = A 9 B
So, we may conclude that
X = A 9 B = 1 for A = B
= 0 for A ! B
Therefore, we obtain the output waveform for the given input waveforms
as
i. n
i
d
o
n
SOL 2.1.43
.
w
w
o
c
.
a
= _A : B i : B
=0
Hence, the output for the circuit will remain zero irrespective of the
input.
SOL 2.1.44
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Page 132
Chap 2
SOL 2.1.45
SOL 2.1.46
in
.
o
c
.
ia
d
o
SOL 2.1.47
n
.
w
w
= _w l + 1i xy l + w _x + yz li
= xy l + wx + wyz l
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Sample Chapter of
Digital Electronics
X2 = SFB
Since, the door will be open is case-1 or case-2. Therefore, we may
express the condition for elevator door to be open as
D = X1 OR X2
D = SFT l + SFB
or
SOL 2.1.48
Page 133
Chap 2
Boolean Algebra and
Logic Simplification
i. n
o
c
.
a
i
d
Z = X + X + Y = X : X + Y = X : _X + Y i
= X + XY = X _1 + Y i = X = X
In option (D), the circuit provides the output X as shown below.
o
n
.
w
w
Hence, the circuit given in option (D) is minimized form of the logic
circuit.
w
SOL 2.1.49
*Maximum Discount*
Page 134
Chap 2
= AD _B 9 C i + A D
= AD _B 5 C i + A D
SOL 2.1.50
= AD + AB + A B
= AD + A _B + B i = AD + A
= _A + A i_D + A i = A + D
in
.
o
NOTE :
Here, it must be noted that, we got first the expression ^AD + A h , and this is also
given in option (B). At first glance it seems to be Answer but it is not. It can be
minimized further into ^A + D h .
SOL 2.1.51
c
.
ia
d
o
n
.
w
w
Output Y is given by
Y = AB + AB = A 5 B = A _XOR i B
SOL 2.1.52
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Sample Chapter of
Digital Electronics
Page 135
Chap 2
Boolean Algebra and
Logic Simplification
i. n
o
c
.
a
i
d
o
n
.
w
w
L = A:B
Hence, the logic expression for given circuit is
SOL 2.1.53
L = _A + B i : _C + D i : E
X + XY = _X + X i_X + Y i = X + Y ! X
X + XY ! X
Option (B)
On minimizing L.H.S. of the equation, we have
X _X + Y i = XX + XY = XY
X _X + Y i = XY
or
Option (C)
On minimizing L.H.S. of the equation, we have
X + XY = X _1 + Y i = X
X + XY = X
or
Option (D)
On minimizing L.H.S. of the equation, we have
or
ZX + ZXY = Z _X + XY i = Z _X + Y i = ZX + ZY
ZX + ZXY = ZX + ZY
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Page 136
Chap 2
SOL 2.1.54
in
.
o
From the circuit diagram, we deduce that LED will glow when
Z = Low _ 0 i , and Z will be low only when X or Y or both will be
High. Now, we consider the different input conditions as
1. For A = B = 1,
c
.
ia
For A = B = 0 ,
3.
d
o
n
.
w
w
4.
SOL 2.1.55
AB + AC = _A + C i_A + B i
Dual form of any identity can be found by replacing all AND function
to OR and vice-versa. Hence, dual form of the expression is given as
_A + B i : _A + C i = _A : C i + _A : B i
SOL 2.1.56
A : 7B : _A + C iA : D
A 7B _A + C iA : D
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Sample Chapter of
SOL 2.1.57
Digital Electronics
Page 137
Chap 2
Boolean Algebra and
Logic Simplification
Z = x 5 y 5 xy
On minimizing the expression, we have
Z = x 5 7y 5 xyA
= x 5 7yxy + yxyA
= x 5 7y _x + y i + 0A
= x 5 7yx + 0A
= x : yx + x : yx
= x _y + x i + xy = x + xy + xy
= x _1 + y i + xy = x + xy
i. n
= x+y
SOL 2.1.58
o
c
.
a
i
d
_X + W i_Y 5 Z i + XW l
On simplification and minimization of the Boolean expression, we get
_X + W i_Y 5 Z i + XW l = _X + W i_YZ l + Y l Z i + XW l
= XYZ l + XY l Z + WYZ l + WY l Z + XW l
From consensus theorem, we have
o
n
.
w
w
AB + AC + BC = AB + AC
So, eliminating the redundant term in the expression, we get
SOL 2.1.59
of
_X + W i_Y 5 Z i + XW l
is
F = _x + y i_x + y li
On simplification, we get the expression
Fsimplified = x + xy l + xy + yy l
...(1)
= x _1 + y l + y i
...(2)
=x
Hence, the logic diagram for the expression (1) and (2) is shown below.
*Maximum Discount*
Page 138
Chap 2
Boolean Algebra and
Logic Simplification
SOL 2.1.60
in
.
o
S = P+Q:R
So, the logic circuit for the given condition is drawn as
c
.
ia
d
o
SOL 2.1.61
n
.
w
w
*Maximum Discount*
Sample Chapter of
Digital Electronics
A0 = A1 = A2 = A3 = A4 = A5 = A6 = 1
A7 = 0
A8 or A9 or both are 1
and either
SOL 2.1.62
Page 139
Chap 2
i. n
o
c
.
a
o
n
i
d
SOL 2.1.63
.
w
w
Y = _A + B i + _C + D i
Now, all the gates are replaced by NOR gate. So, we get the modified
circuit as
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Chap 2
SOL 2.1.64
SOL 2.1.65
in
.
o
c
.
ia
d
o
n
.
w
w
*Maximum Discount*
Sample Chapter of
SOL 2.1.66
Digital Electronics
Page 141
Chap 2
Boolean Algebra and
Logic Simplification
X = AB + CD = (A + B ) (C + D )
= (A + B ) + (C + D )
i. n
SOL 2.1.67
i
d
o
n
.
w
w
o
c
.
a
and
Therefore, by using the above conversion, we get the logic circuit with
NOR gates.
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Page 142
Chap 2
SOL 2.1.68
and
in
.
o
c
.
ia
Therefore, by using the above conversion, we get the logic circuit with
NAND gates as
d
o
n
.
w
w
w
SOL 2.1.69
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Sample Chapter of
Digital Electronics
Page 143
Chap 2
Boolean Algebra and
Logic Simplification
***********
i. n
i
d
o
n
.
w
w
o
c
.
a
*Maximum Discount*
SOLUTIONS 2.2
Page 144
Chap 2
Boolean Algebra and
Logic Simplification
SOL 2.2.1
Correct answer is 0.
Given Boolean function is
F = A + AB + ABC = A _1 + B + BC i = A
Therefore, no gate is required to implement this function.
SOL 2.2.2
Correct answer is 3.
As the given expression is to be realized using one type of 2-input gates.
So, we may use universal gates (NAND, NOR) for realization. Now, we
implement the given function using NAND and NOR gates.
1. NAND Implementation: For NAND implementation, we rewrite the
given expression
in
.
o
c
.
ia
Y = A + BC = A + BC = _A i : _BC i
So, the logic circuit can be implemented as
d
o
n
.
w
w
Y = _A + B i_A + C i
= _A + B i + _A + C i
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SOL 2.2.3
SOL 2.2.4
Digital Electronics
Page 145
Chap 2
Boolean Algebra and
Logic Simplification
i. n
Correct answer is 2.
The Boolean function of two variables x and y are defined as
f _0, 0i = f _0, 1i = f _1, 1i = 1 and f _1, 0i = 0
For the Boolean function, we obtain the truth table as
x
i
d
o
n
.
w
w
o
c
.
a
0
1
Thus, the total cost for the logic circuit will be 2 units.
SOL 2.2.5
Correct answer is 6.
The circuit is as follows
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Chap 2
SOL 2.2.6
SOL 2.2.7
(since A ! B )
Correct answer is 0.
Given the logic equation,
in
.
o
7X + Z #Y + _Z + XY i-A#X + Z _X + Y i- = 1
and
X =1
So, by substituting X = 1 and X = 0 in the logic equation, we get
c
.
ia
71 + Z #Y + _Z + 1Y i-A : 80 + Z _1 + Y iB = 1
71A8Z _ 1 iB = 1
or
Hence, we have
SOL 2.2.8
Z = 1 or Z = 0
d
o
n
.
w
w
Correct answer is 0.
Given logic expression is
A _A + B i_A + B + C i
On solving the expression, we have
SOL 2.2.9
Correct answer is 1.
From the given circuit, we can observe that input to last XNOR gate is
same. So, the XNOR output is given by (Let input is X )
Z = X:X+X:X = X+X = 1
i.e. the output will be High (logic 1), irrespective of the inputs A and
B.
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SOL 2.2.10
Digital Electronics
Page 147
Chap 2
Boolean Algebra and
Logic Simplification
2 2 = 2 2 = 2 16 = 65536
n
SOL 2.2.11
22
SOL 2.2.12
n-1
= 2 2 = 2 2 = 2 8 = 256
4-1
i. n
o
c
.
a
Correct answer is 3.
To implement the given function using NAND and NOR gates, we
rewrite the given function as
i
d
o
n
Y = ABCD = ABCD = AB + CD
So, the equivalent circuit for the Boolean function is
.
w
w
Therefore, two NAND gates and one NOR gate is required to implement
the function Y = ABCD .
***********
*Maximum Discount*
SOLUTIONS 2.3
Page 148
Chap 2
Boolean Algebra and
Logic Simplification
SOL 2.3.1
SOL 2.3.2
SOL 2.3.3
SOL 2.3.4
SOL 2.3.5
SOL 2.3.6
in
.
o
c
.
ia
d
o
n
.
w
w
SOL 2.3.7
SOL 2.3.8
SOL 2.3.9
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SOL 2.3.10
SOL 2.3.11
SOL 2.3.12
SOL 2.3.13
SOL 2.3.14
SOL 2.3.15
o
c
.
a
i
d
i. n
o
n
.
w
w
Page 149
Chap 2
Y = A+B
Y = A:B =
negative-
SOL 2.3.16
SOL 2.3.17
SOL 2.3.18
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Page 150
Chap 2
SOL 2.3.19
SOL 2.3.20
SOL 2.3.21
SOL 2.3.22
SOL 2.3.23
SOL 2.3.24
in
.
o
c
.
ia
d
o
SOL 2.3.25
SOL 2.3.26
n
.
w
w
Output
Y = A9B
SOL 2.3.27
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Sample Chapter of
Digital Electronics
Inputs
Page 151
Chap 2
Outputs
X = A:B
Y = A+B
For both NAND and OR gates, all output entries are logic 1 except
for one entry.
i. n
SOL 2.3.28
SOL 2.3.29
SOL 2.3.30
i
d
o
n
.
w
w
o
c
.
a
Y = AB + AB
Complement of Y = Y = AB + AB
SOL 2.3.31
Complement of Y = Y = Y = AB + AB = AB + AB
SOL 2.3.32
SOL 2.3.33
SOL 2.3.34
SOL 2.3.35
SOL 2.3.36
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Chap 2
SOL 2.3.37
SOL 2.3.39
SOL 2.3.40
SOL 2.3.41
SOL 2.3.42
SOL 2.3.43
SOL 2.3.44
in
.
o
c
.
ia
d
o
n
.
w
w
SOL 2.3.45
SOL 2.3.46
SOL 2.3.47
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Sample Chapter of
SOL 2.3.48
Digital Electronics
Page 153
Chap 2
Boolean Algebra and
Logic Simplification
SOL 2.3.49
SOL 2.3.50
SOL 2.3.51
i. n
o
c
.
a
(A + B ) + C ! A + (B + C )
(A + B ) + C ! A + (B + C )
or
or
o
n
i
d
SOL 2.3.52
.
w
w
= A (1 + X) = A
SOL 2.3.53
SOL 2.3.54
SOL 2.3.55
SOL 2.3.56
*Maximum Discount*
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Chap 2
SOL 2.3.57
(B) Y = 0 + 1 = 1 = 0
(C) Y = 0 $ 1 = 0 = 1
(D) Y = 0 9 1 = 0
SOL 2.3.58
SOL 2.3.59
SOL 2.3.60
in
.
o
***********
c
.
ia
d
o
n
.
w
w
*Maximum Discount*