GME TX6200 and TX7200 CIRCUIT DESCRIPTION

Drawing No :- 42996-1
Date :- 31/01/2006
Written By :- JMT
POWER SUPPLY
Battery voltage via the power on/off switch is applied to voltage regulators U501 (RX/TX power supply)
and U806 (CPU power supply). U501 and U806 feature an inhibit control function (pin3). U806 inhibit
control is held high to enable a constant 5 volts to be applied to the CPU. The transceiver is in the off
condition until U501 receives an enable signal from the CPU. U501 is then switched to the on condition
applying voltage to RX switch Q503 (normally on) and TX switch Q501 (normally off).
RX/TX SWITCHING
The RX and TX switched voltages are controlled by the CPU. In RX mode Q503 is forward biased
resulting in 5V supply to the receiver circuits. Q501 is reversed biased whilst Q502 is forward biased to
short any residual TX supply voltage to ground.
In TX mode a press of the PTT toggles the CPU from RX mode to TX mode. Q501 is forward biased
resulting with 5V supply to the transmitter circuits. During transmit Q503 is reversed biased whilst Q504
is forward biased to short any residual RX supply voltage to ground.
CPU RESET CIRCUIT
U802 executes the CPU reset function. Reset occurs when the CPU pin 25 is pulled low. U802 monitors
the 5 volts input to the CPU, U806. If the input of U802 falls below 4.2 volts, the output of U802 is
forced low resulting with the CPU being placed into reset.
POWER DOWN DETECTION
A power down signal to the CPU pin 22 is generated by a Schmitt trigger circuit DQ801. The circuit
monitors the difference between the input and output of voltage regulator U806. As the battery voltage
falls and before reset occurs the CPU enters a power down mode triggered by the DQ801. Energy stored
in C803 is sufficient to complete a full power down write cycle to the EEROM and save all user settings.
RX/TX INDICATORS
The Green and Red bi-colour LED diode LD901 indicates RX or TX mode. In RX mode the Green LED
is illuminated by driver Q901A via CPU control pin 21. During TX mode, the Red LED is illuminated by
driver Q901B via CPU control 25.
VOLTAGE CONTROLLED OSCILLATOR
Q103 and C115 form a dynamic filter providing a well filtered supply voltage to the VCO circuit. The
VCO oscillator transistor Q101 is configured as a conventional common collector stage. The main tuning
element of the VCO is a capacitive loaded micro-strip resonator, the frequency tuning range is achieved
by varactor diodes D102, D103, D104 and D105. The output buffer stage Q102 is configured as a
conventional common emitter for AC and cascode configuration for DC conditions. Q102 buffer
amplifier provides TX drive over the frequency range of 476.425 to 477.400MHz and RX local oscillator
injection over the frequency range of 455.025 to 476.000MHz.

PHASE LOCKED LOOP AND VCO

A PLL reference frequency of 20.950 MHz is generated by crystal XT301/U303. Frequency adjustment
is achieved by varactor diode D301 in series with the crystal. The exact frequency of the reference
oscillator is controlled by CPU software via DAC, U103.
The reference frequency is applied to the PLL IC U101 pin 8, where it is divided by a programmable
divider to obtain a PLL channel step increment of 12.5 kHz. The 12.5 kHz reference frequency is applied
to a port of the PLLs internal phase comparator. A sample of the VCO frequency is applied to U101 pin
6, where it passes via a pre-scaler and a programmable 18 bit divider. The output of the 18 bit divider is
applied to a second port of the internal phase comparator. The phase comparator compares the 12.5 kHz
reference frequency and the scaled VCO frequency. The comparator output of U101, pin2 applies a
control voltage via the passive PLL loop filter to the VCO varactor diodes. If the phase of the channel
step reference signal and the output of the programmable scaled VCO frequency match then the VCO is
locked onto the nominal channel frequency. Channel separation is 25 kHz which comprises 2 x12.5 kHz
steps.
The divide ratio of the 18 bit counter is determined by the CPU. CPU Data is applied via a 3 line serial
interface consisting of serial data, clock and ground. The PLL data is protected from corruption by a write
enable signal from the CPU. New data will only be written to the PLL if the serial data, clock and write
enable signals are synchronised.
MICROPHONE AMPLIFIER, CTCSS and SELCALL
The microphone amplifier U701 is a dual op-amp.
U701A input circuit incorporates a high pass filter to suppress low frequency voice components from
distorting CTCSS tones and also provides 6dB per octave pre-emphasis over the audio frequency range of
300Hz to 3KHz. Audio from U701A passes via a low pass filter with a corner frequency of approximately
2.7kHz to the input of U701B. Above 3 kHz, attenuation in the order of 12dB per octave prevent out of
band audio signals from interfering with adjacent channels.
CTCSS and SELCALL
CTCSS and SELCALL tones are generated by the CPU. CTCSS tones are injected and the modulation
level set at the input of U701B via R717. No adjustment is required. SELCALL tones are coupled to pin 1
of U701A via R708 and C705. During SELCALL operation, transistor Q702 is turned on and shunts
the microphone audio to ground muting the mic audio input. This is achieved by a mic mute signal
from the CPU, U801 pin 45. During voice transmissions, Q702 is turned off allowing the audio to pass
through to U701.
FM Modulation
Audio frequency components are applied to the VCO PLL loop filter at the junction of R124 and R125
producing FM modulation. Modulation limiting level is set by DAC U103 under control of the CPU setup
software and DAC cntrol lines DI, CLK and LE. When the normal voice modulation limiting level of 5
kHz is set, the CTCSS deviation will be approx. 300Hz .

TX DRIVER & OUTPUT STAGE

Vcc for the transmitter driver stage U601 is supplied from the transistor switch Q501. DC power for the
RF output module is supplied directly from the battery via the power On/Off switch.
RF signal from the VCO buffer Q102 is AC coupled to the driver input U601, pin1.
The amplified RF output from U601, pin 4 is AC coupled to the RF power module U602, pin 1. The level
of RF output power is set by the voltage applied to U602, pin 2. The control voltage is derived from the
CPU, U801 and the DAC, U103.
ANTENNA MATCHING/SWITCHING
The antenna RX/TX switching is achieved with PIN diodes D601 and D602. A low pass filter provides
impedance matching between the RF power output module and the antenna. The low pass filter also
attenuates out of band harmonic signals to the required level.
In receive mode signals from the antenna are passed to the receiver front end amplifier Q201 via the low
pass filter and L605. Diode D601 is reversed biased isolating the output circuit of the RF output module
from the incoming signal path to prevent degradation to the input signal.
During transmit PIN diode D601 is forward biased via L603, L604, L605, D602 and Q601, allowing the
RF to pass to the antenna via the LPF circuit. In receive mode L605 presents a high impedance to the RF
output path. Transistor Q601 is forward biased allowing conduction of diode D602 therefore shunting
residual output signals to ground avoiding damage to the RX input circuit.
RECEIVER RF AMPLIFIER
RF signal passes through a high pass filter consisting of C201, C202 and L201 to the RF amplifier Q201.
Resistive damping, R203 is added across L210 to improve RF stability. The RF signal is coupled to the
2nd RF amplifier via a tuned band-pass circuit L202, L203, C206, C205, C206 and varactor diodes D202
and D203 under control of the CPU via the DAC U103.
The 2nd RF amplifier Q202 is a common emitter stage for AC and connected in series for DC with Q201
to reduce battery current. A tuned band-pass circuit couples signals from Q202 and the mixer stage Q203.
Band-pass tuning is achieved by varactor diodes D204, D204, C213 and D205, L205, C224 under control
of the CPU via the DAC U103.
1ST MIXER and IF AMPLIFIER
Excellent IM performance is provided by a dual gate GASFET first mixer Q203. RF signal coupled from
the 2nd RF amp Q202 is applied to Gate 2, while the local oscillator signal from the VCO is applied to
Gate 1. The resultant 21.4MHz 1st IF signal is coupled to a four pole 1st IF filter XF201. The output of
the XF201 is applied to pin 16 of U303 2nd IF amplifier/demodulator circuit.
2nd MIXER IF AMPLIFIER and DEMODULATOR
U303 performs the following functions: 2nd mixer, 2nd IF limiting amplifier, FM demodulator, noise
amplifier and RSSI. The PLL reference oscillator using XT301 circuit also serves as the local oscillator
for the 2nd mixer. The 1st IF signal of 21.4MHz is applied to pin 16. After mixing, the 2nd IF of 450 kHz
is present at pin 3. The 2nd IF signal passes through narrow band ceramic band-pass filter XF301 before
re-entering U303, pin 5. Further amplification takes place within the limiter amplifier before
demodulation. A quadrature detector demodulator is constructed around C309, R303 and ceramic
discriminator CF302, no adjustment is required for the detector circuit. Demodulated audio is taken
from pin 9.

RECEIVER AUDIO PRE-AMPLIFIER AND AUDIO MUTE

Audio from pin 9 of U303 is coupled via C351 to pin 2 of the dual op amp U301A providing gain and a
low pass filter with a corner frequency of 3.5kHz. The output of U301A is applied to a two channel
multiplexer IC U302. U302 operates as an audio mute switch controlled by the CPU.
The audio mute control signal is applied to U302, pin 5. If pin 5 is at logic 1 audio is passed from the
output of U301A, pin 1 and U302, pins 1 and 7 then to the volume control circuit. If U302 pin5 is logic
0 the audio path from the volume control isolated. R355 and R354 serves as DC input to U302, pin 6 to
maintain a voltage potential across C407 to prevent a thumping sound during audio mute switching.
CTCSS sub audible tones pass via the low pass filter associated with U301B and applied to pin 7 of the
CPU for A-D conversion. Selcall tones are applied to pin 4 of the CPU for processing.
AUDIO POWER AMPLIFIER
The dual audio power amplifier U401 is configured as a single ended class B amplifier with the speaker
circuitry capacitor coupled to output pin 5. DC power for the audio power amp is supplied directly from
the battery via the power On/Off switch.
Pin 1 is a standby function to limit the current drain from the battery when no audio is present. If Pin 1 is
at logic 0 the audio power amp is active. When Pin 1 is at logic 1 the power amp is in standby mode.
The audio is coupled into pin 4 via a high pass filter. The filter suppresses the low frequency CTCSS
tones as a result they can not be heard from the speaker.
MICROPROCESSOR
The M3822, 8 bit microprocessor controls all the functions of the radio. An 8MHz crystal XT802 sets the
timing. The LCD drive consists of four back planes and 25 segment and icon drivers. Back lighting for
the LCD display is via 4 x green LEDs under control of the CPU to switch off the LEDs after a
predetermined time to conserve battery power.
E2PROM
An E2PROM, U803 stores user settings when the radio is powered down. The CPU stores and retrieves
data from the E2PROM in serial format via pin 35 of the CPU. The serial data is synchronised with the
clock, data from pin 26. Pin 27 enables the E2PROM during the read/write sequence.
CTCSS
When transmitting CTCSS, tones are generated using a simple 4 bit 4-2R resistive network RA806 and
RA807, directly under the control of the CPU. When receiving the CTCSS tones are fed to pin 7 of the
CPU. The CPU performs the required decoding algorithms.
LCD
The microprocessor has an inbuilt liquid crystal display driver common drive; segment drive and bias
control circuit.
LCD BIAS CONTROL
The LCD bias pins on the CPU, VL1 VL3 are controlled by the voltage divider network R817, R898
and R819.
The duty ratio controls the layer selection, software sets the duty ratio to four and configures the LCD as
a four layer display by using all common pins Com0 Com3 data.
4

SERVICE NOTES:-