Cmos Funda Full Course

SESSION 1: MOS THEORY
Review of PN Junction
MOS Structure
Accumulation, cutoff, Inversion
MOS transistor
Threshold Voltage
CADENCE DESIGN SYSTEMS, INC.
CADENCE CONFIDENTIAL
Review of PN Junction
Drift current: electrons and holes move in an electric field
E field
(+)
(-)
holes
electrons
Diffusion current: electrons and holes move from high

concentration to low concentration
econc.
Si
2
Si
Si
Si
Review (cont)
PN junction built-in potential
E field
N
- V0
EC
EFp
EV
V0
Eip Ein
q
kT N A N D
ln
2
q ni
qV0
EFn
Fermi levels line up

Electrons traveling from
right to left have to cross
potential barrier of qV0
Bias Effect on Depletion Width
When biased, electric field in depletion region changes

Forward bias: reduces electric field
Reverse bias: increases electric field
Electric field is a result of uncovered charges. Therefore

depletion width must change
Forward bias: less charges needed. Depletion width reduces
Reverse bias: more charges needed. Depletion region increases.
Bias Effect on Depletion Width

Width of depletion region:
2 ( N a N d )
Wd
V0
q Na Nd
Width of depletion region with bias V:
2 ( N a N d )
V0 V
Wd
q Na Nd
5
Diode Equation
Forward bias: barrier lowered, diffusion current dominates
Reverse bias: barrier raised, only current is small drift
current of minority carriers
Diode only lets current flow in one direction
Diode equation:
I I 0 (e
qV / kT
1)
I0 = generation current
6
Capacitance of P/N Junction

E field
Separated charges result in depletion region capacitance

Similar to parallel-plate capacitor
Charge in depletion region:
Nd Na
Q j A 2q
(V0 V )
Nd Na
Capacitance:
A 2 q N d N a
Cj
2 V0 V N d N a
MOS structure
MOS: Metal-oxide-semiconductor
Gate: metal (or polysilicon)
Oxide: silicon dioxide, grown on substrate
MOS capacitor: two-terminal MOS structure

Gate terminal
Metal gate (Al)
Oxide (SiO2)
Si substrate
Body or substrate terminal

8
MOS Energy Band Diagram

qM
qoxid
e
E0
qS
qS
EFm
EC
oxide
bandgap
8ev
Metal
Oxide
Ei
EFp
EV
p-type Si
Work function (qM, qS): energy required to take

electron from Fermi level to free space
Work function difference between Al and Si
At equilibrium, Fermi levels must line up
9
MOS Energy Band Diagram

Bands must bend for Fermi levels to line up
Part of voltage drop occurs across oxide, rest occurs

next to O-S interface
Amount of bending is equal to work function
difference: qM - qS
EC
qS
EFm
M
10
qF
Ei
EFp
EV
F = Fermi potential
(difference between EF
and Ei in bulk)
S = surface potential
S (p-type)
Flat-Band Voltage
Flat-band voltage
Built-in potential of MOS system

Work function difference: VFB = m - S
Apply this voltage to flatten energy bands
11
MOS capacitor operation

Assume p-type substrate
Three regions of operation

Accumulation (VG < 0)
Depletion (VG > 0 but small)
Inversion (VG >> 0)

VG
P-type Si substrate
VB = 0
12
Accumulation
Negative voltage on gate: attracts holes in substrate
towards oxide
Holes accumulate on Si surface (surface is more

strongly p-type)
Electrons pushed deeper into substrate
VG < 0
EFm
qVG
P-type Si substrate
EC
Ei
EFp
EV
VB = 0
13
Depletion
Positive voltage on gate: repels holes in substrate
Holes leave negatively charged acceptor ions
Depletion region forms: devoid of carriers

Electric field directed from gate to substrate
Bands bend downwards near surface

Surface becomes less strongly p-type (EF close to Ei)
VG > 0
Depletion region
P-type Si substrate
Eox
EFm
qVG
EC
Ei
EFp
EV
VB = 0
14
Depletion region depth

Calculate thickness xd of depletion region
Find charge dQ in small slice of depletion area
xd
dQ qN A dx
dQ
dx
Find change in surface potential to displace dQ by distance xd
(Poisson equation):
d x
15
dQ
Si
d xqN A
dx
Si
Depletion region depth (cont.)

Integrate perpendicular to surface
S
xd
qN A x
dS 0 2 Si dx
F
qN A xd2
S F
2 Si
Result:
xd
16
2 Si S F
qN A
Depletion region charge

Depletion region charge density
Due only to fixed acceptor ions
Charge per unit area
Q qN A xd
Q 2qN A Si S F
17
Inversion
Increase voltage on gate, bands bend more
Additional minority carriers (electrons) attracted from
substrate to surface
Forms inversion layer of electrons
Surface becomes n-type
VG >> 0
EC
Eox
P-type Si substrate
VB = 0
18
electrons
qVG
EFm
Ei
EFp
EV
Inversion
Definition of inversion
Point at which density of electrons on surface equals
density of holes in bulk
Surface potential is same as F, but different sign
EC
Remember:
qF
qF = EF - Ei
19
qS = -qF
Ei
EFp
EV
MOS transistor
Add source and drain terminals to MOS capacitor
Transistor types
NMOS: p-type substrate, n+ source/drain
PMOS: n-type substrate, p+ source/drain
N+
source
20
N+
drain
P+
source
P+
drain
P-substrate
N-substrate
NMOS
PMOS
MOS Transistor
Important transistor physical characteristics
Channel length L
Channel width W
Thickness of oxide tox
tox
L
21
MOS transistor operation

Simple case: VD = VS = VB = 0
Operates as MOS capacitor
When VGS<VT0, depletion region forms
No carriers in channel to connect S and D
Vg < VT0
Vs=0
Vd=0
source
drain
depletion
region
P-substrate
VB = 0
22
MOS transistor operation

When VGS > VT0, inversion layer forms
Source and drain connected by conducting n-type layer
(for NMOS)
Vg > VT0
Vs=0
Vd=0
source
drain
depletion
region
P-substrate
inversion
layer
23
VB = 0
MOS transistors Types and Symbols

D
NMOS Enhancement NMOS Depletion

D
PMOS Enhancement
24
NMOS with
Bulk Contact
Threshold voltage
Threshold voltage (VT0): voltage between gate and source
required for inversion
Transistor is off when VGS < VT0
Components:
Work function difference between gate and channel
(Flat-band voltage)
Gate voltage to change surface potential
Gate voltage to offset depletion charge
Gate voltage to offset fixed charges in gate oxide and

silicon-dioxide interface
25
Threshold voltage (1)

Work function difference GC between gate and channel
Represents built-in potential of MOS system
For metal gate: GC = F(substrate) - M(gate)
For poly gate: GC = F(substrate) - F(gate)
VT 0 GC
26

First component accounts for built-in voltage drop
Now apply additional gate voltage to achieve inversion:
change surface potential by -2F
VT 0 GC 2 F
27

Offset depletion region charge, due to fixed acceptor ions
Calculate charge at inversion (S =-F)

From before:
So:
Q 2qN A Si S F
QB 0 2qN A Si 2 F
For non-zero substrate bias (VSB 0):
QB 2qN A Si 2 F VSB
Due to larger depletion region
28
Threshold voltage (3, cont.)

To offset this charge, need voltage -QB/Cox
Cox = gate capacitance per unit area
Cox=ox/tox
tox = thickness of gate oxide
VT 0
29
QB
GC 2 F
Cox
Correct for non-ideal fixed charges

Fixed positive charge density Qox at boundary
between gate oxide and substrate
Due to impurities, lattice imperfections at interface
Correct with gate voltage = -Qox/Cox
Final threshold voltage formula (for NMOS):
VT 0
30
QB 0 Qox
GC 2 F
Cox Cox
Threshold voltage
General form (non-zero substrate bias):
QB Qox
VT GC 2 F
Cox Cox
Can also write as:
QB QB 0
VT VT 0
Cox
Replacing second term:
VT VT 0
Substrate-bias
coefficient
31
2 F VSB 2 F
2qN A Si
Cox
Threshold voltage, summary

If VSB = 0 (no substrate bias):
QB 0 Qox
VT 0 GC 2 F
Cox Cox
If VSB 0 (non-zero substrate bias)
VT VT 0
2 F VSB 2 F
Body effect (substrate-bias) coefficient:
2qN A Si
Cox
Threshold voltage increases as VSB increases!
32
Threshold Voltage (NMOS vs. PMOS)
33
NMOS
PMOS
Substrate Fermi potential
F < 0
F > 0
Depletion charge density
QB < 0
QB > 0
Substrate bias coefficient
>0
<0
Substrate bias voltage
VSB > 0
VSB < 0
Body effect
Body effect: Voltage VSB affects threshold voltage of
transistor
Body normally connected to ground for NMOS, VDD for PMOS
Raising source voltage increases VT of transistor
Implications on circuit design
A
Vx
If Vx > 0,
VSB (A) > 0,
VT(A) > VTO
B
VT0
34
Threshold voltage adjustment

Threshold voltage can be changed by doping the channel
region with donor or acceptor ions
For NMOS:
VT increased by adding acceptor ions (p-type)
VT decreased by adding donor ions (n-type)
Opposite for PMOS
Approximate change in VT0:

Density of implanted ions = NI [cm-2]
Assume all implanted impurities are ionized
VT 0
35
qN I
Cox
5 Minutes Break
36
MOS EQUATIONS Lecture 1
Cut-off, Linear, Saturation

Drain Current equations
MOS Characteristics
Oxide capacitance
Junction Capacitance
37 CADENCE DESIGN SYSTEMS, INC.
MOS transistor characteristics

Three regions of operation: overview
Cutoff: VGS < VT

No inversion layer formed, drain and source are
isolated by depleted channel. IDS 0
Linear: VGS > VT, VDS < VGS-VT
Inversion layer connects drain and source.
Current is almost linear with VDS (like a resistor)
Saturation: VGS>VT, VDSVGS-VT
Channel is pinched-off. Current saturates.
38
Cutoff Region
VS
VG
source
VD
drain
depletion
region
substrate
VGS < VTN
VB
VGS > VTP
Depletion region no inversion

Current between drain and source is 0
Actually there is leakage current
39
Linear mode
When VGS>VT, an inversion layer forms between drain
and source
Current IDS flows from drain to source (electrons travel
from source to drain)
Depth of channel depends on V between gate and
channel
Drain end narrower due to larger drain voltage
Drain end depth reduces as VDS is increased

Vs=0
Channel
(inversion layer)
source
Vg > VT0
Vd < VGS-VT0
drain
depletion
region (larger at
drain end)
P-substrate
VB = 0
40
Linear I/V Equation
Gradual Channel Approximation:

Assume dominant electric field in y-direction
Current is constant along channel
41
Linear I/V Equation

Assume that VGS > VT, then the charge induced per unit
area in channel
QI ( y ) Cox VGS VT V ( y )
The resistance dR of length dy of channel
dy
dR
W nQI ( y )
Where W is width of channel and n mobility of
electron.
42
Linear I/V Equation

For current ID, drop across this resistance will be
ID
dV I D dR
dy
W n QI ( y )
For total length L on integration we have

VDS
I
0
43
dy W nCox (VGS V VT )dV

0
Linear I/V Equation
Final equation for ID
W
2
1
VGS VT VDS 2 VDS
I D nCox
L
Device transconductance:
Process transconductance:
W
kn n nCox
L
k n' n Cox
W
2
1
VGS VT VDS 2 VDS
ID k
L
'
n
44
Saturation mode
When VDS = VGS - VT:
No longer voltage drop of VT from gate to substrate at drain
Channel is pinched off
If VDS is further increased, no increase in current IDS

As VDS increased, pinch-off point moves closer to source
High electric field in depleted region accelerates electrons towards
drain
Vs=0
source
pinch-off point
45
Vg > VT0
Vd > VGS-VT0
drain
depletion
region
VB = 0
Saturation I/V Equation

As drain voltage increases, channel remains pinched off
Channel voltage remains constant
Current saturates
To get saturation current, use linear equation with VDS =
VGS - VT
W
2
I D nCox VGS VTN
L
1
2
46
MOS I/V Characteristics

I/V curve for ideal MOS device
VGS3> VGS2 >VGS1
Drain current IDS
VGS3
Linear
VGS2
VGS1
Saturation
Drain voltage VDS
47
MOS I/V Characteristics

VDS = VGS-VT
Saturation
ID (mA)
VGS = 4V
0.0
VGS = 3V
1.0
2.0
3.0
VDS (V)
VGS = 2V
VGS = 1V
4.0
5.0
(a) ID as a function of VD S
0.020
ID
Triode
Square Dependence
VGS = 5V
0.010
Subthreshold
Current
0.0
2.0
VT1.0
VGS (V)
3.0
(b) ID as a function of VGS

(for VDS = 5V).
NMOS Enhancement Transistor: W = 100 m, L = 20 m
48
MOSFET Capacitances
Oxide Capacitance
Gate to Source overlap
Gate to Drain overlap
Gate to Channel
Source to Bulk junction
Drain to Bulk junction
49
Oxide capacitances
source
Ldrawn
drain
LD
Overlap capacitances
gate electrode overlaps source and drain regions
LD is overlap length on each side of channel
Leff = Ldrawn 2LD

Total overlap capacitance:
C O CGSO CGDO 2C oxWLD
50
Oxide capacitances
Channel capacitances
Gate-to-source: Cgs
Gate-to-drain: Cgd
Cgs
source
Cgd
Cgb
drain
Gate-to-bulk: Cgb
Cutoff:
No channel connecting source and drain
Cgs = Cgd = 0
Cgb = CoxWLeff
Total channel capacitance CC = CoxWLeff
51
Oxide capacitances
Linear mode
Channel spans from source to drain
Capacitance split equally between S and D
1
CGS C oxWLeff
2
1
CGD C oxWLeff
2
CGB 0
Total channel capacitance CC = CoxWLeff

Saturation mode
Channel is pinched off:
CGD 0
2
CGS C oxWLeff
3
CGB 0
Total channel capacitance CC = 2/3 CoxWLeff
52
Oxide capacitances
Cg,total
(no overlap)
53
Reverse-biased P-N junctions!

Capacitance depends on reverse-bias voltage.
54
For a P-N junction:
If V=0, Cap/area =
General form:
A 2 q N d N a
Cj
2 V0 V N d N a
q Si N d N a
C j0
2V0 N d N a
Cj
AC j 0
V
1
V0
m = grading coefficient (0.5 for abrupt junctions)

(0.3 for graded junctions)
55
Junction with substrate
Bottom area = W * LS (length of drain/source)
Sidewall facing channel: area = W * Xj
Total cap = Cj
Junction with sidewalls

Channel-stop implant
Perimeter = 2LS + W
Area = P * Xj
Total cap = Cjsw
Total junction cap C = Cj + Cjsw

56
SESSION 2: STATIC INVERTERS

Lecture 1
Characteristics of Inverters
Resistive Load Inverters
VTC, Delay, Power Dissipation
Pseudo-NMOS Inverters
Depletion Load Inverters
MOS voltage levels

Case 1: NMOS discharges capacitor
Initially: Vout = VDD (capacitor fully charged)
VGS of NMOS = VDD
What is final Vout?
VDD
Vout
VDD
Cload
Vout
time
NMOS remains on since VGS > VT

Final output voltage Vout = 0V
58
MOS voltage levels

Case 2: NMOS charges capacitor
Initially: Vout = 0
Initial VGS of NMOS = VDD
What is final Vout?
VDD
VDD
Vout
VDD
Vout
VDD-VT
Cload
time
NMOS remains on until VGS = VT
Final output voltage Vout = VDD - VT

59
MOS voltage levels

Repeat for PMOS:
Case 1: PMOS discharging capacitor
Gnd
S
D
Vout
Cload
PMOS on until VGS = VT

Vout = |VT|
Case 2: PMOS charging capacitor

VDD
Gnd
PMOS always on (VGS = -VDD)
Vout = VDD
Vout
Cload
60
MOS voltage levels

NMOS summary
Transfers logic 0 completely (good for discharging a node)
Does not transfer logic 1 completely (bad for charging a node)
PMOS summary
Transfers logic 1 completely
Does not transfer logic 0 completely
Result:
NMOS used for pulldown, PMOS for pullup
61
Inverter Operation
Inverter is simplest digital logic gate
0
1
1
0
Many different circuit styles possible
In Out
0 1
1 0
Resistive-load
Pseudo-NMOS
CMOS
Important characteristics
Speed (delay through the gate)
Power consumption
Robustness (tolerance to noise)
Area and process cost
62
Inverter model: VTC

Voltage transfer curve (VTC):
plot of output voltage Vout vs. input voltage Vin
Vin
Inverter
Vout
Ideal digital inverter:
ideal
VDD
When Vin=VDD, Vout=0

Sharp transition region
Vout
actual
Vin
63
When Vin=0, Vout=VDD
VDD
Actual inverter: VOH and VOL

VOH and VOL represent the high and
low output voltages of the inverter
VOH = output voltage when Vin = 0
VOL = output voltage when Vin = 1
VDD
VOH
Ideally,VOH = VDD,VOL = 0
Difference (VOH-VOL) is the voltage
swing of the gate
Vout
Full-swing logic swings from ground

to VDD
VOL
Vin
64
VDD
Inverter threshold
Inverter switching threshold:
VOH
Vout
Point where voltage transfer

curve intersects line Vout=Vin
Vout=Vin
Represents the point at which

the inverter switches state
VTH
Normally, VTH VDD/2
VOL
Vin
65
VDD
Noise Margins
VIL and VIH measure effect of
input voltage on inverter
output
VOH
Slope = -1
Vout
VIL = largest input voltage

recognized as logic 0
VIH = smallest input voltage

recognized as logic 1
VOL
VIL VIH
VDD
Defined as point on VTC where

slope = -1
Vin
66
Noise margin (cont)

Noise margin is a measure of the
robustness of an inverter
interconnect
NML = VIL - VOL

NMH = VOH - VIH
1
VOH
VOL
0
Models a chain of inverters. Example:

NMH
NML
VIH
First inverter output is VOH
VIL
Second inverter recognizes input > VIH

as logic 1
Difference VOH-VIH is safety zone for
noise
Ideally, noise margin should be

as large as possible
67
Noise margin (cont)

Why are VIL, VIH defined as unity-gain point on VTC?
Assume there is noise on input voltage Vin
Vout f Vin Vnoise

First-order approximation:
Vout
dVout
f Vin
Vnoise
dVin
If gain (dVout/dVin) > 1, noise will be amplified.

If gain < 1, noise is filtered. Therefore VIL, VIH
ensure that gain < 1
68
Inverter time response

VDD
Vin
VDD/2
Vss
VDD
Vout
VDD/2
Vss
t0 t1
t2 t3
Propagation delay measured from 50% point of Vin to 50% point

of Vout
tphl = t1 - t0,
69
tplh = t3 - t2,
tp = (tphl+tplh)
Rise and fall time

tF
tR
t0 t1
t2 t3
V90%
V10%
Fall time: measured from 90% point to 10% point
t F = t1 - t 0
Rise time: measured from 10% point to 90% point
tR = t3 - t2
Alternately, can define 20%-80% rise/fall time
70
Ring oscillator
Ring oscillator circuit: standard method of comparing delay from
one process to another
Odd-number n of inverters connected in chain: oscillates with
period T (usually n >> 5)
VOH
V1
V3
V2
V1
V3
V2
V50%
Cload
tPHL2 tPLH3 tPHL1 tPLH2 tPHL3 tPLH1
71
Cload
T t plh1 t phl1 t plh 2 t phl 2 t plh 3 t phl 3

T 2nt p ,
1
1
f
,
T 2nt p
1
tp
2nf
Resistive-load inverter
Requires only NMOS transistor and
resistor
VDD
When Vin = 0:
NMOS is OFF (VGS = 0)

No current through NMOS or resistor
Vout VDD
Vin
Vout
When Vin = VDD:

NMOS is ON (VGS = VDD)
NMOS on resistance << R
Vout 0
72
Gnd
Remember: if body terminal
not shown, it is connected to
gnd for NMOS, VDD for
PMOS
Resistive-load inverter: VOH

VDD
Vin = 0: NMOS transistor off, no current

flows in circuit
No voltage drop across R
Vout
Vin=0
VOH = VDD
Gnd
73
Resistive-load inverter: VOL

Vin = VDD: NMOS transistor on (linear
mode)
I D k ' WL (VGS VT )VDS 12 VDS
VDD
VGS VIN VDD

VDS VOL
(because ID = Iload)
(VDD VOL )
ID
R
(VDD VOL )
2
k ' WL [(VDD VT )VOL 12 VOL ]
R
Iload
Vout
Vin=VDD
ID
Gnd
Solve quadratic equation for VOL, Approx value is
1
VOL
' W
Rk L
74
Resistive-load inverter: VOL cont

Note that the value of VOL depends on the size of the
NMOS device and on R
Increase W to reduce VOL
Increase R to reduce VOL
Logic with this property is called ratioed logic

Requires careful sizing for correct logic levels
Ratioless logic: output levels do not depend on

transistor sizes
75
Resistive-load inverter: VIL

VIL = low unity gain point of VTC
When Vin = VIL, NMOS in saturation:
VDD Vout 1
2
2 kn Vin VT
R
2
Vout VDD 12 Rkn Vin VT
Take derivative of Vout with respect to Vin, set to -1
dVout
Rkn Vin VT 1
dVin
1
Vin VIL
VT
Rkn
76
increase VIL (and

NML) by reducing kn
Resistive-load inverter: VIH

VIH = high unity gain point of VTC
When Vin = VIH, NMOS in linear region:
VDD Vout
2
kn Vin VT Vout 12 Vout
R
2
VDD Vout kn RVin VT Vout 12 kn RVout
(1)
Take derivative of Vout with respect to Vin, set to -1
dVout
dVout
dVout
kn RVin VT
kn RVout kn RVout
dVin
dVin
dVin
1 kn RVin VT kn RVout kn RVout
Solve this equation simultaneously with (1) to get:
8VDD
1
VIH VT
3kn R kn R
77
Resistive-load inverter: VTH

Threshold of resistive-load inverter: VTH:
Point on VTC where Vin = Vout:
NMOS in saturation (ignoring l):
I D 12 k ' WL Vin VT
Vin Vout VTH

(VDD VTH ) 1 ' W
2
2 k L VTH VT
R
Solve this quadratic for VTH
78
Resistive-load inverter: VTC

Drain current IDS
Resistor load line

(slope = 1/R)
Vin=4V
Vin=3V
Vin=2V
VDD
Vout
VDD
R
Vin=1V
VOL
Vout = VDS
VDD
0
1
Plot IDS of transistor and Iload of resistor vs. Vout
2 Vin 3
Since currents must be equal, intersection points define VTC
79
Resistive-load inverter: VTC
Drain current IDS
Vin=4V
small R
Vin=3V
VDD
Vin=2V
Vout
VDD
R
large
R
small R
large
R
Vin=1V
Vout = VDS
VDD
2 Vin 3
Changing value of R affects VTC curve

larger R reduces VOL and improves NML but degrades NMH
80
Resistive-load inverter: power

Static power consumption: depends on input voltage Vin
P0 = power when Vin = 0
P1 = power when Vin = 1
Average power depends on input probability

a = probability that Vin = 1
(1-a) = probability that Vin = 0
Pavg = aP1 + (1-a)P0
81
Resistive-load inverter: power

Find P0 and P1:
Vin = 0: NMOS transistor off. No current flows from VDD to Gnd
(except leakage). P0 = 0
Vin = VDD: NMOS transistor on. Output voltage Vout = VOL.
I load
VDD VOL ,
P IV
R
V V V
P1 DD OL DD
R
VDD VOL VDD

Pavg
R
82
Static power consumed

when Vin = VDD
Resistive-load inverter: delay

R
1
IR
ID
R
Cload
IR
Cload
Output falling (Vin = 1):
Output rising (Vin = 0):
Discharge Cload through

NMOS
Charge Cload through resistor
Need large ID, small IR
83
Need large IR

Delay calculation: approximate method
Use an average value of capacitor current IC
Find current at start of transition, and current at end of transition, and
use the average
I avg
td
dV
C
,
dt
V1
C
0 dt V I avg dV
0
C
V1 V0
td
I avg
84
C
dt
dV
I avg
For rise delay:
V0 = 0, V1 = VDD/2
For fall delay:
V0 = VDD, V1 = VDD/2

Inverter rise delay tplh:
Vin
Vout
Beginning of transition:
Vout VOL ,
End of transition:
VDD VOL
IC
R
Vout VDD ,
1
2
Average current:
I avg
Delay:
VDD
IC
2R
3VDD 2VOL
4R
Cload
4 RCload
V1 V0 , t plh
td
12 VDD VOL
I avg
3VDD 2VOL
85

Inverter fall delay tphl:
Beginning of transition: Vout=VDD (NMOS in saturation)
IC 0 12 kn VDD VT
End of transition: Vout=VCC (NMOS in linear)
2
2
I C1 k n VDD VT 12 VDD 14 VDD
k n 14 VDD
12 VT VDD
Average current:
I avg
1
2
I C 0 I C1
Delay:
Cload
Cload
V1 V0 , t phl
td
I avg
I avg
86
12 VDD
Resistive-load inverter: problems
Static power consumption

Tradeoff between delay and power:
For fast operation, need small resistor
For low power, need large resistor
VOL is larger than 0V

Reduced noise margin
Large area
Hard to make large resistance values on chip
87
Pseudo-NMOS inverter
Replace resistor with always-on PMOS
transistor
Easier to implement in standard process
than large resistance value
VDD
G
PMOS load transistor:

On when VGS < VT
VGS = -VDD: transistor always on
VGS,P = -VDD
S
D
Vout
Vin
Linear when VDS > VGS-VT

Vout-VDD > -VDD-VT Vout > -VT
Saturated when VDS < VGS-VT VoutVDD < -VDD-VT Vout < -VT
Gnd
Remember:
VT(PMOS) < 0
88
Pseudo-NMOS inverter: VOH

VOH for pseudo-NMOS inverter:
VDD
Vin = 0
NMOS in cutoff: no drain current
Result: VOH is VDD (as in resistive-load

inverter case)
Vout
Gnd
89
Pseudo-NMOS inverter: VOL

Find VOL of pseudo-NMOS inverter:
Vin = VDD: NMOS on in linear mode
I Dn
k V
n
DD
VTn VOL V
1
2
2
OL
PMOS on in saturation mode (assume)
I Dp k p VDD VTp
1
2
(neglecting l)
Setting Idn = Idp:

1
2
k V kn VDD VTn VOL k p VDD VTp 0

2
n OL
1
2
Key point: VOL is not zero

Depends on thresholds, sizes of N and P transistors
90
Pseudo NMOS inverter: VTC

I/V curve for NMOS:
I/V curve for PMOS:
Vin=3V
Vin=2V
-Drain current -IDS
Drain current IDS
Vin=4V
VGS=-VDD
Vin=1V
VDS = Vout
VDD
-VDS = -(Vout - VDD)

Plot of -IDS vs -VDS since
current is from source to drain
Only one curve since VGS fixed
91
Pseudo NMOS inverter: VTC
Vin=3V
VDD
Vin=2V
Vout
Drain current IDS
Vin=4V
Vin=1V
Vout = VDS
VDD
2 Vin 3
Similar VTC to resistive-load inverter

Sharper transition region, smaller area
92
Depletion-load inverter
Depletion-load inverter: uses depletion
NMOS transistor as load
VDD
Depletion transistor has VT < 0
Load is always on:
VGS = 0 > VT
Body effect of depletion transistor is

significant (when Vout = VOH)
VGS = 0
D
S
Vout
Vin
Gnd
93
Depletion-load inverter
Static characteristics: VOH and VOL

VOH: NMOS driver is off. As long as body effect does not cause
VT(load) > 0, VOH = VDD
VOL: driver in linear mode, depletion load in saturation
1
2
2
knl VTl knd VDD VTd VOL 12 VOL
2
Need to calculate using body-effect coefficient
(solve for VOL) VOL is non-zero

94
95
CMOS INVERTER Lecture 1
Regions of Operation
Noise margin
Inverter capacitances
Delay, Rise and Fall time
CMOS Inverter
Complementary NMOS and PMOS
devices
VDD
In steady-state, only one device is on (no

static power consumption)
Vin=1: NMOS on, PMOS off
Vout = VOL = 0
Vin
Vout
Vin=0: PMOS on, NMOS off

Vout = VOH = VDD
Ideal VOL and VOH!
Gnd
Ratioless logic
97
CMOS Inverter: VTC

PMOS
NMOS
Vin=3V
VDD
Vin=2V
Vout
Drain current IDS
Vin=4V
Vin=1V
Vout = VDS
VDD
2 Vin 3
Output goes completely to VDD and Gnd

Sharp transition region
98
CMOS inverter operation

VDD
NMOS transistor:
Cutoff if Vin < VTN
Linear if Vout < Vin VTN
Vin
Vout
Saturated if Vout > Vin VTN
PMOS transistor
Cutoff if (Vin-VDD) < VTP Vin < VDD+VTP
Linear if (Vout-VDD)>Vin-VDD-VTP Vout>Vin - VTP
Sat. if (Vout-VDD)<Vin-VDD-VTP Vout < Vin-VTP
99
CMOS inverter VTC

P linear
N cutoff
P linear
N sat
P cutoff
N linear
P sat
N sat
P sat
N linear
100
CMOS inverter VTC
VDD
Increase W of PMOS
kp increases
VTC moves to right
kp=kn
kp=5kn
Vout
kp=0.2kn
VDD
Increase W of NMOS
kn increases
VTC moves to left
For VTH = VDD/2
kn = kp
Wn 2Wp
Vin
101
Effects of VTH adjustment

Result from changing kn/kp ratio:
Inverter threshold VTH VDD/2
Rise and fall delays unequal
Noise margins not equal
Reasons for changing inverter threshold

Want a faster delay for one type of transition (rise/fall)
Remove noise from input signal: increase one noise margin at
expense of the other
102
CMOS inverter: VIL

KCL:
kp
kn
2
VGS ,n VT 0,n 2VGS , p VT 0, p VDS , p VDS , p 2
2
2
kn
Vin VT 0,n 2 k p 2Vin VDD VT 0, p Vout VDD Vout VDD 2
2
2
Differentiate and set dVout/dVin to 1
dV
dV
kn Vin VT 0,n k p Vin VDD VT 0, p out Vout VDD Vout VDD out
dVin
dVin
k n VIL VT 0,n k p 2Vout VIL VT 0, p VDD
VIL
103
2Vout VT 0, p VDD k RVT 0,n
1 kR
Solve simultaneously with KCL to find VIL
kR
kn
kp
CMOS inverter: VIH

KCL:
kp
kn
2
2
2VGS ,n VT 0,n VDS ,n VDS ,n VGS , p VT 0, p
2
2
kp
kn
2
2
2Vin VT 0,n Vout Vout Vin VDD VT 0, p
2
2
Differentiate and set dVout/dVin to 1
dV
dV
kn Vin VT 0,n out Vout Vout out k p Vin VDD VT 0, p
dVin
dVin
k n 2Vout VIH VT 0, p k p VIH VDD VT 0, p
VIH
VDD VT 0, p k R 2Vout VT 0,n

1 kR
kR
kn
kp
Solve simultaneously with KCL to find VIH

104
CMOS inverter: VTH

KCL:
kp
kn
2
VGS ,n VT 0,n VGS , p VT 0, p 2
2
2
kp
kn
2
Vin VT 0,n Vin VDD VT 0, p 2
2
2
Solve for VTH = Vin = Vout

VT 0,n
VTH
VDD VT 0, p
kR
1
105
kR
kn
kp
1
kR
CMOS inverter: Ideal VTH

VT 0,n
VTH
VDD VT 0, p
kR
1
kR
kn
kp
1
kR
Ideally, VTH = VDD/2

Assuming VT0,n = VT0,p,
k R ,ideal
k R,ideal 1
VDD 2 VT 0, p
VDD 2 VT 0,n
W

L p n
2. 5
W
p

L n
106
CMOS inverter: VIL and VIH for Ideal VTH

Assuming VT0,n= -VT0,p, and kR = 1,
VIL
1
3VDD 2 VT 0
8
VIH
1
5VDD 2 VT 0
8
VIL VIH VDD

NM L VIL VOL VIL
NM H VOH VIH VDD VIH VIL
107
CMOS inverter: capacitances

VDD
Cgs,p
Csb,p
Cap on node f:
Cgd,p
Cdb,p
Cgd,n
Cdb,n
Cgs,n
Csb,n
Vin
f
Cint
Cg
Junction cap
Cdb,p and Cdb,n
Gate capacitance
Cgd,p and Cgd,n
Interconnect cap
Receiver gate cap
Gnd
108

Junction capacitances Cdb,p and Cdb,n:
Equation for junction cap
m
AC j 0
q N a N d 1
C j V
,
C
j0
m
2 N a N d 0
V
1
0
Non-linear, depends on voltage across junction
Use Keq factor to get equivalent capacitance for a voltage
transition
Cdb AK eqC j PK eqswC jsw

109
Gate capacitances CGD,p and CGD,n:

In steady state, what regions are transistors in?
One is in cutoff: CGD = CGS = 0
One is in saturation: CGD = 0
Therefore, gate-to-drain capacitance is only due to overlap
capacitance:
C gd , p C gd ,n CoxWL D
However, also need to consider Miller effect ...
110

Cgd1
Vout
Vin
Vout
Vin
2Cgd1
When input rises by V, output falls by V

Effective voltage change across Cgd1 is 2V
Effective capacitance to ground is twice Cgd1
Including Miller effect:
C gd , p C gd ,n 2CoxWL D
111

Interconnect capacitance
Due to capacitance of metal and poly lines used to connect
transistors
Complex; includes parallel-plate and fringing-field components
For wide wires:
Cint
ox
tox
WL
tox = thickness of field oxide
Sample capacitances for 1m process:

poly: 0.058 fF/m2
M1: 0.031 fF/m2
M2: 0.015 fF/m2
M3: 0.010 fF/m2
112
Review: CMOS inverter capacitances

Receiver gate capacitance
Includes all capacitances of gate(s) connected to output node
Unknown region of operation for receiver transistor: total gate cap
varies from (2/3)WLCox to WLCox
Ignore Miller effect since operation unknown
Assume worst-case value, include overlap
C g WL eff Cox 2WL D Cox

113
First-order inverter delay

Assume: Current charging or discharging
capacitance Cload is nearly constant Iavg
Vin
Vout
Cload
114
t PHL
Cload
VDD 12 VDD
I avg
t PLH
Cload
I avg
12 VDD VSS
Inverter delay, falling

ID.n
Vin
Cload
Assume PMOS fully off (ID,p = 0)
dV
I C
dt
I D ,n Cload
115
dVout
dt
Need to determine ID,n


NMOS in saturation
VDD
VDD - Vtn
NMOS in linear region
VDD/2
t0 t1 t2
From t0 to t1: NMOS in saturation
From t1 to t2: NMOS in linear region

Find ID in each region
116
CMOS inverter delay

Another approximate method:
Again assume constant Iavg
Iavg = current I1 at start of transition
good approximation esp. for deep

submicron
V1=VDD
I1
V2=VDD
t PHL
CloadVDD
2
k n VDD VTn
t PLH
117
CloadVDD
k p VDD VTP
t1
t2
Iavg = I1
Inverter delay, falling t1-t0
Assumption: Input fast enough to go through transition before output

voltage changes
Vout drops from VDD to VDD-VTN (NMOS saturated)
I DS kn (Vin VT 0,n )2 / 2 kn (VOH VT 0,n )2 / 2

2CL
t dt kn (VOH VT 0,n )2
0
t1
VOH VT 0 , n
dV
out
VOH
2CLVT 0,n
t1 t0
2
kn (VOH VT 0,n )
118
Inverter delay, falling t2-t1

Vout drops from (VOH-VT0,n) to VDD/2
2
I DS kn (VOH VT 0,n )Vout 12 Vout
t2 t1 CL
(VOH VOL ) / 2
VOH VT 0 , n
kn (VOH
dVout
2
VT 0,n )Vout 12 Vout
2(VOH VT 0,n ) (VOH VOL ) / 2

CL
t2 t1
ln
kn (VOH VT 0,n )
(VOH VOL ) / 2
119

Total fall delay =
(t1-t0) + (t2-t1)
2VT 0,n
4(VOH VT 0,n )
CL
t PHL
ln
1
kn (VOH VT 0,n ) VOH VT 0,n

VOH VOL
120
Inverter delay, rising

Similar calculation as for falling delay
Separate into regions where PMOS is in linear, saturation
t PLH
121
k p (VOH
4(VOH VOL VT 0, p )
2 VT 0, p
CL
ln
1
VOH VOL
VOL VT 0, p ) VOH VOL VT 0, p
Inverter rise, fall time

Exact method: separate into regions
t1
Vout drops from 0.9VDD to VDD-VT (NMOS in saturation)
Vout rises from 0.1VDD to VT (PMOS in saturation)
t2
Vout drops from VDD-VT to 0.1VDD (NMOS in linear region)
Vout rises from VT to 0.9 VDD (PMOS in linear region)
tf,r = t1 + t2
122
Inverter rise, fall time
Average current method:

Find current at start and end of transition
Find average and use
fall,rise
123
CV
I avg
How to improve delay?

Minimize load capacitances
Small interconnect capacitance
Small Cg of next stage
Raise supply voltage
Increase transistor gain factor

increase transistor drive current for charging/discharging output
capacitance
124
CMOS inverter delay

Review of exact method
Break transition into regions of operation
Example: tphl (output falling):
NMOS in saturation
VDD
VDD - Vtn
VDD/2
t0 t1 t2
125
CMOS inverter delay

What if input has finite rise/fall time?
Both transistors are ON for some amount of time
Capacitor charge/discharge current is reduced
tpHL(ns)
Empirical equations:
tr
2
t phl (actual) t phl ( step)
2
tf
t plh (actual) t ( step)
2
2
plh
trise(ns)
126
SESSION 3: CMOS LOGIC STRUCTURES

Lecture 1
MOS a Switch
Static CMOS
NAND,NOR
Transistor sizing
Complex Gate
Design techniques
127
Switch-level model
Model transistors as switches and

resistances
Resistance Ron = average resistance for a
transition
For NMOS tphl:
RP
A
Ron 12 RNMOS (Vout VDD ) RNMOS (Vout 12 VDD )

V
Ron 12 DS
I D Vout VDD
128
VDS

I D Vout 12VDD
R
A
CL
Switch-level model
Delay estimation using switch-level model (for general
RC circuit):
R
n
CL
dV
C
I C
dt dV
dt
I
V
RC
I
dt
dV
R
V
V1
RC
t1 t0 t p
dV
V
V0
V1
t p RCln(V1 ) ln(V0 ) RC ln
V0
129
Switch-level model
Delay estimation using switch-level model (for
general RC circuit):
R
n
CL
dV
C
I C
dt dV
dt
I
V
RC
I
dt
dV
R
V
V1
RC
t1 t0 t p
dV
V
V0
V1
t p RCln(V1 ) ln(V0 ) RC ln
V0
130
Switch-level model
For fall delay tphl, V0=VDD, V1=VDD/2
V1
12 VDD
t p RC ln RC ln
VDD
V0
t p RC ln( 0.5)
t phl 0.69RnC L
t plh 0.69R p CL
131
Standard RC-delay
equations
Static CMOS
Complementary pullup network
(PUN) and pulldown network
(PDN)
Only one network is on at a time
PUN: PMOS devices
VDD
In1
In2
In3
PUN
Why?
PDN: NMOS devices
Why?
PUN and PDN are dual
networks
Output is always connected to
VDD or Gnd
132
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks
Dual Networks
Example: NAND gate
Dual networks:
parallel connection in PDN = series
connection in PUN, vice-versa
If CMOS gate implements logic
function F:
PUN implements function F
PDN implements function G = F
133
parallel
B
series
NAND gate
NAND function: F = AB
PUN function: F = A B = A + B
Or function (+) parallel connection
Inverted inputs A, B PMOS transistors
PDN function: G = F = A B
And function () series connection
Non-inverted inputs NMOS transistors
134
NOR gate
NOR gate operation: F = A+B

A
PUN: F = A+B = AB
PDN: G = F = A+B
135
CMOS gate design

Designing a CMOS gate:
Find pulldown NMOS network from logic function or by inspection
Find pullup PMOS network
By inspection
Using logic function
Using dual network approach
Size transistors using equivalent inverter

Find worst-case pullup and pulldown paths
Size to meet rise/fall or threshold requirements
136
Graph-based dual network

Draw network for PUN or PDN
Circuit nodes are vertexes
Transistors are edges
F
F
A
A
B
gnd
137
Graph-based dual network

To derive dual network:
Create new node in each enclosed region of graph
Draw new edge intersecting each original edge
Edge is controlled by inverted input
A
A
138
B
B
A
B
Analysis of CMOS gates

Represent on transistors as resistors
1
W
Transistors in series resistances in series

Effective resistance = 2R
Effective width = W
139
Analysis of CMOS gates

Represent on transistors as resistors
W
W
0
Transistors in parallel resistances in parallel
Effective resistance = R
Effective width = 2W
140
Equivalent Inverter
CMOS gates: many paths to VDD and Gnd

Multiple values for VTH, VIL, VOL, etc
Different delays for each input combination
Equivalent inverter
Represent each gate as an inverter with appropriate device width
Include only transistors which are on or switching
Calculate VTH, delays, etc using inverter equations
141
Static CMOS Logic Characteristics

VTH of the equivalent inverter is used (assumes all inputs
are tied together)
For specific input patterns, VTH will be different
For VIL and VIH, only the worst case is interesting since
circuits must be designed for worst-case noise margin
For delays, both the maximum and minimum must be
accounted for in race analysis
142
Equivalent Inverter: VTH

Example: NAND gate threshold VTH
Three possibilities:
A & B switch together
A switches alone
B switches alone
What is equivalent inverter for each case?
143
Equivalent inverter: delay

Represent complex gate as inverter for delay estimation
Use worse-case delays
Example: NAND gate
Worse-case (slowest) pull-up: only 1 PMOS on
Pull-down: both NMOS on
WP
WP
WN
WP
WN
WN
144
Example: NOR gate

Find threshold voltage VTH when both
inputs switch simultaneously
Two methods:
145
WP
Transistor equations
WP
Equivalent inverter
WNB
F
WN
Example: complex gate

Design CMOS gate for this truth table:
A
F = A(B+C)
146
Example: complex gate

Completed gate:
B
A
What is worse-case pull up delay?

WP
WP
C
What is worse-case pull down delay?
WP
F
A
B
Effective inverter for delay calculation:
WN
WN C
WN
WP
WN
147
Transistor Sizing
Sizing for switching threshold
All inputs switch together
Sizing for delay

Find worst-case input combination
Find equivalent inverter, use inverter analysis to set device

sizes
148
Influence of Fan-In and Fan-Out

VDD
A
Fan-Out: Number of Gates Connected

2 Gate Capacitances per Fan-Out
A
B
FanIn: Quadratic Term due to:
C
D
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
tp = a1 FI + a2 FI 2 + a3 FO
149
tp as a function of Fan-In
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
5
fan-in
tpLH
9
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

150
Complex Gate - Design Techniques

Transistor Sizing:
As long as Fan-out Capacitance dominates
Progressive Sizing:
Out
InN
MN
CL
M1 > M2 > M3 > MN
151
In3
M3
C3
In2
M2
C2
In1
M1
C1
Distributed RC-line
Can Reduce Delay with more than 30%!
Complex Gate - Design Techniques(2)

Transistor Ordering
critical path
critical path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
152
CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)

Improved Logic Design
153

Buffering: Isolate Fan-in from Fan-out
CL
154
CL
CMOS design guidelines

Transistor sizing
Size for worst-case delay, threshold, etc
Tapering: transistors near power supply are larger than transistors
near output
Transistor ordering
Critical signal is latest-arriving signal to gate
Put critical signals closest to output
Stack nodes are discharged by early signals
Reduced body effect on top transistor
155
CMOS design guidelines

Limit fan-in of gate
Fan-in: number of gate inputs
Affects size of transistor stacks
Normally fan-in limit is 3-4
Convert large multi-input gates into smaller chain of gates
Limit fanout of gate

fanout: number of gates connected to output
Capacitive load: affects gate delay
NANDs are better than NORs
156
5 minute break
157
PASS LOGIC and D Latch Lecture 1
Transmission gate
MUX
Tristate Inverter
D Latch, MS register
158
CMOS disadvantages
For N-input CMOS gate, 2N transistors required
Each input connects to an NMOS and PMOS transistor
Large input capacitance: limits fanout
Large fan-in gates: always have long transistor stack in PUN or

PDN
Limits pullup or pulldown delay
Requires very large transistors
Single-stage gates are inverting
159
Pseudo-NMOS logic
Pseudo-NMOS: replace PMOS PUN with single always-on PMOS
device
Same problems as pseudo-NMOS inverter:
VOL larger than 0
static power when PDN is on
Advantages
Replace large PMOS stacks with single device
Reduces overall gate size, input capacitance
Especially useful for wide-NOR structures
160
Transmission Gate Logic
NMOS and PMOS connected in parallel

Allows full rail transition ratioless logic
Equivalent resistance relatively constant during transition
Complementary signals required for gates

Some gates can be efficiently implemented using transmission
gate logic
161
Equivalent Resistance
0V
Vin
Vout
VDD
For a rising transition at the output (step input)

NMOS sat, PMOS sat until output reaches |VTP|
NMOS sat, PMOS lin until output reaches VDD-VTN
NMOS off, PMOS lin for the final VDD VTN to VDD voltage swing
162
Equivalent Resistance Region 1

NMOS sat:
Req,n
VDD Vout
1
2
k n VDD Vout Vtn
PMOS sat:
Req, p
163
VDD Vout
1
2
k p VDD Vtp

NMOS sat:
PMOS lin:
Req,n
Req, p
164
VDD Vout
1
2
k n VDD Vout Vtn
2VDD Vout
2
k p 2VDD VTP VDD Vout VDD Vout
k p 2VDD VTP VDD Vout
Req ,n
NMOS off:
PMOS lin:
165
Req, p
k p 2VDD VTP VDD Vout
Equivalent resistance
Equivalent resistance Req is
parallel combinaton of Req,n
and Req,p
Req is relatively constant
Req,p
Req,n
Req
VTp
Vcc-VTn VDD
Vout
166
Resistance Approximations
To estimate equivalent resistance:

Assume both transistors in linear region
Ignore body effect
Assume voltage difference is small
Req,n
k n VDD Vtn
Req, p
k p VDD Vtp
1
Req
kn VDD Vtn k p VDD Vtp
167
Transmission Gate Logic

Useful for multiplexers (select between multiple inputs) and XORs
Transmission gate implements logic function
F = A if S
If S is 0, output is floating, which should be avoided

Always make sure one path is conducting from input to output
Two transmission gates can implement

AS + BS
TGate 1: A if S
TGate 2: B if S
168
Pass-Transistor Based Multiplexer

S
VDD
VDD
M2
F
S
M1
B
GND
S
169
In1
In2
Transmission Gate XOR
B
M2
A
F
M1
M3/M4
B
170
Switch logic
Can implement Boolean formulas as networks of switches.
Can build switches from MOS transistorstransmission gates.
Transmission gates do not amplify but have smaller layouts.
171
Types of switches
n-type
complementary
172
Behavior of n-type switch
n-type switch has source-drain voltage drop when conducting:
conducts logic 0 perfectly;
introduces threshold drop into logic 1.
VDD
VDD - Vt
VDD
173
n-type switch driving static logic

Switch under-drives static gate, but gate restores logic levels.
VDD
VDD - Vt
VDD
174
n-type switch driving switch logic

Voltage drop causes next stage to be turned on weakly.
VDD
VDD - Vt
VDD -2 Vt
VDD
175
Behavior of complementary switch
Complementary switch products full-supply voltages for

both logic 0 and logic 1:
176
n-type transistor conducts logic 0;
p-type transistor conducts logic 1.
NMOS in SERIES PARALLEL
Switch controlled by the gate input
NMOS switch closes when the gate input is High
Remember - NMOS transistors pass a strong 0 but a weak 1
177
PMOS in SERIES PARALLEL

Switch controlled by the gate input
PMOS switch closes when the gate input is low
Remember - PMOS transistors pass a strong 1 but a weak 0
178
Pass Transistor Logic
Primary inputs drive source/drain terminals as well as gate terminals
N transistors instead of 2N
No static power consumption
Ratioless
Bidirectional (versus undirectional)
179
NMOS Only Switch
VC does not pull up to VDD, but VDD VTn

Threshold voltage drop causes static power consumption (M2 may
be weakly conducting forming a path from VDD to GND)
180
NMOS Only Switch
VC does not pull up to VDD, but VDD VTn

Threshold voltage drop causes static power consumption (M2 may
be weakly conducting forming a path from VDD to GND)
181
Body effect - VSB at x - when pulling high (B is tied to GND and S

charged up close to VDD). So the voltage drop is even worse
Cascaded Pass Transistors
Pass transistor gates should not be cascaded as on the left
182
Tristate Inverter
Tri-state inverters : 0 1 Z
tri-state
inverter
en
When en=0, F is
floating
en
183
Memory elements
Stores a value as controlled by clock.
May have load signal, etc.

In CMOS, memory is created by:
184
capacitance (dynamic);
feedback (static).
Variations in memory elements

Form of required clock signal.
How behavior of data input around clock affects the stored

value.
When the stored value is presented to the output.
Whether there is ever a combinational path from input to
output.
185
Memory element terminology

Latch: transparent when internal memory is being set from
input.
Flip-flop: not transparentreading input and changing output
are separate events.
186
Clock terminology
Clock edge: rising or falling transition.
Duty cycle: fraction of clock period for which clock is active

(e.g., for active-low clock, fraction of time clock is 0).
187
Memory element parameters

Setup time: time before clock during which data input must be
stable.
Hold time: time after clock event for which data input must
remain stable.
clock
data
188
Dynamic latch
Stores charge on inverter gate capacitance:
189
Latch characteristics
Uses complementary transmission gate to ensure that storage
node is always strongly driven.
Latch is transparent when transmission gate is closed.
Storage capacitance comes primarily from inverter gate
capacitance.
190
Latch operation
= 0: transmission gate is off, inverter output is determined

by storage node.
= 1: transmission gate is on, inverter output follows D input.
Setup and hold times determined by transmission gatemust

ensure that value stored on transmission gate is solid.
191
Stored charge leakage

Stored charge leaks away due to reverse-bias leakage
current.
Stored value is good for about 1 ms.
Value must be rewritten to be valid.
If not loaded every cycle, must ensure that latch is loaded
often enough to keep data valid.
192
Non-dynamic latches
Must use feedback to restore value.
Some latches are static on one phase (pseudo-static)load

on one phase, activate feedback on other phase.
193
Re-circulating latch
Static on one phase:
LD
2
LD
2
194
Clocked inverter
circuit
symbol
195
Clocked inverter operation

= 0: both clocked transistors are off, output is floating.
= 1: both clocked inverters are on, acts as an inverter to drive

output.
196
Clocked inverter latch
197
Clocked inverter latch operation

Not transparentuse multiple storage elements to isolate
output from input.
Major varieties:
master-slave;
edge-triggered.
= 0: i1 is off, i2-i3 form feedback circuit.

= 1: i2 is off, breaking feedback; i1 is on, driving i3 and output.
Latch is transparent when = 1.
198
Flip-flops
Not transparentuse multiple storage elements to isolate
output from input.
Major varieties:
199
master-slave;
edge-triggered.
Master-slave flip-flop
master
slave
200
Master-slave operation
= 0: master latch is disabled; slave latch is enabled, but
master latch output is stable, so output does not change.
= 1: master latch is enabled, loading value from input; slave
latch is disabled, maintaining old output value.
201
Signal skew
Machine data signals must obey setup and hold times

avoid signal skew.
If delays along different paths vary significantly, outputs
may not be valid even though inputs are.
202
Signal skew example

Invalid latch input: signals are not aligned:
b
circuit
a
stable
stable
stable
time
5
10
timing diagram
203
Clock skew
Clock must arrive at all memory elements in time to load data.
204
SESSION 4: POWER DISSIPATION

Lecture
Static and Dynamic Power Dissipation
Short Circuit Dissipation
Impact of Rise/Fall Times on Short-Circuit Currents.
Buffer Design Issues
205
CMOS inverter power
Power has three components

Static power: when input isnt switching
Dynamic capacitive power: due to charging and discharging of
load capacitance
Dynamic short-circuit power: direct current from VDD to Gnd when
both transistors are on
206
static power
Static power consumption:
Static current: in CMOS there is no static current as long as Vin < VTN
or Vin > VDD+VTP
Leakage current: determined by off transistor
Influenced by transistor width, supply voltage, transistor threshold
voltages
VDD
VDD
Ileak,p
Vss
VDD
VDD
Vss
Ileak,n
207
Dynamic capacitive power
Evdd ivcc (t )VDD dt

0
dVout
VDD C L
dt
dt
0
VDD
C LVDD dVout
0
Evdd C V
2
L DD
2
Pdyn C LVDD
f
208
Energy for one

complete cycle
(charge and
discharge)
Dynamic capacitive power

Formula for dynamic power:
Pdyn C V
2
L DD
Observations
Does not (directly) depend on device sizes
Does not depend on switching delay
Applies to general CMOS gate in which:
Switched capacitances are lumped into CL
Output swings from Gnd to VDD
Input signal approximated as step function
Gate switches with frequency f
209
Dynamic short-circuit power

Short-circuit current flows from VDD to Gnd when both transistors
are on
Plot on VTC curve:
Imax: depends on
saturation current
of devices
VDD
Imax
Vout
ID
Vin
210
VDD
Dynamic short-circuit power
Imax
Approximate short-circuit current as a triangular wave
Energy per cycle:
Esc VDD
Psc
211
I m axt f t r t f
I m axt r
VDD
VDD I m ax
2
2
2
tr t f
2
VDD I m ax f
Inverter power consumption

Total power consumption
Ptot Pdyn Psc Pstat

Ptot C V
2
L DD
tr t f
f VDD I m ax
2
Energy-delay product:
f VDD I leak
Multiply energy x delay: EDP = E*D

Often the goal of a design is to minimize EDP
212
Power reduction
Reducing dynamic capacitive power:
Lower the voltage!
Quadratic effect on dynamic power
Reduce capacitance
Short interconnect lengths
Drive small gate load (small gates, small fan-out)
Reduce frequency
Lower clock frequency -> use more parallelism
Lower signal activity
213
Power reduction
Reducing short-circuit current:
Fast rise/fall times on input signal
Reduce input capacitance
Insert small buffers to clean up slow input signals before sending
to large gate
Reducing leakage current:

Small transistors (leakage proportional to width)
Lower voltage
214
Inverter design
Consider chain of minimum-sized inverters:
Wp, Wn
Wp, Wn
Cload
Wp, Wn
Cload
Wp, Wn
Cload
Cload
Delay of single
inverter is tp0
Now double the size of each inverter:

2Wp, 2Wn
2Wp, 2Wn
2Cload
215
2Wp, 2Wn
2Cload
2Wp, 2Wn
2Cload
2Cload
What is new
inverter delay?
Inverter chain delay

Neglecting interconnect capacitance:
Both delay and load capacitance scale linearly with inverter
size
Increasing inverter size also increases capacitance -> delay
remains constant
Interconnect cap remains

constant
Increasing inverter size
reduces delay
delay
Including interconnect
capacitance
size
216
Inverter as a buffer
Consider minimum-size inverter driving load Cload:
Wp,Wn
Cg
Cload
Delay of inverter:
Gate cap of min-size inverter = Cg
Delay of min-size inverter driving another min-size inverter =
tp0
Cload xC g ,
217
t p xt p 0
Inverter as buffer
Example:
Assume tp0 = 1ns
Wp,Wn
Wp,Wn
Wp,Wn
Inverter delay = 1ns
20Wp,20Wn
Inverter delay = 20ns!
Reduce delay by inserting extra buffer

What is the optimum ratio u?
Wp,Wn
Cg
218
uWp,uWn
Cload
Inverter as buffer
Total delay = delay of first inverter + delay of buffer:
First inverter has u-times larger load:
delay = utp0
Second inverter has x/u-times larger load:
delay = (x/u)tp0
Total delay:
Wp,Wn
x
x
t p ut p 0 t p 0 u t p 0
u
u
219
Cg
uWp,uWn
Cload
Inverter as buffer
Find factor u which minimizes tp: take derivative of tp wrt u and
set to 0
x
t p ut p 0 t p 0
u
t p
x
t p0 2 t p0 0
u
u
x
1,
uopt x
2
u
t p ,opt 2t p 0 x
220
Inverter as buffer
When should a single-inverter buffer be used?

Only if combined delay of both inverters is faster than unbuffered
case
unbuffered: t p xt p 0
buffered:
t p 2t p 0 x
2t p 0 x xt p 0
x2 x
x4
221
single-inverter buffer is
faster if load is > 4X larger
Superbuffer design
Large fixed load capacitance driven by chain of n
inverters
Stage ratio = u
First inverter is minimum size
Each inverter is u times bigger than previous one
What is optimum u and n ?
1
Cg
222
u2
u3
Cload
Superbuffer design
tp0 = average delay of one inverter driving another one of same size
Delay of each stage = delay of inverter driving another inverter u
times bigger = utp0
Total delay = n u tp0
Ratio of load cap to gate cap:
Cload u nC g
Cload
x
,
Cg
x un
ln( x) n ln(u ),
223
ln( x)
n
ln(u )
number of buffers
required
Superbuffer design
Total delay:
u
Total delay ln( x)
t p0
ln(u )
Optimum stage delay u =
e ~ 2.7
Including interconnect, u
ranges from 3-5
224
Buffer example
20
A minimum-sized inverter (size 1)
needs to drive a fan-out of 4 size 20
inverters
20
1
20
Cg
Find the delay for the (a) nonbuffered, (b) single buffer, and (c)
super-buffer case
20
tp0 = 0.5 ns
225
SESSION 5: DYNAMIC LOGIC Lecture 1
Pre charge evaluate

Charge sharing, leakage
Domino Logic
C2MOS logic
226
Dynamic Logic
VDD
VDD
Mp
Me
Out
CL
In1
In2
In3
PDN
In1
In2
In3
PUN
Out
Me
n network
2 phase operation:
227
Mp
CL
p network
Precharge
Evaluation
Example
VDD
Mp
N + 1 Transistors
Out
Ratioless
No Static Power Consumption
Noise Margins small (NML)

C
Requires Clock
228
Me
Transient Response
6.0
Vout (Volt)
4.0
Vout
EVALUATION
PRECHARGE
2.0
0.0
0.00e+00
229
2.00e-09
t (nsec)
4.00e-09
6.00e-09
Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
230
GND
Charge Sharing
Output is floating after clk = 1 if inputs are 0
If upper transistors in a stack switch, the intermediate and

output node voltages will be equalized, possibly leading to a
drop in the output voltage = noise
Final output
V=(C1V1+C2V2)/(C1+C2)
may be higher if NMOS turns off
C1
231
C2
Charge Leakage & Cap. Coupling

Output is floating after clk = 1 if inputs are 0
Since the current is not 0 when transistors are in cutoff, current

can leak away from the output when all inputs are 0
Changes in input signals couple to the output and intermediate
nodes, also resulting in voltage drops
232
Noise Solutions
Charge sharing:
Ensure the output capacitance is large enough such that the
voltage drop is minimal
Precharge internal stack nodes to VCC
Pre-discharging internal stack nodes can increase performance,
but worsens noise
Charge leakage/sharing and cap. coupling:

Add a keeper PMOS (weak P pullup) increased evaluation
contention
233
Reliability Problems -Charge Leakage
VDD
Mp
Out
(1)
CL
A
Vout
(2)
precharge
evaluate
Me
t
(a) Leakage sources
(b) Effect on waveforms
Minimum Clock Frequency: > 1 MHz

234
Charge Sharing (redistribution)
case 1) if V out < VTn
VDD
Mp
Out
CL
Ma
B=0
235
Mb
Me
X
Ca
Cb
C V
= C V
t + C V
V V
L DD
L out
a DD
Tn X
or
Ca
V out = Vout t V DD = -------- V DD V Tn V X
C
L
case 2) if V out > VTn

C
a
Vout = V DD ----------------------
C +C
a
L
Charge Redistribution - Solutions
VDD
VDD
Mp
Mbl
Mp
Mbl
Out
Out
A
Ma
Ma
Mb
Mb
Me
Me
(a) Static bleeder

236
(b) Precharge of internal nodes

Clock Feedthrough
VDD
could potentially forward

bias the diode
Mp
Out
CL
A
237
Ma
Mb
Me
5V
X
Ca
Cb
overshoot
out
Cascading Dynamic Gates

VDD
VDD
Mp
Mp
Out2
Out1
In
Out1
VTn
In
Out2
Me
(a)
Me
t
(b)
Only 01 Transitions allowed at inputs!
238
Domino Logic
Solves problem of cascading dynamic gates, but is non-inverting
Add an inverter between dynamic gates
Inverter drives the gates fanout increased performance
Sometimes the inverter is replaced with a more complex static CMOS

gate
Static CMOS gate improves dynamic noise margins
Solve non-inverting problem by implementing both F and F separately

Area/power doubles
239
Domino Logic
240
Charge-Based Storage
In
(b) Non-overlapping clocks
(a) Schematic diagram
Pseudo-static Latch
241
Master-Slave Flip-Flop
In
Overlapping Clocks Can Cause

Race Conditions
Undefined Signals
242
2 phase non-overlapping clocks
In
t12
243
2-phase dynamic flip-flop
In
Input Sampled
Output Enable
244
Flip-flop insensitive to clock overlap
VDD
VD D
M2
M6
M4
In
M3
CL1
M8
D
M1
M7
CL2
M5
section
section
C2MOS LATCH
245
C2MOS avoids Race Conditions
VDD
M2
VD D
VDD
VDD
M6
M2
M6
In
1
M3
M1
D
1
In
M8
D
M7
M5
(a) (1-1) overlap
246
M4
M1
M5
(b) (0-0) overlap
Pipelined Logic using C2MOS
VDD
In
VDD
VDD
F
C1
Out
C2
C3
NORA CMOS
What are the constraints on F and G?
247
Example
VDD
VDD
VDD
Number of a static inversions should be even
248
NORA CMOS Modules
VD D
In1
In2
In3
VDD
VDD
PUN
PDN
(a) -module
Combinational logic
VDD
VDD
Latch
VDD
VD D
In 4
In 1
In 2
In 3
PDN
249
Out
Out
In4
(b) -module
Doubled C2MOS Latches
VDD
VDD
VDD
VDD
Out
In
In
Doubled n-C2MOS latch
250
Out
Doubled n-C2 MOS latch
TSPC - True Single Phase Clock Logic
VD D
VDD
VDD
VDD
PUN
In
Static
Logic
Out
PDN
Including logic into

the latch
251
Inserting logic between

latches
Master-Slave Flip-flops
VDD
VDD
(a) Positive edge-triggered D flip-flop
VDD
VD D
VDD
VDD
VDD
VDD
(b) Negative edge-triggered D flip-flop
VDD
(c) Positive edge-triggered D flip-flop

using split-output latches
252
Cascading Domino
For gates with all inputs coming from other domino gates, the
bottom NMOS transistor can be eliminated
Why? All inputs will be 0 during precharge and can only
transition from 0 to 1 during evaluate
Results in increased performance due to decreased stack height
Precharge now depends on input precharge time
253
Dynamic Logic Power

Power depends upon switching activity
Switching activity depends upon the probability of a 1 input
Pavg
1
2
2
CloadVDD
CloadVDD
f
T
Effective capacitance is doubled when the gate evaluates because the

gate must later precharge
Frequency must be multiplied by the probability that an evaluation will
occur
Power is usually higher except for very high activity gates
254
SESSION 6: SCALING of MOS Lecture 1
Velocity saturation
Mobility degradation
Threshold voltage variation
DIBL
Channel length modulation
Scaling
Constant field, constant voltage, Effects of scaling
255
Secondary effects
Short-channel effects:
Short channel device has channel length comparable to depth of
drain and source junctions and depletion width
Causes threshold voltage and I/V curve variations
Narrow-channel effects:
Narrow channel device has small channel width
Sub-threshold conduction (leakage current)
256
Short-channel effects
Short-channel device: channel length is comparable to depth of
drain and source junctions and depletion width
In general, visible when L ~ 1um and below
Short-channel effects:
Carrier velocity saturation
257

Vgs
0
N+
source
Vds
N+
drain
P
Electric field Ey exists along channel

As channel length is reduced, electric field increases (if voltage is
constant)
Electron drift velocity vd is proportional to electric field

only for small field values
for large electric field, velocity saturates
258

Effect of velocity saturation:
Current saturates before saturation region
VDSAT = voltage at which saturation occurs
Drain current is reduced:
I D ( sat ) W vd ( sat ) Cox VDSAT

(no longer quadratic function of VGS)
Saturation region is extended:
VDSAT < VGS-VT
259
MOS I/V equations depend on surface mobility n (or p)
In short-channel devices, n and p are not constant

As vertical electric field Ex increases, surface mobility decreases
1 VGS VT
0 = low-field mobility, is empirical constant

As VGS increases, surface mobility decreases
260

Until now, threshold voltage assumed constant
VT changed only by substrate bias VSB
In threshold voltage equations, channel depletion region

assumed to be created by gate voltage only
Depletion regions around source and drain neglected: valid if
channel length is much larger than depletion region depths
In short-channel devices, depletion regions from drain and source
extend into channel
261

Short-channel effects cause threshold voltage variation:
VT rolloff
As channel length L decreases, threshold voltage decreases
Drain-induced barrier lowering

As drain voltage VDS increases, threshold voltage decreases
Hot-carrier effect
Threshold voltages drift over time
262
Source
depletion
region
N+
source
N+
drain
Drain
depletion
region
Gate-induced
depletion region
Even with VGS=0, part of channel is already depleted
Bulk depletion charge is smaller in short-channel device VT is

smaller
263

Change in VT0:
xdS, xdD: depth of depletion regions at S, D
xj: junction depth
x j
2 xdS
2
x
1
dD
1
VT 0
2q Si N A 2 F
1 1
1

Cox
2 L
xj
xj
VT0 is proportional to (xj/L)

For short channel lengths, VT0 is large
For large channel lengths, term approaches 0
264
Threshold voltage variations

Graphically: VT0 versus channel length L
VT0
Long-channel VT
Lnom
VT Roll-off:
VT decreases rapidly with channel length
265
DIBL
Drain-induced barrier lowering (DIBL)
Drain voltage VDS causes change in threshold voltage
As VDS is increased, threshold voltage decreases
Cause: depletion region around drain

Depletion region depth around drain depends on drain voltage
As VDS is increased, drain depletion region gets deeper and
extends further into channel
For very large VDS, source and drain depletion regions can
meet punch-through!
Issue: results in uncertainty in circuit design
266

Hot-carrier effect
increased electric fields causes increased electron velocity
high-energy electrons can tunnel into gate oxide
This changes the threshold voltage (increases VT for NMOS)
Can lead to long-term reliability problems
267

Hot electrons
High-velocity electrons can also impact the drain, dislodging holes
Holes are swept towards negatively-charged substrate cause
substrate current
Called impact ionization
This is another factor which limits the process scaling voltage
must scale down as length scales
268
Threshold voltage variations

Summary of threshold variations in short-channel devices
VT rolloff: threshold voltage reduces as channel length L

reduces
DIBL: threshold voltage reduces as VDS increases
Hot-carrier effect: threshold voltage drifts over time as

electrons tunnel into oxide
269
Short-channel summary
Long-channel
Short-channel
Both devices have same effective W/L ratio I/V curves should be
similar
Short-channel device has ~ 40% less current at high VDS
Note linear dependence on VGS in short-channel device
270
Sub-threshold conduction
When VGS < VT, transistor is off
However, small drain current ID still flows
Called subthreshold leakage current
Model for subthreshold current:
I D ( subthreshold ) I SWe
q
AVGS BVDS
kT
Increases as VGS increases (potential barrier lowered)

Increases as VDS increases (DIBL)
271
Subthreshold conduction
Exponential relationship to VGS
log IDS(sub)
subthreshold slope
(mV/decade of current)
VT
VGS
Subthreshold slope:
Shift in VGS required to reduce leakage by factor of
10
Typical values: 80-120 mV/decade
272
Gate leakage
Another source of leakage current is gate leakage (Fowler-Nordheim
Tunneling)
For very thin gate oxide, electrons can tunnel through the gate oxide,
resulting in current from gate to drain or source
Equation for gate leakage current:
I FN C1WLEox2 e
E0
Eox
E0, C1 constants
Eox = electric field across oxide
IFN proportional to area of gate

Limits scaling of gate oxide
273
Leakage
Effect of leakage current
Wasted power: power consumed even when circuit is inactive
Leakage power raises temperature of chip
Can cause functionality problem in some circuits: memory,
dynamic logic, etc.
Reducing transistor leakage

Long-channel devices
Small drain voltage
Large threshold voltage VT
274
Leakage
Leakage vs. performance tradeoff:
For high-speed, need small VT and L
For low leakage, need high VT and large L
Process scaling
VT reduces with each new process (historically)
Leakage increases ~10X!
One solution: dual-VT process

Low-VT transistors: use in critical paths for high speed
High-VT transistors: use to reduce power
275
Channel Length Modulation

In saturation, pinch-off point moves
As VDS is increased, pinch-off point moves closer to source
Effective channel length becomes shorter
Current increases due to shorter channel
L L L
'
W
2
I D nCox VGS VTN 1 lVDS
L
1
2
l = channel length modulation coefficient

276
SPICE Model Equations

SPICE Level 1
Approximations (GCA) from SESSION 1
Useful for hand calculations
SPICE Level 2
Variation of mobility with electric field
Variation of channel length in saturation (more accurate)
Subthreshold conduction
SPICE Level 3
Mostly empirical
Accurate to 2m
277
Scaling
Improvement in CMOS process technology. Reduction in device
dimensions, improved circuit performance
First-order constant field scaling

Apply a dimensionless factor > 1 to all dimensions, device
voltages and concentration densities
Constant voltage scaling

VDD is kept constant, process is scaled
Lateral scaling
Only the gate length is scaled (gate shrink)
278
MOSFET Scaling
Constant Voltage
Traditional, board-level compatible
Constant Field
Ideal, helps reliability
Hybrid
practical
279
Scaling
Scaling has a threefold objective:
Reduce the gate delay by 30% (43% increase in frequency)
Double the transistor density
Saving 50% of power (at 43% increase in frequency)
How is scaling achieved?

All the device dimensions (lateral and vertical) are reduced by 1/
Concentration densities are increased by
Device voltages reduced by 1/ (not in all scaling methods)
Typically 1/ = 0.7 (30% reduction in the dimensions)
280
Constant Field
Before Scaling
Length
L/s
Width
W/s
Oxide Thickness
tox
tox/s
Diffusion/Junction Depth
Xj
Xj/s
Supply Voltage
VDD
VDD/s
Threshold Voltage
VT
VT/s
Doping Densities
NA,ND
sNA,sND
E dx
281
After Scaling
V Edx
Constant Voltage
Before Scaling
Length
L/s
Width
W/s
Oxide Thickness
tox
tox/s
Diffusion/Junction Depth
Xj
Xj/s
Supply Voltage
VDD
VDD
Threshold Voltage
VT
VT
Doping Densities
NA,ND
s2NA,s2ND
E dx
282
After Scaling
V Edx
Scaling: Capacitance Effects

Constant Field
Cox,scaled sCox
C g ,scaled
Cg
s
Constant Voltage
Cox,scaled sCox
283
C g ,scaled
Cg
s
Scaling: Current Effects

Constant Field
I D , scaled
ox W s VGS
2 t ox s L s
VT
2
ID
s
s
Current density increases by s
Constant Voltage
I D , scaled
ox W s
2 t ox s L s
VGS VT 2 sI D
Current density increases by s3
284
Scaling: Power Effects

Constant Field
VDS I D P
2
s s
s
P s2
P
W s L s
Pscaled
Pscaled
Ascaled
Constant Voltage
Pscaled VDS sI D sP
Pscaled
sP
s3 P
Ascaled W s L s
285
Scaling: Performance Effects

Constant Field
scaled
C s V s
I s
Constant Voltage
scaled
286
(C / s )V
2
sI
s
Technology scaling
Some consequencies 30% scaling in the constant field regime (s =

1.43, 1/s = 0.7):
Device/die area:
W L (1/s)2 = 0.49
In practice, microprocessor die size grows about 25% per technology

generation! This is a result of added functionality.
Transistor density:
(unit area) /(W L) s2 = 2.04
In practice, memory density has been scaling as expected. (not true for
microprocessors)
287
Technology scaling
Gate capacitance:
W L / tox 1/s = 0.7
Drain current:
Gate delay:
(W/L) (V2/tox) 1/s = 0.7
(C V) / I 1/s = 0.7
Frequency s = 1.43
In practice, microprocessor frequency has doubled every technology

generation (2 to 3 years)! This faster increase rate is due to two factors:
the number of gate delays in a clock cycle decreases with time (the designs
become highly pipelined)
advanced circuit techniques reduce the average gate delay beyond 30% per
generation.
288
Technology scaling
Power:
Power density:
C V2 f (1/s)2 = 0.49
1/tox V2 f 1
Active capacitance/unit-area:
Power dissipation is a function of the operation
frequency, the power supply voltage and of the circuit
size (number of devices).
289
Technology scaling
Interconnects scaling:
Higher densities are only possible if the interconnects also scale.
Reduced width increased resistance
Denser interconnects higher capacitance
290
Technology scaling
To account for increased parasitics and integration
complexity
more interconnection layers are added:

thinner and tighter layers local interconnections
thicker and sparser layers global
interconnections and power
Interconnects are scaling as expected
291
SESSION 7: CMOS Technology Lecture 1
Photolithography
CMOS Fabrication Sequence
Latch up
292
Lithography
Lithography: process used to transfer patterns to each layer of the IC
Lithography sequence steps:

Designer:
Drawing the layer patterns on a layout editor
Silicon Foundry:
Masks generation from the layer patterns in the design data base
Printing: transfer the mask pattern to the wafer surface
Process the wafer to physically pattern each layer of the IC
293
Lithography
Basic sequence
The surface to be patterned is:
1. Photoresist coating
Photoresist
SiO2
spin-coated with photoresist

the photoresist is dehydrated in an oven (photo
resist: light-sensitive organic polymer)
The photoresist is exposed to ultra violet light:

For a positive photoresist exposed areas
become soluble and non exposed areas remain
hard
2. Exposure
Opaque
Ultra violet light
Mask
Exposed
Unexposed
Substrate
The soluble photoresist is chemically removed

(development).
The patterned photoresist will now serve as an
etching mask for the SiO2
294
Substrate
3. Development
Substrate
Lithography
The SiO2 is etched away leaving the

substrate exposed:
4. Etching
the patterned resist is used as the etching

mask
Substrate
Ion Implantation:
5. Ion implant
the substrate is subjected to highly

energized donor or acceptor atoms
The atoms impinge on the surface and
travel below it
The patterned silicon SiO2 serves as an
implantation mask
Substrate
6. After doping
The doping is further driven into the bulk

by a thermal cycle
diffusion
295
Substrate
Lithography
The lithographic sequence is repeated for each physical layer
used to construct the IC. The sequence is always the same:
Photoresist application
Printing (exposure)
Development
Etching
296
Lithography
Patterning a layer above the silicon surface
1. Polysilicon deposition
4. Photoresist developmen t
Polysilicon
SiO2
Substrate
2. Photoresist coating
Substrate
5. Polysilicon etching
photoresist
Substrate
3. Exposure
Substrate
UV light
6. Final polysilicon pattern
Substrate
297
Substrate
Lithography
Etching:
anisotropic etch (ideal)
Process of removing unprotected

material
layer 1
layer 2
Etching occurs in all directions

Horizontal etching causes an under
cut
isotropic etch
undercut
preferential etching can be used to

minimize the undercut
Etching techniques:
Wet etching: uses chemicals to
remove the unprotected materials
Dry or plasma etching: uses ionized
gases rendered chemically active by
an rf-generated plasma
298
resist
resist
layer 1
layer 2
preferential etch
undercut
resist
layer 1
layer 2
CMOS fabrication sequence

0. Start:
For an n-well process the starting point is a p-type silicon wafer:
wafer: typically 75 to 230mm in diameter and less than 1mm thick
1. Epitaxial growth:
A single p-type single crystal film is grown on the surface of the
wafer by:
subjecting the wafer to high temperature and a source of
dopant material
The epi layer is used as the base layer to build the devices
p-epitaxial layer
Diameter = 75 to 230mm
P+ -type wafer
299
< 1mm

2. N-well Formation:
PMOS transistors are fabricated in n-well regions
The first mask defines the n-well regions

N-wells are formed by ion implantation or deposition and diffusion
Lateral diffusion limits the proximity between structures
Ion implantation results in shallower wells compatible with todays fineline processes
Physical structure cross section
Mask (top view)

n-well mask
Lateral
diffusion
n-well
p-type epitaxial layer
300

3. Active area definition:
Active area:
planar section of the surface where transistors are build
defines the gate region (thin oxide)
defines the n+ or p+ regions
A thin layer of SiO2 is grown over the active region and covered with
silicon nitride
Stress-relief oxide
Silicon Nitride
Active mask
n-well
p-type
301

4. Isolation:
Parasitic (unwanted) FETs exist between unrelated transistors (Field
Oxide FETs)
Source and drains are existing source and drains of wanted devices
Gates are metal and polysilicon interconnects
The threshold voltage of FOX FETs are higher than for normal FETs
Parasitic FOX device
n+
n+
n+
n+
p-substrate (bulk)
302

FOX FETs threshold is made high by:
introducing a channel-stop diffusion that raises the impurity concentration in
the substrate in areas where transistors are not required
making the FOX thick
4.1 Channel-stop implant

The silicon nitride (over n-active) and the photoresist (over n-well)
act as masks for the channel-stop implant
channel stop mask = ~(n-well mask)
Implant (Boron)
resit
n-well
p-type
303
p+ channel-stop implant

4.2 Local oxidation of silicon (LOCOS)
The photoresist mask is removed
The SiO2/SiN layers will now act as a masks

The thick field oxide is then grown by:
exposing the surface of the wafer to a flow of oxygen-rich gas
The oxide grows in both the vertical and lateral directions
This results in a active area smaller than patterned
patterned active area
Field oxide (FOX)
n-well
active area after LOCOS
p-type
304

Silicon oxidation is obtained by:
Heating the wafer in a oxidizing atmosphere:
Wet oxidation: water vapor, T = 900 to 1000C (rapid process)
Dry oxidation: Pure oxygen, T = 1200C (high temperature required to achieve an
acceptable growth rate)
Oxidation consumes silicon

SiO2 has approximately twice the volume of silicon
The FOX is recedes below the silicon surface by 0.46XFOX
Field oxide
XFOX
0.54 XFOX
Silicon surface
0.46 XFOX
Silicon wafer
305

5. Gate oxide growth
The nitride and stress-relief oxide are removed
The devices threshold voltage is adjusted by:

adding charge at the silicon/oxide interface
The well controlled gate oxide is grown with thickness tox
n-well
p-type
tox
Gate oxide
tox
n-well
p-type
306

6. Polysilicon deposition and patterning
A layer of polysilicon is deposited over the entire wafer surface
The polysilicon is then patterned by a lithography sequence
All the MOSFET gates are defined in a single step
The polysilicon gate can be doped (n+) while is being deposited to
lower its parasitic resistance (important in high speed fine line
processes)
Polysilicon mask
Polysilicon gate
n-well
p-type
307

7. PMOS formation
Photoresist is patterned to cover all but the p+ regions
A boron ion beam creates the p+ source and drain regions
The polysilicon serves as a mask to the underlying channel

This is called a self-aligned process
It allows precise placement of the source and drain regions
During this process the gate gets doped with p-type impurities
Since the gate had been doped n-type during deposition, the final type (n or p) will
depend on which dopant is dominant
p+ implant (boron)
p+ mask
n-well
Photoresist
p-type
308

8. NMOS formation
Photoresist is patterned to define the n+ regions
Donors (arsenic or phosphorous) are ion-implanted to dope the n+
source and drain regions
The process is self-aligned
The gate is n-type doped

n+ implant (arsenic or phosphorous)
n+ mask
n-well
Photoresist
p-type
309

9. Annealing
After the implants are completed a thermal annealing cycle is
executed
This allows the impurities to diffuse further into the bulk
After thermal annealing, it is important to keep the remaining
process steps at as low temperature as possible
n-well
n+
p+
p-type
310

10. Contact cuts
The surface of the IC is covered by a layer of CVD oxide
The oxide is deposited at low temperature (LTO) to avoid that
underlying doped regions will undergo diffusive spreading
Contact cuts are defined by etching SiO2 down to the surface to
be contacted
These allow metal to contact diffusion and/or polysilicon regions
Contact mask
n-well
n+
p+
p-type
311

11. Metal 1
A first level of metallization is applied to the wafer surface and

selectively etched to produce the interconnects
metal 1 mask
metal 1
n-well
n+
p+
p-type
312

12. Metal 2
Another layer of LTO CVD oxide is added
Via openings are created
Metal 2 is deposited and patterned
Via
metal 2
metal 1
n-well
n+
p+
p-type
313

13. Over glass and pad openings
A protective layer is added over the surface:

The protective layer consists of:
A layer of SiO2
Followed by a layer of silicon nitride

The SiN layer acts as a diffusion barrier against contaminants
(passivation)
Finally, contact cuts are etched, over metal 2, on the passivation
to allow for wire bonding.
314
Yield
Y
The yield is influenced by:

the technology
80
the chip area
60
the layout
40
Scribe cut and packaging also

contribute to the final yield
Yield tendency
100
Yield (%)
number of good chips on wafer

total number of chips
20
1.0 defects/cm2
Yield can be approximated by:
Y e
AD
A - chip area (cm2)
2.5 defects/cm2
5.0 defects/cm2
10
0
10
Chip edge ( area in mm)
D - defect density (defects/cm2)

315
Other processes
P-well process
NMOS devices are build on a implanted p-well
PMOS devices are build on the substrate

P-well process moderates the difference between the p- and the
n-transistors since the P devices reside in the native substrate
Advantages: better balance between p- and n-transistors
p-well
n+
316
p+
n-type
Other processes
Twin-well process
n+ or p+ substrate plus a lightly doped epi-layer (latchup
prevention)
wells for the n- and p-transistors
Advantages, simultaneous optimization of p- and n-transistors:
threshold voltages
body effect
gain
p-well
n-well
n+
epitaxial layer
p+
n+ substrate
317
Other processes
Silicon On Insulator (SOI)
Islands of silicon on an insulator form the transistors
Advantages:
No wells denser transistor structures
Lower substrate capacitances
phosphorus glass or SiO2
S
n+
p-
n+
SiO2
S
p+
n-
polysilicon
D
p+
thinoxide
sapphire (insulator)
318
Other processes
Very low leakage currents
No FOX FET exists between unrelated devices
No latchup
No body-effect:
Radiation tolerance
Disadvantages:
Absence of substrate diodes (hard to implement protection
circuits)
Higher number of substrate defects lower gain devices
More expensive processing
319
Advanced CMOS processes

Shallow trench isolation
n+ and p+-doped polysilicon gates (low threshold)

source-drain extensions LDD (hot-electron effects)
Self-aligned silicide (spacers)
Non-uniform channel doping (short-channel effects)

n+ poly
Silicide
p+ poly
Oxide spacer
n+
p-doping
n+
p+
n-doping
p+
n-well
Shallow-trench isolation
p-type substrate
320
Source-drain
extension
Process enhancements
Up to six metal levels in modern processes
Copper for metal levels 2 and higher

Stacked contacts and vias
Chemical Metal Polishing for technologies with several metal levels
For analogue applications some processes offer:

capacitors
resistors
bipolar transistors (BiCMOS)
321
Latchup
CMOS process contains parasitic bipolar transistors
Under certain conditions, these parasitic transistors can turn on,
shorting power and ground rails and usually destroying the chip
latchup
Avoiding latchup requires certain layout design rules, and careful
control of process
Latchup was a major problem in early CMOS processes
Now, latchup is mainly issue for I/O circuits, with high current
demands and possibly noisy voltages
322
Latchup
substrate tap
NMOS
PMOS
n-well tap
Current flowing in well or substrate can forward-bias bipolar transistor
Positive feedback between transistors: when one turns on, Vdd and Gnd are
connected
Solution: reduce Rnwell and Rpsubs: use many substrate taps in layout
High-current circuits use guard rings
323
SESSION 8: DESIGN RULES Lecture 1
Eular graph
Stick diagrams
Design rules
Layout example
324
Why we need design rules

Masks are tooling for manufacturing.
Manufacturing processes have inherent limitations in

accuracy.
Design rules specify geometry of masks which will provide
reasonable yields.
Design rules are determined by experience
325
Manufacturing problems
Photoresist shrinkage, tearing.
Variations in material deposition.

Variations in temperature.
Variations in oxide thickness.
Impurities.
Variations between lots.
Variations across a wafer.
326
Transistor problems
Variations in threshold voltage:
oxide thickness;
ion implantation;
poly variations.
Changes in source/drain diffusion overlap.

Variations in substrate.
327
Wiring problems
Diffusion: changes in doping
variations in resistance, capacitance.
Poly, metal: variations in height, width

in resistance, capacitance.
- variations
Shorts and opens.
328
Oxide problems
Variations in height.
Lack of planarity -> step coverage
metal 2
metal 2
329
metal 1
Via problems
Via may not be cut all the way through.
Undersize via has too much resistance.

Via may be too large and create short.
330
Constraints on Layout
Resolution constraints
What is the smallest width feature than can be printed
What is the smallest spacing that will guarantee no shorts
Depends on lithography and processing steps that follow

Resolution often depends on the smoothness of the surface
need to keep the image in focus, since depth of field is small
Most modern processes are planarized, to keep surface flat
331
Constraints on Layout
Alignment/overlap constraints
Like printing a color picture, need to align layers to each other

Need to choose which layer to align to
That layer will have better registration than the others.
332
Design Rules
Interface between designer and process engineer
Guidelines for constructing process masks

Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
333
MOSIS SCMOS design rules

Designed to scale across a wide range of technologies.
Designed to support multiple vendors.

Designed for educational use.
Ergo, fairly conservative.
334
l and design rules
l is the size of a minimum feature.
Specifying l particularizes the scalable rules.

Parasitics are generally not specified in l units.
335
Resolution design rules

Minimum line-width:
Minimum width
smallest dimension
permitted for any object in
the layout drawing (minimum
feature size)
Minimum spacing:
smallest distance permitted

between the edges of two
objects
This rules originate from the
resolution of the optical printing
system, the etching process, or
the surface roughness
336
Minimum spacing
l and design rules

Contacts and vias:
Contact
metal 1
minimum size limited by the

lithography process
large contacts can result in
cracks and voids
Dimensions of contact cuts
are restricted to values that
can be reliably
manufactured
A minimum distance
between the edge of the
oxide cut and the edge of
the patterned region must be
specified to allow for
misalignment tolerances
(registration errors)
337
n+
p
Contact size
d
metal 1
d
n+ diffusion
Registration tolerance
x2
metal 1
x1
n+ diffusion
l and design rules

MOSFET rules
n+ and p+ regions are formed
in two steps:
the active area openings
allow the implants to
penetrate into the silicon
substrate
the nselect or pselect
provide photoresist
openings over the active
areas to be implanted
Since the formation of the
diffusions depend on the
overlap of two masks, the
nselect and pselect regions
must be larger than the
corresponding active areas to
allow for misalignments
338
Correct mask sizing

overlap
x
active
n+
p-substrate
x
nselect
Incorrect mask sizing
overlap
x
active
n+
x nselect
p-substrate
l and design rules

Gate overhang:
The gate must overlap the
active area by a minimum
amount
This is done to ensure that
a misaligned gate will still
yield a structure with
separated drain and
source regions
A modern process has may
hundreds of rules to be
verified
Programs called Design
Rule Checkers assist the
designer in that task
339
gate overhang
no overhang
no overhang
and misalignment
Short circuit
CMOS Process Layers
340
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Representation
Wires
341
metal 2
metal 1
pdiff/ndiff
poly
Intra-Layer Design Rules

Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
Metal1
2
2
Metal2
3
342
Transistor Layout
2
3
2
3
1
343
Vias and Contacts

In SCMOS, the spacing from contacts is often slightly larger
than base material
Poly contact to poly spacing is 3 l
Diffusion contact to diffusion is 4 l
This is done so the fabricator can make the surround of the

actual contact cut slightly larger than 1 l, if needed
344
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
345
Select Layer
2
3
Select
2
1
3
Substrate
346
Well
CMOS Inverter Layout
In
GND
VD D
Out
(a) Layout
A
n
p-substrate
+
Field
Oxide
(b) Cross-Section along A-A

347
Stick diagrams
A stick diagram is a cartoon of a layout.
Does show all components/vias (except possibly tub ties),
relative placement.
Transistor 1 is to the right of transistor 2, and under transistor 3
Does not show exact placement, transistor sizes, wire lengths,

wire widths, tub boundaries.
Each wire is assigned a layer, and crossing wires must be on
different layers
348
Stick Diagrams
But
Wires are drawn as stick figures with no width

The size of the objects is not to scale
If you forgot a wire you can squeeze it in between two other wires
It does not have to be beautiful
It is faster to draw a stick diagram first with pencils and paper
349
Stick layers
metal 2
metal 1
poly
ndiff
pdiff
350
Dynamic latch stick diagram
VDD
in
out
VSS
phi
351
phi
Using the Design Rules
SCMOS design rules are simplified, there are still a number of rules to
remember.
Begin with a stick diagram of the cell you want to layout.
Use a subset of the rules to estimate what the layout will look like,
if it meets your standards-begin the actual layout.
Good idea to have a plan on where things go before you start.
Warning:
Layout is often (sometimes) fun to do- can be an infinite time sink
Can find a way to shrink the cell a few more microns.
352
Layout Issues
In CMOS there are two types of diffusion
ndiff (green surrounded by hatched pwell)

Poly crossing ndiff makes NMOS transistors
pdiff (green surrounded by dotted nwell)

Poly crossing pdiff makes PMOS transistors
Be careful, ndiff and pdiff are different
Cant directly connect ndiff to pdiff

Must connect ndiff to metal and then metal to pdiff
Cant get ndiff too close to pdiff because of wells

Large spacing rule between ndiff and pdiff
Means you need to group NMOS devices together and PMOS devices together
353
Basic Layout Planning

Simple guidelines to CMOS layouts
You need to route power and ground. (in metal)

No one will auto connect it for you.
Keep NMOS devices near NMOS devices and PMOS devices near PMOS
devices.
So NMOS usually are placed near Gnd, and PMOS near Vdd You need
to route power and ground. (in metal)
No one will auto connect it for you.
Run poly vertically and diffusion horizontally, with metal1 horizontal (or the
reverse, just keep them orthogonal)
Good default layout plan
354
Basic Layout Planning

Simple guidelines to CMOS layouts
Keep diffusion wires as short as possible (just connect to transistor)

All long wires (wire that go outside a cell, for example) should be in
either m1 or m2.
Try to design/layout as little stuff as possible (use repetition/tools)
Critical issue
355
Typical Cell Layout Plan

The Parity
(note: no PMOS and no Vdd Gnd) (very unusual)
Even
Even Out
Odd
Odd Out
A
A_b
CMOS Inverter/Buffer
Vdd
Gnd
A
356
A_b
Estimating Area from Sticks
Draw stick diagram
Find the critical length path in X and in Y
Count the number of contacted pitches

If transistors are not minimum width, remember to take that into account
If you not happy with the answer, goto step 1 and try again.
Else you are done, and you can try to layout the cell.
May miss the real critical length path
Will get better at seeing the critical path as you do more layout.
357
CMOS gate layout
Goal: minimum area

Method
Minimize diffusion breaks (reduces capacitance on internal nodes)
Align transistors with common gates above each other in layout
(minimizes poly length)
Group PMOS and NMOS transistors together
Approach:
Use Euler path method to find ordering of transistors in layout
358
Layout: Euler path method

Goal: layout without diffusion breaks
Method for finding ordering of transistors in layout Euler

path
Euler path path through a graph that traverses each edge
only once
Find common Euler path in pullup and pulldown graph

This gives the ordering of inputs in the layout
359
Euler path method

Example: complex CMOS gate
F
C
Vdd
D
B
D
B
gnd
NMOS network
Euler path: BACED
PMOS network
Euler path: BACED
Common Euler path!

360
Layout: Euler path method

C
D
VDD
D
A
F
F
C
D
Gnd
E
Euler path: BACED
361
1.
2.
3.
Order transistors gates according to

Euler path
Connect VDD and Gnd
Make other connections according
to circuit diagram
Example: x = (ab+cd)
x
x
c
VDD
x
a
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}

VD D
x
GND
a
(c) stick diagram for ordering {a b c d}
362
CMOS layout styles

Full-custom
Design broken into complex logic blocks
Each block is laid out by hand
Limited re-usability
Standard cell
Design broken into gates, either by logic designer or automated
synthesis tool
Library of standard cells created
Correct cells chosen from library, connected by layout designer or
place and route tool
363
Standard cells
Example standard cell gates:
inverters, buffers, XOR gates
2,3,4-input NAND, NOR

And-Or-Invert (AOI) gates
Or-And-Invert (OAI) gates
Latches, flip-flops, etc
Multiple versions of each gate:

Designed for different output loads
Detailed specifications
Delays for each input combination
364
365

Cmos Funda Full Course

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SESSION 1: MOS THEORY

CADENCE DESIGN SYSTEMS, INC.

Diffusion current: electrons and holes move from high

Fermi levels line up

Bias Effect on Depletion Width

When biased, electric field in depletion region changes

Reverse bias: increases electric field

Electric field is a result of uncovered charges. Therefore

Bias Effect on Depletion Width

Capacitance of P/N Junction

Separated charges result in depletion region capacitance

MOS capacitor: two-terminal MOS structure

Body or substrate terminal

MOS Energy Band Diagram

Work function (qM, qS): energy required to take

MOS Energy Band Diagram

Part of voltage drop occurs across oxide, rest occurs

Built-in potential of MOS system

MOS capacitor operation

Three regions of operation

Inversion (VG >> 0)

Holes accumulate on Si surface (surface is more

Depletion region forms: devoid of carriers

Bands bend downwards near surface

Depletion region depth

Depletion region depth (cont.)

Depletion region charge

MOS transistor operation

MOS transistor operation

MOS transistors Types and Symbols

NMOS Enhancement NMOS Depletion

Gate voltage to offset fixed charges in gate oxide and

Threshold voltage (1)

Threshold voltage (2)

Threshold voltage (3)

Calculate charge at inversion (S =-F)

For non-zero substrate bias (VSB 0):

Threshold voltage (3, cont.)

Threshold voltage (4)

Correct for non-ideal fixed charges

Final threshold voltage formula (for NMOS):

Replacing second term:

Threshold voltage, summary

Body effect (substrate-bias) coefficient:

Threshold Voltage (NMOS vs. PMOS)

Substrate Fermi potential

Depletion charge density

Substrate bias coefficient

Substrate bias voltage

Threshold voltage adjustment

Opposite for PMOS

Approximate change in VT0:

Assume all implanted impurities are ionized

MOS EQUATIONS Lecture 1

Cut-off, Linear, Saturation

37 CADENCE DESIGN SYSTEMS, INC.

MOS transistor characteristics

Cutoff: VGS < VT

VGS < VTN

VGS > VTP

Depletion region no inversion

Drain end depth reduces as VDS is increased

Linear I/V Equation

Gradual Channel Approximation: