Cmosvlsi Devicech PSR

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MOSFET CURRENT-VOLTAGE
CHARACTERISTICS
& SS MODEL
Dr Sreehari Rao Patri

ECE Department, N.I.T.Warangal
patri@nitw.ac.in
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CHIP DESIGN CENTER NITW
MOS Device Structure
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NMOS and PMOS with Well
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MOS Symbols
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Etymology
The 'metal' in the name is now often a
misnomer because the previously metal
gate material is now a layer of polysilicon
Previously aluminium was used as the gate
material until the 1980s when polysilicon
became dominant, owing to its capability
to form self-aligned gates.
IGFET is a related, more general term
meaning
insulated-gate
field-effect
transistor, and is almost synonymous with
MOSFET, though it can refer to FETs with a
gate insulator that is not oxide.
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Composition
Usually the semiconductor of choice is silicon
But some chip manufacturers, most notably IBM, have
begun to use a mixture of silicon and germanium (SiGe) in
MOSFET channels.
Unfortunately, many semiconductors with better electrical
properties than silicon, such as gallium arsenide, do not
form good semiconductor-to-insulator interfaces and thus
are not suitable for MOSFETs.
However there continues to be research on how to create
insulators with acceptable electrical characteristics on
other semiconductor material.
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Composition Contd..
To overcome power consumption increase
due to gate current leakage, high-
dielectric is replacing silicon dioxide as
the gate insulator, and metal gates are
making a comeback by replacing polysilicon
The gate is separated from the channel by a
thin
insulating
layer
of
what
was
traditionally silicon dioxide, but more
advanced
technologies
used
silicon
oxynitride.
Some companies have started to introduce a
high- dielectric + metal gate combination in
the 45 nanometer
node
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The primacy of MOSFETs

In 1960, Dawon Kahng and Martin M. (John)
Atalla at Bell Labs invented the metal oxide
semiconductor field-effect transistor (MOSFET).
Operationally and structurally different from
Shockley's bipolar junction transistor,
the
MOSFET was made by putting an insulating
layer on the surface of the semiconductor and
then placing a metallic gate electrode on that.
It used crystalline silicon for the semiconductor
and a thermally oxidized layer of silicon dioxide
for the insulator.
The silicon MOSFET did not generate
localized electron traps at the interface
between the silicon and its native oxide layer,
and thus was inherently free from the trapping
and scattering of carriers that had impeded the
performance of earlier
field-effect transistors. 8
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Primacy contd..
Following the (expensive) development of
i)
clean rooms to reduce contamination
ii)
photolithography and the planar
process to allow circuits to be made in very
few steps,
the Si SiO2 system possessed technical
attractions such as low cost of production
(on a per circuit basis) and ease of
integration.
Largely because of these two factors, the

MOSFET has become the most widely used
type of integrated circuit.
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CMOS circuits
The principal reason for the success of the MOSFET was the
development of digital CMOS logic, which uses p- and nchannel MOSFETs as building blocks.
Overheating is a major concern in integrated circuits since
ever more transistors are packed into ever smaller chips.
CMOS logic reduces power consumption because no current
flows (ideally), and thus no power is consumed, except
when the inputs to logic gates are being switched.
CMOS
accomplishes
this
current
reduction
by
complementing every nMOSFET with a pMOSFET and
connecting both gates and both drains together.
A high voltage on the gates will cause the nMOSFET to
conduct and the pMOSFET not to conduct and a low voltage
on the gates causes the reverse.
During the switching time as the voltage goes from one
state to another, both MOSFETs will conduct briefly. This
arrangement greatly reduces power consumption and heat
generation.
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Digital
The growth of digital technologies like the
microprocessor has provided the motivation to
advance MOSFET technology faster than any
other type of silicon-based transistor.
A big advantage of MOSFETs for digital
switching is that the oxide layer between the
gate and the channel prevents DC current from
flowing through the gate, further reducing
power consumption and giving a very large
input impedance.
The insulating oxide between the gate and
channel effectively isolates a MOSFET in one
logic stage from earlier and later stages, which
allows a single MOSFET output to drive a
considerable number of MOSFET inputs.
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Digitalcontd..
Bipolar transistor-based logic (such as TTL)
does not have such a high fanout capacity.
This isolation also makes it easier for the
designers to ignore to some extent loading
effects between logic stages independently.
That extent is defined by the operating
frequency: as frequencies increase, the input
impedance of the MOSFETs decreases
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Analog
The MOSFET's advantages in most digital circuits do
not translate into supremacy in all analog circuits.
The two types of circuit draw upon different features
of transistor behavior.
Digital circuits switch, spending most of their time
outside the switching region, while analog circuits
depend on MOSFET behavior held precisely in the
switching region of operation.
The bipolar junction transistor (BJT) has traditionally
been the analog designer's transistor of choice, due
largely to its higher transconductance and its higher
output impedance (drain-voltage independence) in the
switching region.
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MOSFETSSUITABILITYANALOG
CKTS OVER BJTS
Nevertheless, MOSFETs are widely used in many
types of analog circuits because of certain
advantages.
The characteristics and performance of many analog
circuits can be designed by changing the sizes (length
and width) of the MOSFETs used.
By comparison, in most bipolar transistors the size of
the device does not significantly affect the
performance.
MOSFETs' ideal characteristics regarding gate current
(zero) and drain-source offset voltage (zero) also
make them nearly ideal switch elements, and also
make switched capacitor analog circuits practical.
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In their linear region, MOSFETs can be used as

precision resistors, which can have a much higher
controlled resistance than BJTs.
In high power circuits, MOSFETs sometimes have the
advantage of not suffering from thermal runaway as
BJTs do.
Also, they can be formed into capacitors and gyrator
circuits which allow op-amps made from them to
appear as inductors, thereby allowing all of the
normal analog devices, except for diodes (which can
be made smaller than a MOSFET anyway), to be built
entirely out of MOSFETs.
This allows for complete analog circuits to be
made on a silicon chip in a much smaller space
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Some ICs combine analog and digital MOSFET circuitry on a

single mixed-signal integrated circuit, making the needed
board space even smaller.
This creates a need to isolate the analog circuits from the
digital circuits on a chip level, leading to the use of isolation
rings and Silicon-On-Insulator (SOI).
The main advantage of BJTs versus MOSFETs in the analog
design process is the ability of BJTs to handle a larger
current in a smaller space.
Fabrication processes exist that incorporate BJTs and
MOSFETs into a single device.
Mixed-transistor devices are called Bi-FETs (Bipolar-FETs)
if they contain just one BJT-FET and BiCMOS (bipolarCMOS) if they contain complementary BJT-FETs.
Such devices have the advantages of both insulated gates
and higher current density.
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BJTS BOLD FACE

BJTs have some advantages over MOSFETs for at
least two digital applications.
Firstly, in high speed switching, they do not have the
"larger" capacitance from the gate, which when
multiplied by the resistance of the channel gives the
intrinsic time constant of the process.
The intrinsic time constant places a limit on the
speed a MOSFET can operate at because higher
frequency signals are filtered out.
Widening the channel reduces the resistance of the
channel, but increases the capacitance by the exact
same amount.
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Reducing the width of the channel increases

the resistance, but reduces the capacitance
by
the
same
amount.
R*C=Tc1,
0.5R*2C=Tc1, 2R*0.5C=Tc1.
There is no way to minimize the intrinsic
time constant for a certain process.
Different processes using different channel
lengths, channel heights, gate thicknesses
and materials will have different intrinsic
time constants.
This problem is mostly avoided with a BJT
because it does not have a gate.
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The second application where BJTs have an advantage over

MOSFETs stems from the first.
When driving many other gates, called fanout, the resistance of the
MOSFET is in series with the gate capacitances of the other FETs,
creating a secondary time constant.
Delay circuits use this fact to create a fixed signal delay by using a
small CMOS device to send a signal to many other, many times
larger CMOS devices.
The secondary time constant can be minimized by increasing the
driving FET's channel width to decrease its resistance and
decreasing the channel widths of the FETs being driven,
decreasing their capacitance.
The drawback is that it increases the capacitance of the driving
FET and increases the resistance of the FETs being driven, but
usually these drawbacks are a minimal problem when compared to
the timing problem.
BJTs are better able to drive the other gates because they can
output more current than MOSFETs, allowing for the FETs being
driven to charge faster.
Many chips use MOSFET inputs and BiCMOS outputs.
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MOS FET driven by gate voltage

What happens
when gate voltage
increases from
zero?
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Formation of depletion region

As VG becomes more
positive, the holes in
the p-substrate are
repelled from the gate
area
This leaves negative
ions behind so as to
mirror the charge on
the gate
DEPLETION region is
created
NO current flows, since
NO charge carriers are
available.
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On set of Inversion
As VG increases
width of dep regn
increases
Potential at the oxide
silicon interface
increases
The structure
resembles two
capacitors in series:
gate oxide capacitor
and depletion region
capacitor
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Interface is INVERTED
When the interface
potential
reach
sufficiently
positive
value, electrons flow
from the source to
surface and eventually
to drain
Thus the channel of
the charge carriers is
formed under the gate
oxide between S and
D.
the tst is turned ON
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Threshold voltage
The value of VG for which this INVERSION
takes place is called THRESHOLD
VOLTAGE
If VG raises further, the charge in the
depletion
region
remains
relatively
constant, while the channel charge
density continues to increase
Provides a greater current from S to D
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Quantification of VTH
The TURN ON phenomenon is a
GRADUAL function of gate voltage
How to define VTH UNAMBIGUOUSLY?
VTH of NFET is defined as the gate
voltage for which the interface is As
much n-type as the substrate is
P-type
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Nsub is the doping concentration of the

substrate
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In practice, the native

threshold value obtained
from the equation may
not be suited to the
circuit design.
E.g. VTH=0 and the
device may not TURN
OFF for VG0
The threshold voltage is
typically
adjusted
by
implantation of dopants
into the channel area
during fabrication
This alters the doping
level of the substrate
near oxide interface.
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Consider a semiconductor bar carrying current I.

The charge density along the direction of current
is Qd coulombs per meter.
Velocity of the charge is m/sec
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I/V characterization
Measure the total charge that passes

through a cross section of the bar in unit
time.
With velocity , all of the charge
enclosed in meters of the bar must
flow through the cross section in one
second.
I Qd .
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MOS I/V CH
Consider an NFET whose S & D are connected to ground.

Refer fig shows channel charge with equal drain and source voltages.
What is the charge density in the INVERSION layer?
Since onset of the INVERSION occurs at VGS = Vth, the INVERSION charge
density produced by the gate oxide capacitance proportional to V GS -Vth.
For VGS > VTH, any charge placed on the gate must be mirrored by the charge in
the channel
This yields a uniform channel charge density.
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Charge density (charge / unit length) is

Qd = WCox(VGS -Vth).
where Cox is capacitance per unit area.
Cox.W = Ctotal/L = capacitance per unit

length
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CASE 2: Drain Voltage VD > 0
Fig: Channel charge with unequal drain and source voltages.

Since channel potential varies from zero at the source to V D at the drain.
Local voltage difference between gate and channel varies from V G to VG - VD
Thus the charge density at point x along the channel is Q d= W Cox[VGS - V(x) Vth].
where V(x) is the channel potential at x.
Current density ID = -WCox[VGS - V(x) - Vth].
Note: Negative sign is due to the charge carriers (i.e. electrons).
is the velocity of electrons in the channel.
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= E ,
where is the mobility of charge carriers,
E is the electric field.
Qd (x) = WCox[VGS - V(x) - Vth].
where V(x) is channel potential at x.
Current ID = -WCox[VGS - V(x) - Vth]
ID = -WCox[VGS - V(x) - Vth] E
ID = WCox[VGS - V(x) - Vth] (dV/dx)
V(0) = 0; V(L) =VDS ;
Integrating both sides w.r.t dx
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Evaluation of ID
Since ID is constant along the length of the

channel,
L is effective channel length.

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Fig:
Drain
current
verses Drain- source
voltage in the triode
region.
Observations:
Current capability of
the device INCREASES
with VGS.
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Q) What is the peak current and for which value of

VDS it occurs?
Calculate Id/ VDS and equate it to 0
It yields VDS = (VGS VTH)
Corresponding ID,max = . n COX (W/L) (VGS
VTH)2
Where W/L aspect ratio, (VGS VTH) is over
drive voltage.
If VDS< VGS - Vth , then the device operates in
the TRIODE region.
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For VDS << 2(VGS - Vth)

ID n COX (W/L) (VGS VTH)VDS
Observations:
Id is a linear function of VDS.
For small VDS, each parabola can be approximated by a straight line.
For VGS << 2(VGS Vth), the device operates in DEEP TRIODE region.
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MOS FET as controlled linear resistor

This linear relationship between ID and VDS
implies that the path from S to D can be
represented by a linear RESISTOR, Ron
Where Ron = VDS / ID
=VDS/{(n COX (W/L) (VGS VTH)VDS}
=1/[n COX (W/L) (VGS VTH)]
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Variation of Ron with VG
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Q) When VDS > VGS - Vth what

happens?
Will ID follow
parabolic path?
NO!
Indeed ID becomes
relatively constant.
Implies transistor is
in saturation region.
How?
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Density of INVERSION
layer charge is
proportional to [VGS V(x) VTH].
If Vx [VGS VTH], then
Qd(x) drops to zero.
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Channel pinch off

In the other words;
from the Figure if
VDS is slightly greater
than VGS VTH, then
INVERSION
layer
STOPS at x L.
Implies the channel
is PINCHED OFF.
As
VDS
increases
more, a point at
which Qd=0 MOVES
towards the source.
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Thus at some point along the channel, local potential

difference between the gate and oxide silicon interface is
NOT SUFFICIENT to support an INVERSION layer.
Recall the equation for ID
ID = WCox[VGS - V(x) - Vth] (dV/dx)
Integration now is to be taken from ?

X=0 to x=L
Where L is the point at which qd drops to zero.
This corresponds to RHS limits V(x)=0 to V(x)= VGS-VTH
This gives ID = n Cox (W/ L ) (VGS-VTH)2
Observation:
ID is IND of VDS if L remains close to L.
For PMOS
ID = p Cox (W/ L ) (VGS-VTH)2
It is assumed that ID flows from D to S whereas holes from
S to D Since p = n; PMOS suffers from lower current
driving capability.
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Saturated mosfet as current source?
With approximate L=L, a saturated

MOSFET can be used as a current
source connected between D and S.
Observations:
Current sources INJECT current
into ground or draw current
from VDD.
Only ONE terminal of each
current source is FLOATING.
Since MOSFET (saturated) produces
a current in response to its G-S OD
voltage, a figure of merit can be
defined that indicates how well a
DEVICE converts a voltage to
current.
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Figure of merit gm
gm represents SENSITIVITY
of the device.
For high gm, a SMALL change
in VGS results in a LARGE
change in ID.
Observations:
gm in saturation = 1/Ron in
deep triode region.
Alternatively,
Substitute
(VGS-VTH) in gm expression
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gm variation as a function of V,I

Observations:
Eq. (1) indicates that gm increases with OD if W/L is
constant.
Eq. (2) indicates that gm increases with ID if W/L is
constant.
Eq. (2) indicates that gm decreases with OD if ID is
constant. biasing style
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gm in triode region
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Example
For
the
arrangement
shown, plot the gm as a
function of VDS
Let VDS is decreasing
from infinite
So long as VDS > Vgs-Vth,
tst is in sat
gm is constant
When VDS < Vgs-Vth, tst is
in triode region
gm ? with VDS
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Water analogy of MOSFET
Source: water reservoir

Drain: water reservoir
Gate: gate between source and drain reservoirs
Want to understand MOSFET operation as a function of:
gate-to-source voltage (gate height over source water
level)
drain-to-source voltage (water level difference between
reservoirs)
Initially consider source tied upto body (substrate or back).
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Cut off regn

MOSFET: VGS < VT , VGD < VT with VDS > 0.
Water analogy: gate closed; no water can flow
regardless of relative height of source and drain
reservoirs.
Id=0
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Triode regn
MOSFET: VGS > VT , VGD > VT, with VDS > 0.

Water analogy: gate open but small difference in height
between source and drain; water flows.
Electrons drift from source to drain electrical current!
VGS |Qn| ID
VDS Ey ID
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Saturation
MOSFET: VGS > VT , VGD < VT (VDS > 0).
Water analogy: gate open;
water flows from source to drain, but free-drop on
drain side
total flow independent of relative reservoir height!
ID independent of VDS: ID = IDsat
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Sat contd..
At pinch-off:
charge control equation inaccurate
around VT
electron concentration small but not
zero
electrons move fast because electric
field is very high
dominant electrostatic feature: acceptor
charge
there is no barrier to electron flow (on the
contrary!)
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Clarification on notation
As VG-VD of an NFET
drops below VTH pinch
off occurs
If VG-VD of a PFET is
NOT large enough,
(<|VTP|), the device is
saturated.
This view does not
require the knowledge
of source voltage.
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BODY EFFECT
Q) What happens if bulk voltage of NFET DROPS below the

source voltage?
So far we presume that S and B are at the same potential.
Fig: NMOS with negative bulk voltage.
Let VS = VD = 0; VG < VTH.
Depletion region is formed but NO INVERSION layer.
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Variation of depletion region charge with bulk voltage
As VB becomes more negative, more holes are attracted towards to sub

connection, leaving a large negative charge behind
DEPLETION REGION becomes WIDER.
Threshold voltage is a function of the total charge in the DEPLETION REGION
because the gate must mirror Qd before an INVERSION layer is created.
As VB drops and Qd increases then VTH also increases.
This called BODY EFFECT or BACK GATE EFFECT.
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Vth with body effect
where Body effect coefficient

= 0.3 or 0.4 V1/2 typically.
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Example
Plot the drain current if VX varies from
infinite to 0.
Assume
VTH0=0.6V,
gamma=0.4v0.5,2F=0.7V
When VX is sufficiently negative, Vth
exceeds 1.2VM1 is OFF
1.2=0.6+0.4{sqrt[0.7-Vx1]-sqrt(0.7)}
Vx1=-4.76V
Vx1< Vx<0,
ID increases according to
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Threshold voltage with body effect

eqn summary
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For the Body effect to manifest itself, the

bulk potential Vsub NEED NOT change
If the source voltage changes w.r.t SUB, the
same phenomenon occurs.
.Ex: consider Fig
CASE1 :ignore the body effect
Fig: A Circuit in which VSB varies with input
level.
Ignore body effect (let substrate be
connected to source)
As Vin increases, Vout=?
since Id I1(constant),source potential
should rise as Vin increases
I1 = n W/L Cox[Vin- Vout- VTH]2
Vout=(Vin-VGS) closely follows Vin
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Illustration of Body effect

CASE 2 : Substrate is connected
to ground.
As Vin becomes more positive,
Vout also becomes more positive
(since Id = I1const)
Potential
difference
between
source and bulk increases, VTH
raises.
Vin Vout (VGS) must increase
so as to maintain Id constant.
Body Effect is usually
undesirable.
Change in threshold voltage
complicates analog design.
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CHANEL LENGTH MODULATION:
Recall, Actual length of

INVERTED
channel
gradually decreases as
potential
difference
between gate and drain
increases.
L is a function of VDS.
This
effect
is
called
channel
length
modulation.
is channel length
modulation coefficient.
For longer channels is
small
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Sub threshold conduction

For VGS=Vth, a
WEAK inversion
layer still exists
and some current
flows from D to S.
For VGS<Vth, , ID is
finite
It exhibits
EXPONENTIAL
dependence on VGS
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SUB THRESHOLD CONDUCTION

PROS AND CONS
gm = n Cox (W/ L ) (VGS-VTH)
Q. Is it possible to achieve an arbitrarily larger

transconductance by increasing W and maintaining ID
constant?
Q. Is it possible to achieve an higher transconductances
than bipolar tst (Ic/VT) biased at the same current?
If W increases while ID remains constant, then VGSVTH
and the device enters sub threshold region.
Hence gm is calculated from ID/(VT)
This implies that MOSFETs are inferior to bipolar transistors
The expn. dependence of ID on VGS larger gains!
However since such conditions are met only by large device
width or low drain current, the SPEED of the sub threshold
device is SEVERELY LIMITED.
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MOS FET Layout
Birds eve view and TOP view

Layout is determined by both
electrical properties required of
the device in the circuit and the
design rules imposed by the
technology.
E.g. W/L is chosen to set the
transconductance or other ckt
parameters, while the MIN L is
dictated by the process.
The gate polysilicaon and the
source and drain terminals are
typically tied to metal aluminum
wires that serve as interconnects
with
low
resistance
and
capacitance.
To accomplish this, one or more
contact windows must be opened
in each region, filled with metal
and connected to the upper metal
wires
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MOS FET Capacitance

A
capacitance
exists
between every two of the
four terminals of a MOSFET.
The value of each cap
depends
on
the
bias
conditions
Oxide cap:C1 = W L Cox
Dep cap between ch and
sub C2
C3 = C3 =Cov Overlap cap
gaate poly-S/D = W LD Cox
C5= Jn cap bet S/D and
Sub. =bottom plate cap
+side wall cap
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Layout for Low Capacitance with

folded structure
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G-S and G-D Capacitances with

VGS
CGB is usually neglected in sat and triode regns

because the inversion layer acts as shield
between gate and bulk region
if the gate voltage varies, charge is supplied by
the source and drain, rather than the bulk.
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JUNCTION CAPACITANCE
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LINEARIZING THE JUNCTION

CAPACITANCE
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MOS Small Signal Models

The quadratic eqns discussed sofar are derived from
the large-signal model of MOSFETs..
Such a model is essential in analyzing circuits in
which the signal significantly disturbs the bias points,
specifically if non non linear effects are of concern.
If the perturbation in bias condition is small, a smallsignal model , i.e. an approximation of large signal
model around the operating point can be employed to
simplify calculations.since in many analog ckts, MOS
FETs are employed in SAT, corresponding model is
considered
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SS model is derived by producing a small increment in a

bias point and calculating the resulting increment in other
bias parameters.
Recall Drain current is a fn of G-S voltage
a voltage dependent current source equal towing to the
gmVGS is employed.
The low frequency impedance between G and S is very high
Owing to the channel length modulation, ID also varies with
VDS
This effect can also be modeled by Voltage dependent
current source
But a current source whose value depends upon the voltage
across it is equivalent to a linear resistor.
It is modeled by a resistor ro or rds tied between D and S
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Recall that bulk potential

influences
the
threshold
voltage and hence the G-S
overdrive.
With all other terminals held
at a consant voltage, the
drain current is a function of
the bulk voltage.
Thus the bulk behaves as
second gate.
This dependence is modeled
as
a
current
source
connected between D and S,
this is written as gmb Vbs
gmb = ID/ VBS
=gm where = gmb/gm
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Behavior of MOS device as a

capacitor
If the S,D, and B of NFET are grounded and
gate voltage rises, an inversion layer
begins to form for VGSVTH
Recall that for 0<VGS<VTH, device
operates in sub threshold condition
Now consider NFET shown.
Tst now can be considered as 2 terminal
device
Its capacitance for different gate voltages is
analyzzed
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Begin with a negative

gate source voltage
The negative potential on
the gate attracts holes in
the substrate to oxide
interface
MOSFET
operates
in
accumulation region
The 2 terminal device
can be viewed as a
capacitor having unitarea capacitance because
the 2 plates of the
capacitor are separated
by tox
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As Vgs rises, the density of

the holes at the interface falls
A depletion region begins to
form under the oxide
Device enters weak inversion
region
In this mode, the capacitance
consists
of
the
series
combination of Cox and Cdep.
As Vgs exceeds Vth, oxide
silicon interface sustains a
channel and the
unit area
capacitance returns to Cox
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End of session
Than Q
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Dr Sreehari Rao Patri

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MOS Device Structure

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NMOS and PMOS with Well

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The primacy of MOSFETs

Largely because of these two factors, the

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In their linear region, MOSFETs can be used as

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Some ICs combine analog and digital MOSFET circuitry on a

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BJTS BOLD FACE

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Reducing the width of the channel increases

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The second application where BJTs have an advantage over

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MOS FET driven by gate voltage

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Formation of depletion region

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Nsub is the doping concentration of the

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In practice, the native

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Consider a semiconductor bar carrying current I.

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Measure the total charge that passes

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Consider an NFET whose S & D are connected to ground.

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Charge density (charge / unit length) is

Cox.W = Ctotal/L = capacitance per unit

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CASE 2: Drain Voltage VD > 0

Fig: Channel charge with unequal drain and source voltages.

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Since ID is constant along the length of the

L is effective channel length.

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Q) What is the peak current and for which value of

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For VDS << 2(VGS - Vth)

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MOS FET as controlled linear resistor

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