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Mitigating antenna effect in IC design

Learn how to manage the antenna effect, which can potentially cause yield and
reliability problems during the manufacturing of MOS integrated circuits.
By Gagan Kansal
Layout Design Engineer
Freescale Semiconductors
and
Ajay Sharma
Lead Engineer
Freescale Semiconductors
Over several decades, the density and speed of ICs have risen exponentially, following a trend described by Moores
Law. While it is accepted that this exponential improvement trend will end, it is still not clear that exactly how
dense and fast integrated circuits will get by the time this point is reached. With the increasing density and Gate
oxide width reducing with each technology node, many effects which were common in VLSI are becoming important
and difficult to manage. One of those effects is Antenna Effect. The semiconductor technology has been continuously
improved over the past two decades and has led to ever smaller dimensions, higher packaging density, faster
circuits, and lower power dissipation.

Figure 1: The collected net charges are channeled to the gate.

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Antenna effect
The Antenna Effect or Plasma Induced Gate Oxide Damage is an effect that can potentially cause yield and reliability
problems during the manufacturing of MOS integrated circuits. Presently Lithographic processes for IC fabrication
use Plasma etching (or dry etching). Plasma is an ionized/reactive gas used to etch. It allows super control of
pattern (shaper edges / less undercut) and also allows several chemical reactions that are not possible in traditional
(wet) etch. But life is not always so good. Several unwanted effects also accumulate. One of them is the charging
damage.
Plasma charging damage refers to the unintended high-field stressing of the gate-oxide in MOSFET during plasma
processing. During Plasma Etching high amount of charge can collect on poly and metal surfaces. Through
capacitive coupling, large electric fields may develop over gate oxides, resulting in stresses that cause oxide
breakdown and shifts in threshold voltage Vt of the device. The collected net charges are channeled to the gate as
shown in figure 1 where it is neutralized by the current tunnelling across the gate-oxide.
Clearly, the size of the conductor exposed to the plasma plays a role in determining the magnitude of the net charge
collection rate and therefore the tunnelling current. This is the so called antenna effect. The area ratio of the
conductor to the oxide under the gate is the antenna ratio. The antenna ratio, in a rough sense, is a current
multiplier that amplifies the tunnelling current density across the gate-oxide.
For a given antenna ratio, a larger tunnelling current is supported when the plasma density is higher. Higher
tunnelling current means higher damage. For the conductor layer pattern etching processes, the amount of
accumulated charge is proportional to perimeter length. For ashing processes, the amount of accumulated charge is
proportional to area. For contact etching processes, the amount of accumulated charge is proportional to area of via.
Classically, the antenna ratio (AR) is defined as the ratio of total area and/or perimeter of conducting layer attached
to gate, to the total gate area.
The classical theory predicts that the amount of degradation is directly proportional to the AR, with the charging
effect identical for each metal layer. However, AR was found to have little or no dependence on antenna effect.
There are also layout dependencies that need to be considered.
Layout dependency of charging damage
The extent of charging damage is a function of the geometry that is connected to the gate-dense-line antennae. But it
is also affected by electron shading effects, by etch rate differences in reactive ion etching (RIE), by plasma ashing
and oxide deposition (plasma-induced damage or PID). Hence a new model of antenna effect should be considered
taking into account the etch time factor as shown in formula 1. A better predictor of antenna effect can be expressed
with formula 2.

Formula 1

Formula 2
According to this new model, the PID has little to no dependence on AR, but the ratio of antenna capacitance to gate
capacitance is good indicator of PID. The plasma-induced damage depends upon the frequency of the plasma power
source. For oxides under 4nm, plasma-induced damage is not particularly sensitive to stress current. Increasing the
dielectric constant of the gate without increasing J can decrease the PID.
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Design solution to reduce antenna effects


There are several design solutions to reduce antenna effects. The routing options mean breaking signal wires and
route the signal to upper metal layers by jumper insertion. All the metal being etched is not connected to a gate until
the last metal layer is etched.
One can also use dummy transistors by adding extra gates to reduce the capacitance ratio, but there may be reverse
antenna effects. Another solution is to connect reverse biased diodes to the gate of transistor (during normal circuit
operation, the diode does not affect functionality). Alternatively, after placement and route, designers could connect
diodes only to those layers with antenna violations. One diode can be used to protect all input ports that are
connected to the same output ports. Jumper insertion is the most effective method of avoiding antenna-effect
problems while diode insertion can repair the remaining antenna problems.

Figure 2: Jumper insertion breaks up a long wire so that the wire connected to the gate input is shorter and less
capable of collecting charge.

Figure 3: Two nets with the same separation between the input and output pins, but slightly different jumper locations.
Jumper insertion
A jumper is a forced layer change from one metal layer to another, and then back to the same layer. Jumper
insertion breaks up a long wire so that the wire connected to the gate input is shorter and less capable of collecting
charge, as shown in figure 2.
It should be noted that the location where we are putting the jumper is very important. We have to put the jumper
in such a way so as to decrease the length of the route. Figure 3 shows two nets with the same separation between
the input and output pins, but slightly different jumper locations. The first one has no antenna violation but the
second one is having Antenna violation. This example shows that antenna violations can be avoided through the use
of jumpers (also known as bridges). A jumper directs the net to a higher metal layer before descending again. In
the process of metallisation, the pin is connected to a small amount of wire area, except on the highest layer,
avoiding any antenna problem below that layer.
Diode insertion
As shown in figure 4, diode insertion near a logic gate input pin on a net provides a discharge path to the substrate
so that built-up charges cannot damage the transistor gate. Using diodes, we are actually providing a discharge path
for the extra ions that accumulates on the metal through the substrate. Unfortunately, diode insertion increases cell
area and slows timing due to the increase of logic gate input load. Moreover, diode insertion is not feasible in
regions with very high placement utilisation.
During the IC manufacturing process, the metal layer is exposed to conditions that lead to the build-up of an
electrostatic charge. The amount of charge that builds up depends on a number of factors; the most important from
an antenna standpoint is how much metal is exposed. As more metal is exposed, the maximum charge that
accumulates on the net that the metal is part of also increases. The substrate remains at ground since it is connected
to the fabrication device. As a result a voltage gradient develops across the gate oxide. When this gradient becomes
large enough, it is relieved via an explosive discharge (i.e. lightning). The problem is more significant at smaller
technologies because the damage resulting from the discharge is more likely to extend across the entire length of
the gate.
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Figure 4: Diode insertion near a logic gate input pin on a net provides a discharge path to the substrate so that built-up
charges cannot damage the transistor gate.

Figure 5: When the metal layer is eventually connected through the higher-level metal bridge, it is no longer exposed
to the charge accumulation and again does not contribute to an antenna violation.

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Antenna rule checking is different for every process technology because the method for expressing antenna ratio is
not standardised. Antenna repair is accomplished by inserting a reverse-bias diode on the violating net as close to
the gates being protected as practical. During normal chip operation, the reverse bias prevents electrons from
flowing from the net through the diode and into the chips substrate.
During fabrication, however, the charge on the net can build to the point where the voltage drop across the diode
exceeds its break-down voltage. This voltage is greater than the normal operating voltage, but less than the voltage
at which an electrostatic discharge at the gate can be expected. When this happens, the diode allows electrons to
flow from the net to the substrate and thus limits how much charge can accumulate on the net. The process is nondestructive, and its possible that the net could discharge through the diode several times during the fabrication
process.
The other way to repair is to break up the antenna by shifting briefly to a different metal. When this metal layer is
fabricated, the long piece on one side is no longer electrically connected to the gate and does not contribute to any
antenna effects. When it is eventually connected through the higher-level metal bridge, it is no longer exposed to
the charge accumulation and again does not contribute to an antenna violation (figure 5). 

About the authors


Gagan Kansal is Layout Design Engineer at Freescale Semiconductors, Noida, India.
Ajay Sharma is Lead Engineer at Freescale Semiconductors, Noida, India.

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