Linear Integrated Circuits Unit1 Raghudathesh VTU

Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
LINEAR INTEGRATED CIRCUITS (VTU) - 10EC46

UNIT - 1
Operational Amplifier Fundamentals: Basic Op-Amp circuit, Op-Amp parameters: Input &
output voltage, CMRR & PSRR, offset voltages & currents, Input & output impedances, Slew
rate & Frequency limitations Op-Amps as DC Amplifiers Biasing Op-Amps, Direct coupledVoltage Followers, Non-inverting Amplifiers, Inverting amplifiers, Summing amplifiers,
Difference amplifier.
7 Hours.
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TEXT BOOKS:
1. Operational Amplifiers and Linear ICs, David A. Bell, 2 nd edition, PHI/Pearson, 2004.
2. Linear Integrated Circuits, D. Roy Choudhury and Shail B. Jain, 2 nd edition, Reprint 2006,
New Age International.
Special Thanks To:
Faculty: Rajappa H S (Asst Professor, ECE, GMIT)
The starting point of all achievement is desire.

Every noble work is at first impossible.
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Quotes:
D
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BY:
RAGHUDATHESH G P
Asst Prof
ECE Dept, GMIT
Davangere 577004
Cell: +917411459249
Mail: datheshraghubooks@gmail.com
Website: raghudathesh.weebly.com
A moments insight is sometimes worth a lifes experience.
The true secret of happiness lies in taking a genuine interest in all the details of daily life.
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Dare to live the life you have dreamed for yourself. Go forward and make your dreams come true.
Department of ECE
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
LIC:
Abbreviated as Linear Integrated Circuits.
Definition1: An Integrated Circuit (IC) is a miniature, low cost electronic circuit

consisting of active and passive components fabricated together on a single crystal of
silicon. The active components are transistors and diodes and passive components are
resistors and capacitors.
Definition2: An Integrated Circuit (IC), sometimes called a chip or microchip, is a

semiconductor wafer on which thousands or millions of tiny resistors, capacitors, and
transistors are fabricated. An IC can function as an amplifier, oscillator, timer, counter,
computer memory, or microprocessor.
Classification:
A particular IC is categorized as either linear (analog) or digital, depending on
its intended application.
Linear ICs:
They have continuously variable output that depends on the input signal level
(they have infinite state changes). As the term implies, the output signal level is a
linear function of the input signal level.
Ideally, when the instantaneous output is graphed against the instantaneous input,
the plot appears as a straight line.
Applications: audio-frequency (AF) and radio-frequency (RF) amplifiers.
Operational Amplifier (op amp) is a common device in these applications.
Digital ICs:
They operate at only a few defined levels or states, rather than over a continuous
range of signal amplitudes.
Applications: used in computers, computer networks, modems, and frequency
counters.
The fundamental building blocks of digital ICs are logic gates, which work with
binary data, that is, signals that have only two different states, called low (logic 0)
and high (logic 1).
Advantages of ICs over discrete circuits:

1. Minimization & hence increased equipment density.
2. Cost reduction due to batch processing.
3. Increased system reliability
4. Improved functional performance.
5. Matched devices.
6. Increased operating speeds
7. Reduction in power consumption.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Operational Amplifier:
Definition: An Operational Amplifier, or op-amp for short, is fundamentally a voltage
amplifying device are having very high gain integrated circuit amplifiers which is
basically a three-terminal device consists of two high impedance inputs, one called the
Inverting Input, marked with a negative sign, ( - ) and the other one called the Noninverting Input, marked with a positive sign ( + ). The third terminal having low
impedance represents the output which can both sink and source either a voltage or a
current.
The inputs are identified as non-inverting input and inverting input because of the way in
which they affect the output voltage.
The basic circuit of an operational amplifier consists of a differential amplifier input

stage and an emitter - follower output stage.
The term OP-AMP is used to denote an amplifier which can be configured to perform
various operations like amplification, subtraction, differentiation, addition, integration
etc.
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Circuit Symbol and Terminals:
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Figure 1.1 shows there are two input terminals, one output, and two supply terminals.
The two input terminals of the operational amplifier are designated inverting input
(identified with a minus sign) and non-inverting input (plus sign).
Input signal at the inverting input terminal produces an inverted output (Phase), and any
input to the non-inverting terminal generates a non-inverted output (Phase).
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Figure 1.1 Circuit and IC symbol for an operational amplifier (op-amp)
The supply terminals are identified as + VCC (the positive supply terminal) and VEE the
negative supply terminal). Typical supply voltages for operational amplifiers range from
9 V to 22 V.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Characteristics of Ideal OPAMP:

Voltage Gain is infinite (AV = )
Open loop gain is infinite
Input impedance is infinite (Ri = )
Output impedance zero (Ro = 0)
Bandwidth is infinite ( BW = )
Gain Independent of Frequency
Zero input voltage offset, i.e., Vo = 0 when V1 = V2
Zero power supply rejection ratio ( PSRR =0) i.e. output voltage is zero when power
supply VCC = 0
9. No change in the characteristic feature with change in temperature
10. Infinite Common mode rejection ratio (CMRR = )
11. Infinite slew rate (S = )
1.
2.
3.
4.
5.
6.
7.
8.
Some typical operational amplifier packages are illustrated in Fig. 1.2.
Figure 1.2: Opamp Packages
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Packaging:
The plastic dual-in-line (DIP) package in Fig. 1.2(a) has eight terminals, only five of
which are normally used for a basic operational amplifier.
The TO-5 metal can-type package shown in Fig. 1.2(b) also uses only five of its eight
terminals.
As with other semi-conductor devices, a metal can package can normally dissipate more
heat than a plastic container.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
But DIP packages are usually the least expensive and they can be more compact than
metal can containers.
Block Diagram Representation of Op-amp:

Op-amps are available in an integrated circuit form. Commercial integrated circuit opamps usually consist of four cascaded blocks.
The block diagram of IC op-amp is shown in the Figure 1.3 below
Figure 1.3: Internal block schematic of an op-amp
Input Stage:
The input stage requires:
High input impedance to avoid loading on the sources.
It requires two input terminals.
It also requires low output impedance.
All such requirements are achieved by using the dual input, balanced output
differential amplifier as the input stage.
The function of a differential amplifier is to amplify the difference between the
two input signals. The differential amplifier has high input impedance. This stage
provides most of the voltage gain of the amplifier.
Intermediate Stage:
The output of the input stage drives the next stage which is an intermediate stage.
This is another differential amplifier with dual input, unbalanced i.e. single ended
output.
The overall gain requirement of the op-amp is very high. The input stage alone
cannot provide such a high gain.
The main function of the intermediate stage is to provide an additional voltage
gain required.
Practically, the intermediate stage is not a single amplifier but the chain of
cascaded amplifiers called multistage amplifiers.
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Level Shifting Stage:

All the stages are directly coupled to each other.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
As the op-amp amplifies DC signals also, the coupling capacitors are not used to
cascade the stages.
Hence the DC. quiescent voltage level of previous stage gets applied as the input
to the next stage. Hence stage by stage DC. level increases well above ground
potential. Such a high DC voltage level may drive the transistors into saturation.
This further may cause distortion in the output due to clipping. This may limit the
maximum AC output voltage swing without any distortion.
Hence before the output stage, it is necessary to bring such a high DC voltage
level to zero volts with respect to ground. The level shifter stage brings the DC
level down to ground potential, when no signal is applied at the input terminals.
Then the signal is given to the last stage which is the output stage.
The buffer is usually an emitter follower whose input impedance is very high.
This prevents loading of the high gain stage.
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Output Stage:
The basic requirements of an output stage are low output impedance, large a.c.
output voltage swing and high current sourcing and sinking capability.
The push-pull complementary amplifier meets all these requirements and hence
used as an output stage.
This stage increases the output voltage swing and keeps the voltage swing
symmetrical with respect to ground.
The stage raises the current supplying capability of the op-amp.
Overall block diagram is as shown below
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Figure 1.4: Op-amp Internal Architecture
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Basic Operational Amplifier Circuit:

The basic circuit of an operational amplifier is shown in the figure 1.5 below
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Figure 1.5: The basic circuit of an operational amplifier has a differential amplifier input stage and an emitter follower output
The circuit is provided with a +VCC and VEE supply voltages, and the two input
terminals are grounded.
Transistors Q1 and Q2 constitute a differential amplifier, which produces a voltage change

at the collector of Q2 when a difference input voltage is applied to the bases of Q 1 and Q2.
Transistor Q3 operates as an emitter-follower to provide low output impedance.

The DC output voltage level at the emitter of Q3 is obtained by applying KVL to the loop
+VCC, RC, Q3, base of Q3 and output.
Assume that Q1 and Q2 are matched transistors, that is they have equal VBE levels and
equal current gains.
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------- (1)
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Then, with both transistor bases at ground level, the emitter currents are equal, and both
IEl and IE2 flow through the common emitter resistor, RE. Thus, total emitter current could
be calculated as
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Appling KVL to the loop from base of transistor Q2, RE and VEE supply we get,
--------- (2)
Hence,
Also,
Substituting IC2 in equation (1) we get,
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Given that Vcc = +10 V, V EE = - 10 V, RE = 4.7 k, RC = 6.8 k, and all transistors have
VBE = 0.7 V.
Scenario1: With both input terminals at ground level we shall find the output voltage
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Scenario2: A positive-going voltage is applied to the non-inverting input terminal and

inverting input terminal is grounded.
When a positive-going voltage is applied to the non-inverting input terminal, Q1 base is
pulled up by the input voltage, and its emitter terminal tends to follow the input signal.
Since Q1 and Q2 emitters are connected together, the emitter of Q2 is also pulled up by the
positive-going signal at the non-inverting input terminal.
The base voltage of Q2 is fixed at ground level so the positive-going movement at its
emitter causes a reduction in its base-emitter voltage (VBE2). The result of the reduction in
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
VBE2 is that its emitter current is reduced and consequently its collector current is
reduced.
Let, the positive-going input at the base of Q1 reduces IC2 by 0.2 mA (1.0 to 0.8 mA).
This gives a new level of output voltage as,
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Conclusion: The output voltage has changed from +2.5 V to +3.9 V, a change of +1.4 V. It is
seen that a +ve going signal at the non-inverting input terminal has produced a positive-going
output voltage.
Scenario3: A positive-going voltage is applied to the inverting input terminal and noninverting input terminal is grounded.
Here, Q2 base is pulled up, the base-emitter voltage of Q2 is increased, and that of Q1 is
reduced by a similar amount. This results in an increase in I E2 and a consequent increase
in IC2.
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Let us assume that a 0.2 mA change occurs in IC2. Thus, IC2 is increased from 1 mA to 1.2
mA by the positive-going voltage at the inverting input terminal. The output voltage can
now be calculated as
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Conclusion: The output voltage has now changed from its original level of +2.5 V to +1.1V, a
change of -1.4 V. Therefore, the positive-going signal at the inverting input terminal produced a
negative-going voltage change at the output.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
A Basic Operational Amplifier Circuit Consists:

1. A differential amplifier stage with two (inverting and non-inverting) input terminals
and
2. A voltage follower output stage.
The differential amplifier offers high impedance at both input terminals and it produces
voltage gain.
The output stage gives the op-amp low output impedance.
A practical operational amplifier circuit is much more complex than the basic circuit.
Input Voltage Range:
The maximum positive going and negative going input voltage that is applied to an OpAmp is termed as its input voltage range.
Ex: For Op-Amp 741 typical input range is 13V when using a 15V supply.
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Output Voltage Range:
The maximum output voltage swing is limited by the input voltage range.
The op-amp is connected to function as either a non-inverting or inverting amplifier; the

output voltage may be much larger than the input.
Just how far the output voltage can swing in positive or negative direction depends on the
supply voltage and the op-amp output circuitry.
A rough approximation for most operational amplifiers is that the maximum output
voltage swing is approximately equal to 1 V less than the supply voltage.
For the 741 op-amp with a supply of 15 V, the data sheet lists the output voltage swing
as typically 14 V when RL 10 k.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
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Common Mode Rejection Ratio:
Figure 1.6: Basic op-amp circuit with the two input terminals connected together, and a common mode input voltage applied.
Common Rejection Ratio (CMRR) is defined as the ability of Op-Amp in rejecting

common mode inputs. CMRR is also defines as the ratio of the open-loop gain M to the
common mode gain Acm.
CMRR expressed in decibels as,
The common mode voltage gain Acm is defined as the ratio of change in the output
voltage to the change in common mode input voltage.
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From the figure 1.6 we see that the two input terminals are connected together and both
are raised to 1V above ground level. This is known as a common mode input.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Here we see that there is no differential input; both input terminals are at the same
potential. So ideally the output should be zero.
As the base voltages of Q1 and Q2 are raised to 1V above ground, the voltage drop across
emitter resistor RE is increased by 1V, and, consequently, IC1, and IC2 are increased.
The increased level of IC2 produces an increased voltage drop across resistor RC, which
results in a change in the output voltage at the emitter of Q 3.
Similarly, if a -1V common mode input is applied, IC2 falls, and again a change is
produced at the circuit output.
The effect of op-amp common mode gain is modified by feedback. Consider the noninverting amplifier circuit in Figure 1.7.
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Figure 1.7: A common mode input voltage appears at both input terminals of a non-inverting opamp
The output voltage is given by,
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Any output voltage will produce a feedback voltage across resistor R 2, which results in a
differential voltage at the op-amp input terminals.
The differential input produces an output which tends to cancel the output voltage that
caused the feedback. The differential input voltage required to cancel V o(cm) is,
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Op-AmpFundamentals
RAGHUDATHESH G P
Vd is also the feedback voltage developed across R2 hence,
Hence,
Here,
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Power Supply Voltage Rejection:
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Asst Professor
For a basic op-amp circuit a variation in -VEE could have essentially the same effect as an
input voltage change. Hence, variations in VCC and VEE do produce some changes at the
output.
The power supply rejection ratio (PSRR) is a measure of how effective the operational
amplifier is in dealing with variations in supply voltage.
Ideally, the output voltage should not vary with variations in the power supply voltage.
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If a variation of 1V in VCC or VEE causes the output to change by 1V, then the supply
voltage rejection ratio is 1V per volt (1V/V).
If the output changes by 10 mV when one of the supply lines changes by 1V, then the
supply rejection ratio is 10mV/V.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
For the 741 operational amplifier, the supply voltage rejection ratio is specified as
typically 30V/V.
Input Offset Voltage:

Definition1: Input offset voltage is the amount of input voltage that should be
applied between two input terminals of an op-amp in order to force the output voltage
to zero.
The origin of input offset voltage is due to the mismatch between the transistors of
the input stage of the op-amp i.e, VBE1 VBE2
Definition2: Output offset voltage is a DC voltage present at the output terminal of

an op-amp when both the input terminals are grounded.
Consider a internal circuit of op-amp voltage follower circuit as shown below
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For the output voltage to be exactly equal to the input, the transistor Q 1 and Q2 must
be perfectly matched.
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Figure 1.8: internal circuit of op-amp voltage follower circuit
Determining the output voltage by applying KVL to Vi, VBE1, VBE2 and output V0.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Scenario1: Say both transistors are matched VBE1 = VBE2 and Vi = 0
Output is given as
V
Scenario2: Say both transistors are not perfectly matched hence VBE1 = 0.7V and
VBE2 = 0.6 V and Vi = 0
Output is given as
The above unwanted output voltage is known as an output offset voltage.
To set the output voltage to ground level, the input would have to be raised/increased
to +0.1 V. This is termed an input offset voltage (Vos).
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Typical input offset voltage for 741 op-amp is 1 mV.

Input offset Current (Ios):
Definition: The algebraic difference between two input currents flowing into the two
input terminals of an op-amp.
Input transistors of an operational amplifier not being perfectly matched that is, the
transistor base-emitter voltages being unequal, the current gain (hFE) of one transistor
may not be exactly equal to that of the other.
Thus, when both transistors have equal levels of collector current, the base current in one
might be 1A while the other has a base current of 1.2 A.
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The difference these two input current levels is known as the input offset current (Ios).
When an operational amplifier is connected as a simple voltage follower the input offset
current has no effect. But some circuits have two equal-value resisistors in series with the
input terminals and in this case, the input offset current produces unequal voltage drops
across these resistors as shown in figure 1.9 below.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
The difference in the resistor voltage drops behaves as a differential input voltage which
produces an output offset voltage.
The typical input offset current for the 741 operational amplifier is 20 nA.
Figure 1.9: Input offset current
Input Bias Current:
Definition: the average of the two input currents, flowing into the op-amp terminals is
called as input bias current.
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For 741 op-amp, maximum value of input bias current is 500 nA.
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Figure1.10: Input Bias Current
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Offset Nulling:
There are two method for nulling input offset voltage and current which is discussed
below
Method1:
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Figure 1.11: Potentiometer method
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A variable resistance introduces between the emitters of Q1 and Q2 can minimize

the effect of offset voltage and currents.
The variable resistance RP is a low resistance Potentiometer which changes the
voltage drop from base of each transistor to the common point of Potentiometer.
Thus, input current also gets altered.
Because an offset voltage is produces by the input offset current, this adjustment
can null the effects of both input offset current and input offset voltage.
Method2:
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Figure 1.12: manufacturer's recommended method of offset nulling for the741
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
A 10 k potentiometer is connected to offset nulling terminals 1 and 5 moving

contact is connected to the negative supply line as shown in figure 1.12.
The potentiometer is adjusted to null the output offset zero. Thus nulling both
input offset current and input offset voltage.
Resistor Tolerance Effect:
The discussions of offset voltages and currents assumed that either there were no resistors
at the op-amp input terminals, or else that exactly equal resistors were connected to the
input terminal.
Most operational amplifier circuits have resistors at their input terminals and sometimes
those resistors may not have equal resistance values.
Input offset voltage due to the input offset current is,
Output voltage is given as
Resistor tolerance is,
Input offset voltage is given as,
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Input Impedance:
For all linear applications, some form of negative feed-back is provided by externally
connected components.
From negative feedback theory the impedance at the op-amp input terminal becomes
Here,
Zi = the op-amp input impedance without negative feedback
M = op-amp open-loop gain
= feedback factor = 1 for a voltage follower
Note the above equation applies to a non-inverting amplifier, it does not apply to an
inverting amplifier.
The impedance of signal sources connected at the input of an operational amplifier circuit
as shown in figure 1.13 below should be very much smaller than the amplifier input
impedance to avoid a loss of signal across RS.
Figure 1.13: Op-Amp Input & output Impedance
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Output Impedance:
Here,
Zo = op-amp output impedance without negative feedback
= feedback factor
Load impedances connected at the output of an operational amplifier should be larger

than the circuit output impedance as shown in Figure 1.13. This is to avoid any
significant loss of output as a voltage drop across Zout.
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The typical output resistance specified for the 741 op-amp is 75. Any stray capacitance
in parallel with this is certain to have a much larger reactance than 75 .
Like the input impedance, the output impedance of the op-amp is affected by negative
feedback.
Slew Rate:
The slew rate (S) of an operational amplifier is the maximum rate at which the output
voltage can change.
When the slew rate is too slow for the input, it results in distortion.
Consider the figure 1.14 shown below where a sine wave is applied as input to a voltage
follower produces a triangular waveform as output. The triangular wave results because
the op-amp output simply cannot move fast enough to follow the sine wave input.
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Expression for slew rate is given as below,
Figure 1.14: Slew rate
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Here,
t = minimum time required for satisfactory operation of op-amp
V0 = output voltage change
S = slew rate in V/s
The typical slew rate of the 741 op-amp is specified as 0.5 V per microsecond. This
means that 1s is required for the output to change by 0.5 V.
Frequency Limitations:
Figure 1.15 below shows the graph of the open-loop gain (M) plotted versus frequency
for a 741 operational amplifier.
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Figure 1.15: Graph of Signal frequency v/s open-loop gain
It can be seen that M is 100 dB when the signal frequency is 1 Hz. At 10 Hz the gain has
fallen below 100 dB, and M continues to fall as the signal frequency increases.
Note that frequency is plotted to a logarithmic base that M falls linearly as f increases
logarithmically.
M falls by 20 dB when f increases from 100 Hz to 1 kHz. The ten times increases in
frequency is termed a decade. So, the rate of fall of the gain is said to be 20 dB per
decade.
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From figure 1.12 we see that M falls to zero at approximately 800 kHz. Where an internal
gain equal to or greater that 80 dB is required for a particular application, it is available
with a 741 only for signal frequencies up to approximately 100 Hz.
An internal gain greater than 20 dB is possible for signal frequencies up approximately
90 kHz. Other operational amplifiers maintain substantial internal off frequencies than
the 741.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Bias Current Paths:

Operational amplifiers must be correctly biased if they are to function properly.
The inputs of most operational amplifiers are the base terminals of the transistors in a
differential amplifier. Base currents must flow into these terminals for the transistors to
be operational.
Hence, the input terminals must be directly connected to suitable DC bias voltage
sources.
For many applications, the most appropriate DC bias voltage level for the op amp input
terminals is approximately halfway between the positive and negative supply voltages.
One of the two input terminals is usually connected in some way to the op-amp output to
facilitate negative feedback.
The other input might be biased directly to ground via a signal source as shown in figure
1.16 below.
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Figure 1.16: Directly Connected Voltage Follower
Base current IB1 flows into the op-amp via the signal source while IB2 flows from the
output terminal as illustrated above.
Figure 1.17 shows a situation in which resistor R1 is included in series with the inverting
terminal to match signal source resistance R s in series with the non-inverting terminal.
The op-amp input currents produce voltage drops IB1Rs and IB2R1 across the resistors.
Rs and R1 should be selected as equal resistors so that the resistor voltage drops are
approximately equal. Any difference in these voltage drops will have the same effect as
an input offset voltage.
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Figure 1.17: R1 included to march Rs
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Maximum Bias Resistor Values:
If very small resistance values are selected for Rs and R1 in the circuit in figure 1.17 the
voltage drops across them will be small.
On the other hand, if Rs and R1 are very large, the voltage drops IB1RS and IB2R1, might
be several volts.
For good bias stability, the maximum voltage drop across these resistors should be much
smaller than the typical forward-biased VBE level for the op-amp input transistors.
Usually, the resistor voltage drop is made at least ten times smaller than V BE.
For 741 op-amp IB(max) = 500 nA.
Hence
This is a maximum value for the bias resistors for a 741 operational amplifier.
For other op-amps are involved, R(max) should be calculated using the specified I B(max) for
that particular op-amp. the general expression is given as,
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Potential Divider Bias:
Figure 1.18: Potential Divider Using Op-Amp
Figure 1.18 shows a potential divider (R1 and R2) circuitry is employed to derive a
terminal bias voltage from the supply voltages.
Potential divider bias is commonly used with op-amps and in transistor circuitry.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
The potential divider current (I2) should be much larger than the op-amp maximum input
bias current. This is to ensure that I B, and any bias current variation, has a negligible
effect upon the bias voltage level.
Usually I2 is made 100 or more times IB. Thus,
For 741 op-amp typical value of IB(max) is 500 nA thus,
The above is the minimum value of IB when using a 741 and it would be quite
satisfactory to use a current of 1 mA.
The input voltage range is minimum of 12 V for a 741 op amp with a 15 V supply.
The resistance "seen" when "looking out" of the non-inverting input terminal in figure
1.18 is R1R2. To equalize the voltage drops at the input terminals,
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Single Polarity Supply Voltage:
A single polarity supply voltage can be employed with an operational amplifier.

A 741 could use a +30 V supply as illustrated in figure 1.19 below.
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Figure 1.19: op-amp with single polarity
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Op-AmpFundamentals
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Asst Professor
In this case the input terminal bias voltage should be approximately half the supply
voltage (+ 15 V for a 30 V supply).
Alternatively, VB might be within the input voltage range ( 12 V for a 741 using a 15
V supply) of the half-way point between + Vcc and ground. Since the circuit shown in
figure 1.19 is a voltage follower, the dc output voltage will be equal to the bias voltage
level.
Biasing BIFET Op-Amps:
BIFET Op-amps are operational amplifiers with FET input stages is shown in figure 1.20
below.
H
ES
Figure 1.20: Op-amp with FET input Stage
BIFET draw very low levels of input bias current like, 50 pA is not unusual.
In this case, the usual design approach of selecting resistor currents one hundred times
IB(max) would result in very high resistor values which are undesirable for several reasons.
1. When the bias resistors at the gate terminal of a FET are extremely large, a charge
can accumulate at the gate and this might take a relatively long time to discharge.
2. Thus, the gate voltage would not be a stable quantity, and the op-amp bias
conditions would be uncertain.
3. Another reason for avoiding high resistance values with any op-amp circuit is that
stray capacitance becomes more effective as resistance values increase, possibly
resulting in unwanted circuit oscillations.
For satisfactory bias conditions when using BIFET op-amps, the resistance "seen" when
"looking out" of either input terminal should normally not exceed 1 M.
A reasonable rule-of-thumb is to first select the largest resistor in a bias network as 1

M, then calculate the other resistors accordingly.
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There are some op-amps which can operate with even larger resistors, notably the LM108
(not a BIFET op-amp) which can use signal source resistors as high as 10 M.
Department of ECE
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Op-AmpFundamentals
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Asst Professor
Concept of Virtual Ground:

An Op-Amp has a very high gain typically order of 105.
If power supply voltage Vcc = 15V, then maximum input voltage which can be applied is
Here Ad = Differential Gain.
Let say supply voltage be 15 V and gain be 105 then,
i.e. Op-Amp can work as a linear amplifier (from +Vi to Vi) if input voltage is less than
15 V. Above that Op-Amp saturates as shown in figure 1.21 below
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Figure 1.21: Op-amp input & Output relation
Consider the Op-amp circuit as shown below,
AG
Department of ECE
Figure 1.22: Op-amp Circuit
Page No - 26
Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Say if V1 is grounded then V2 cannot be more than 150 V as supply voltage is +15 V,
which is very very small and close to ground.
Therefore V2 can also be considered at ground if V1 is at ground. Physically V2 is not

connected to the ground yet we considered V2 at ground that is called virtual ground.
Direct-Coupled Voltage Followers:

A voltage follower also called a unity-gain amplifier, a buffer amplifier, and an isolation
amplifier is a op-amp circuit which has a voltage gain of 1.
This means that the op amp does not provide any amplification to the signal. The reason
it is called a voltage follower is because the output voltage directly follows the input
voltage, meaning the output voltage is the same as the input voltage.
This is the reason voltage followers are used. They draw very little current, not disturbing
the original circuit, and give the same voltage signal as output. They act as isolation
buffers, isolating a circuit so that the power of the circuit is disturbed very little.
Voltage followers are important to buffer or isolate a low impedance load from a voltage
source. This means that rather than connect a relatively low value of load resistance
across the terminals of the power source, the op amp can be used to eliminate any loading
that might occur. Thus, the power source will not be loaded down. The circuit acts as an
ideal voltage source with nearly zero internal impedance, since it barely uses any current,
yet outputs the full voltage.
Design:
An operational amplifier may be function as a voltage follower with the use of any
external components connected to it as in figure 1.23 below.
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Department of ECE
Figure 1.23: Op-amp voltage follower
Page No - 27
Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
In the above circuit the resistor R1 is commonly used between output and inverting
terminal to match the source resistance Rs.
Say the maximum values of base currents I B1 and IB2 may be IB1(max) and IB2(max) for
the case of perfect matching then,
------ (1)
The above will be the maximum voltage drop across each resistors.
Since IB1(max) and IB2(max) are same for op-amp hence Rs and R1 will be practically
same.
Hence, input offset voltage is given by
H
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------- (2)
Performance:
The input impedance of the voltage follower is given as below
D
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The output impedances of the voltage follower is given as below
AG
The voltage follower has very high input impedance and very low output impedance
hence it used to convert a very high input impedance source to low output impedance
acting as buffer.
Consider a load resistance connected to the source as shown in figure 1.24(a) below
Figure 1.24(a): Load connected directly to source
The load voltage is given as below,
Department of ECE
Page No - 28
Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Figure 1.24(a): Load connected using Voltage Follower
Consider a load resistance connected to the source as shown in figure 1.24(b) below
H
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Now we know that input impedance (Zin) of op-amp is very large hence input voltage
to op-amp is given as below,
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Also we know that output impedances (Z out) of the voltage follower is very low,
output voltage across the load is given as,
AG
And output voltage Vo is given as,
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Due to large open loop gain M, Vo = Vi and due to very low output impedance VL = Vo.
Hence load voltage is same as the output voltage which is equal to input voltage.
Voltage Follower Using a Potential Divider Bias:

Figure 1.25 below illustrates the use of a voltage follower with a potential divider
produce a low impedance dc voltage source.
H
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Figure 1.25: Potential Divider Bias for Op-amp
In reality a potential divider is used to obtain the voltage required from supply voltage as
shown in figure 1.26 below
Figure 1.26: potential divider
AG
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In the above circuit various electrical parameters is given below,
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
-------- (1)
------- (2)
------- (3)
-------- (4)
Say in above case when RL varies by a small amount IL change due to the change in V L
then
The above draw back can be eliminated by using voltage follower to generate constant
voltage across the load as shown below
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AG
Figure 1.27: Voltage follower with potential divider
Due to very high input impedance and very low output impedance, if R L changes, the
load voltage VL is same as V2 which does not dependant on RL.
Due to above reasons load voltage remains constant irrespective of change in RL.
Parameters with Op-amp is as below
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Asst Professor
Comparison of Emitter Follower and Voltage Follower:
Also called as buffer amplifiers

Higher Input Impedance but
less than Voltage Follower
output impedance greater than
voltage follower
AC signal voltage loss is more
than voltage follower
Also called as buffer amplifiers

Higher
Input
Impedance
Compared to Emitter Follower
Lower output impedance much
lower than emitter follower
AC signal voltage loss is very
less compared to emitter
follower
DC loss is the voltage drop of DC loss is Vi/M which is very
the transistor
small
AG
Voltage Follower
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Emitter Follower
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Sl No
1
2
3
When RL Changes by say 10% also, VL = V2
Op-AmpFundamentals
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Direct Coupled Non-inverting Amplifier:

Figure 1.28 below shows the circuit for direct coupled non-inverting amplifier
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Figure 1.28: Direct Coupled Noninverting Amplifier Configurations
The closed loop voltage gain of the non-inverting amplifier is
Input and output voltages are given as,
The closed loop voltage gain is given as,
AG
Department of ECE
Page No - 33
Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Design Steps:
1. From Potential divider logic the resistor values R2 and R3 are determined using Vi,
Vo, I2. By convention we select I2 much larger than IB(max) by about 100 times.
2. From the concept of virtual ground, Vi = VA = VB thus
H
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3. As Vo appears across (R2 + R3) hence,
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4. To equalize the voltage drop due to bias current IB at each input terminal,
5. If R1 is not very large compared to RS then,
AG
6. In case of BIFET op-amp, R2 is selected as 1M, a large value.
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Op-AmpFundamentals
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Asst Professor
Input and Out Impedance of Direct Coupled Non-Inverting Amplifier:

Consider the circuit as shown below
H
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Figure 1.29: Impedance circuit of direct coupled non-inverting amplifier
The input impedance of an op-amp circuit is given as,
Here,
Zi = the op-amp input impedance without negative feedback
= feedback factor
For non-inverting amplifier the feedback factor is given as
Here Av = closed loop voltage gain of the non-inverting amplifier
Substituting (2) in (1) we get
AG
------ (3)
The input impedance given by equation (3) is the impedance "seen" when "looking into"
the non-inverting input terminal; it does not include R1. Thus, the impedance seen from
the signal source is
------ (2)
D
AT
------ (1)
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Output impedance of an op-amp circuit as
Here,
As = 1/Av above equation is written as,
Direct Coupled Inverting Amplifier:
The inverting amplifier circuit is as shown in the figure 1.30 below
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= feedback factor
------- (4)
AG
Figure 1.30: The Op-amp inverting amplifier circuit using BJT
Input and output voltages are given as,
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
The closed loop voltage gain is given as,
Design Steps:
From Potential divider logic the resistor values R2 and R3 are determined using Vi,
Vo, I1. By convention we select I1 much larger than IB(max) by about 100 times.
H
ES
------ (1)
D
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To equalize the voltage drop due to bias current I B at each input terminal,
If R1 is not very large compared to RS then,
From the concept of virtual ground,
AG
As Vo appears across (R2) hence,
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Direct Coupled Inverting Amplifier Using LF353:
Figure 1.30: The Op-amp inverting amplifier circuit using BJT
Resistance R1 is given as
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In case of BIFET op-amp, R2 is selected as 1M, a large value.

The closed loop voltage gain of the circuit is given as,
To equalize the voltage drop due to bias current I B at each input terminal,
AG
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Input and Out Impedance of Direct Coupled Inverting Amplifier:

Consider the circuit as shown below
Figure 1.29: Impedance circuit of direct coupled inverting amplifier(add)
From the above circuit we see that the op-amp inverting terminal will be at ground level.
Hence the junctions of R1 and R2 will always be close to ground potential.
Thus by looking into the inverting amplifier from the signal source, the resistance R 1 is
seen with its other end at ground level thus,
H
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------- (1)
Output impedance of an op-amp circuit as
D
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------ (2)
Here,
= feedback factor
For non-inverting amplifier the feedback factor is given as
Substituting (2) in (1) we get
AG
------- (4)
When R2 >> R1 then
------ (3)
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------ (5)
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Inverting Summing Circuits:

Figure 1.30 shows the Inverting Summing Circuit
Applying KCL to node A,
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Figure 1.30: Inverting Summing Circuit
From the concept of virtual ground at node A, Vi = 0 and i = 0, hence,
Say if R1 = R2 then,
For summing amplifiers voltage gain Av is given as
AG
------ (3)
Put (3) in (2)
------- (2)
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------ (1)
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-------- (4)
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Case1: R1 = R2 = R3, then
In such cases output is the direct sum of the input voltages inverted.
Case2: R3 > R1 and R2 then,
The circuit output voltage is now the sum of the input voltages multiplies by R3/R1.
Case3: R3 < R1 and R2 then,
The circuit output voltage is now the sum of the input voltages multiplies by R 1/R3.
Now let us consider a 3 inputs to a summing circuit as shown in figure 1.31 below
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Department of ECE
Figure 1.31: Op-amp summing circuit with 3 input
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
The output voltage is given as,
Case1: R1 = R2 = R3, then
Case2: R1 = R2 = R3 and R4 = R1/3, output voltage is given as
Above equation shows that output voltage is a average of the inputs. Hence, summing
amplifier can be designed as averaging circuit.
Application: Audio Mixers.
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Difference Amplifier or Subtractor:
H
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The op-amp circuit which amplifies the difference between two of its input is known as
Difference Amplifier or Subtractor.
In open loop mode, the op-amp acts as difference amplifier but due to its large open-loop
gain the output will be saturated thus; practical circuits do use negative feedback.
Figure 1.32 shows the op-amp configured as a difference amplifier.
AG
Figure 1.32: op-amp configured as a difference amplifier
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We employ superposition theorem to solve the circuit

Case1: let V1 be operational and V2 be grounded. Output be represented as Vo1 as shown
in figure 1.33 below
RAGHUDATHESH G P
------ (1)
--------- (2)
Case2: let V2 be operational and V1 be grounded. Output be represented as Vo2 as shown

AG
The output voltage is given as
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Looking in to the above figure we see that it is a inverting amplifier configuration, hence
gain is given as
D
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Figure 1.33: op-amp configured as a difference amplifier with V1 Operational
Figure 1.34: op-amp configured as a difference amplifier with V2 Operational
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
Looking in to the above figure we see that it is a non-inverting amplifier configuration,

hence gain is given as
------ (3)
The output voltage is given as
The voltage VA is given by Ohms law as,
Substituting VA in Vo2 we get,
H
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------- (4)
Adding both the outputs we get,
AG
------- (5)
Now Say we select the resistances R1 = R3 and R2 = R4 in such case above equation is
reduced to,
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Op-AmpFundamentals
-------- (6)
Now say if R2 = R1 in this case the output is the difference value of 2 input voltages.
Two Types:
Differential Input Resistance (Ri(diff)):
It is the resistance offered to an input signal source which is directly connected across
the input terminal and is given as,
Figure 1.35: Differential Input Resistance
Common Mode Input Resistance (Ri(cm)):

It is the resistance offered to an input signal source which is connected between
ground and both the input terminals and is given as,
AG
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Input Resistances:
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Asst Professor
Op-AmpFundamentals
Figure 1.35: Common Mode Input Resistance
H
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Effect of Common Mode Voltage:

Say Vc, is the common voltage which gets applied to both the input terminals.
Hence input 1 becomes V1 + Vc, while input 2 becomes V2 + Vc. But the output is
amplified difference of (V1 + Vc) and (V2 + Vc).
Thus Vc, gets cancelled and has no effect on the output. But this is true if the ratio R4/R3
is perfectly matched with R2/R1.
If these ratios are unequal then V c, at one input gets amplified more than that at the other
input. Hence Vc will not get cancelled and output will get disturbed.
Practically it is impossible to match these ratios perfectly and some common mode
voltage is bound to be present.
To nullify the effect of common mode voltage, the resistor R 4 is selected as the
combination of fixed and variable resistor.
Hence adjusting variable part of R4, the ratio R4/R3 is made almost equal to R2/R1. Thus
common mode voltage is nulled. This is shown in the figure 1.36.
AG
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Department of ECE
Figure 1.36: Practical Adjustments for difference amplifier
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Op-AmpFundamentals
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Asst Professor
Output Level Shifting:

In the figure 1.36 R4 is connected to a DC bias voltage VB instead of being grounded in
the usual manner.
Now let both the input voltages V1 and V2 be grounded and modified circuit is as shown
H
ES
------- (3)
Since the circuit is behaving as non-inverting amplifier hence the output voltage is given
as,
------ (2)
Substituting (2) in (1) we get,
AG
------- (1)
But Current I in the circuit given by applying KVL to the circuit,
Voltage at point A is given as,
D
AT
Figure 1.37: Effect of VB
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Asst Professor
Using resister relationship i.e, R2/R1 = R4/R3 to nullify the common mode voltage, we get
RAGHUDATHESH G P
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Circuit Design:
1. Obtain the values of R1 and R2 as per the design of an inverting amplifier.
2. Select R3 and R4 such that R2/R1 = R4/R3.
3. Generally R1 = R3 and R2 = R4 is selected considering the requirement of the input
resistor.
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Op-AmpFundamentals
RAGHUDATHESH G P
Asst Professor
VTU Questions:
H
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1. Define the following terms as applied to op-amp and mention their typical values for
IC741: i. CMRR; ii. Slew Rate; iii. PSRR; iv. Input Offset Voltage. v. Output Offset
Voltage. December 2015 (08 Marks), June 2014 (08 Marks), June 2013 (06 Marks)
2. Sketch an op-amp direct coupled difference amplifier circuits. Explain the operation of
the circuits and derive an equation for the output voltage. December 2015 (07 Marks),
December 2013 (05 Marks)
3. Design a direct coupled non-inverting amplifier to amplify 100mV signal using IC741 to
a level of 4V. December 2015 (05 Marks)
4. Explain direct coupled two I/P-inverting summing amplifiers with neat diagram and
necessary design steps. June 2014 (06 Marks)
a level of 5V. June 2014 (06 Marks)
6. Explain Common Mode Voltage, Common Mode Voltage Gain and Common Mode
Rejection Ratio for op-amps. Show that
December 2013 (10
Marks)
a level of 3V [consider
]. December 2013 (05 Marks)
AG
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8. With a neat circuit diagram, explain the basic op-amp circuit. June 2013 (06 Marks),
9. Draw a neat circuit diagram for a direct coupled non-inverting op-amp circuit and explain
the design steps. June 2013 (04 Marks)
10. Two signals each ranging from 0.1 V to 1 V are to be summed. Using 741 op-amp design
a suitable inverting summing circuits. June 2013 (04 Marks)
11. Define Slew rate and unity gain bandwidth. What is the effect of slew rate on the output
voltage of op-amp? December 2012 (06 Marks)
12. Design an inverting amplifier using IC741 op-amp. The voltage gain is to be 50 and the
output voltage amplitude is to be 2.5 V. December 2012 (06 Marks)
13. Derive an expression for output voltage of non-inverting summing circuit using an opamp, consider two inputs. June 2014 (07 Marks)
14. The non-inverting amplifier uses A741 op-amp with R1=R2=2.2k. Determine
maximum possible output offset voltages due to
a. Input offset voltage of 5 mV.
b. Input bias current of IB(max) = 500A.
c. Input offset current of Ii(os) = 200 A.
d. Resistance tolerance of 10%
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Linear Integrated Circuits Unit1 Raghudathesh VTU

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Op-AmpFundamentals

LINEAR INTEGRATED CIRCUITS (VTU) - 10EC46

The starting point of all achievement is desire.

A moments insight is sometimes worth a lifes experience.

The center of every mans existence is a dream.

Definition1: An Integrated Circuit (IC) is a miniature, low cost electronic circuit

Definition2: An Integrated Circuit (IC), sometimes called a chip or microchip, is a

Advantages of ICs over discrete circuits:

The basic circuit of an operational amplifier consists of a differential amplifier input

Circuit Symbol and Terminals:

Figure 1.1 Circuit and IC symbol for an operational amplifier (op-amp)

Characteristics of Ideal OPAMP:

Some typical operational amplifier packages are illustrated in Fig. 1.2.

Figure 1.2: Opamp Packages

Block Diagram Representation of Op-amp:

The block diagram of IC op-amp is shown in the Figure 1.3 below

Figure 1.3: Internal block schematic of an op-amp

Level Shifting Stage:

Figure 1.4: Op-amp Internal Architecture

Basic Operational Amplifier Circuit:

Transistors Q1 and Q2 constitute a differential amplifier, which produces a voltage change

Transistor Q3 operates as an emitter-follower to provide low output impedance.

Substituting IC2 in equation (1) we get,

Scenario2: A positive-going voltage is applied to the non-inverting input terminal and

A Basic Operational Amplifier Circuit Consists:

The output stage gives the op-amp low output impedance.

Input Voltage Range:

Output Voltage Range:

The op-amp is connected to function as either a non-inverting or inverting amplifier; the

Common Mode Rejection Ratio:

Common Rejection Ratio (CMRR) is defined as the ability of Op-Amp in rejecting

CMRR expressed in decibels as,

The output voltage is given by,

Vd is also the feedback voltage developed across R2 hence,

Power Supply Voltage Rejection:

Input Offset Voltage:

Definition2: Output offset voltage is a DC voltage present at the output terminal of

Consider a internal circuit of op-amp voltage follower circuit as shown below

Figure 1.8: internal circuit of op-amp voltage follower circuit

Scenario1: Say both transistors are matched VBE1 = VBE2 and Vi = 0

The above unwanted output voltage is known as an output offset voltage.

Typical input offset voltage for 741 op-amp is 1 mV.

Figure 1.9: Input offset current

Input Bias Current:

Figure1.10: Input Bias Current

Figure 1.11: Potentiometer method

A variable resistance introduces between the emitters of Q1 and Q2 can minimize

Figure 1.12: manufacturer's recommended method of offset nulling for the741

A 10 k potentiometer is connected to offset nulling terminals 1 and 5 moving

Resistor Tolerance Effect:

Output voltage is given as

Resistor tolerance is,

Input offset voltage is given as,

Figure 1.13: Op-Amp Input & output Impedance

Load impedances connected at the output of an operational amplifier should be larger

Expression for slew rate is given as below,

Figure 1.14: Slew rate

Figure 1.15: Graph of Signal frequency v/s open-loop gain

Bias Current Paths:

Figure 1.16: Directly Connected Voltage Follower

Figure 1.17: R1 included to march Rs

Maximum Bias Resistor Values:

For 741 op-amp IB(max) = 500 nA.

Potential Divider Bias: