28nm SerDes Timing Modes PDF

28nm SerDes Timing Modes
Friday, August 28, 2015
10:27 AM
NOTE: This document assumes familiarity with the "28nm Legacy SerDes Timing Model" document
("SerDes28_ETM_Legacy_130.pdf", called the "Legacy ETM document" in the rest of this document) and
the "16nm D6 SerDes Timing Model" document ("SerDesETM16_D6_11.pdf", called the "16nm ETM
document in the rest of this document). This document is a supplement to the Legacy ETM and 16nm
ETM documents, and where there is a conflict between the Legacy ETM and 16nm document and this
one, the Legacy ETM or 16nm ETM documents take precedence.
Why are there two ETM documents?

Starting with 16nm process generation, the timing model architecture was changed to simplify setting
timing modes and to better model the actual timing characteristics of the SerDes. Most of the changes
are related to how phase calibration is handled. To document how to use the timing model for 16nm
SerDes a new series of documents ("SerDesETM16_<serdes_architecture>_<revision>") were created.
In some cases, the LSB (Logical Sub-Block) of the 16nm SerDes was ported back into 28nm so that the
digital architecture developed for 16nm could be used by 28nm customers. An example of this is the
28nm 16-bit PCIe SerDes ("sd28C_pcie_16b_01"). Because these SerDes have a different timing
architecture than the older 28nm SerDes, The ETM document was renamed to include the string
"Legacy", but no ETM document was (or will be in the future) created for 28nm SerDes that with 16nmstyle LSBs.
So,
For legacy 28nm SerDes (such as the "sd28C_str_txhs_rxd6_05" Ethernet SerDes) the legacy ETM
document ("SerDes28_ETM_Legacy_130.pdf") should be used.
For 28nm SerDes with 16nm LSBs (such as the "sd28C_pcie_16b_01" PCIe SerDes) the 16nm ETM
document should be used.
Accordingly, this document is divided into two major sections, one each for Ethernet and PCIe SerDes.
Ethernet SerDes Timing Modes

As listed in Table 1 (reproduced in part below) in the Legacy ETM document, for the Ethernet SerDes
there are 24 mode values arranged in 8 groups that control which timing arcs are enabled and disabled
in a timing run. The person running STA should understand which modes are appropriate for that
particular timing run.
Similarly, for the PCIe SerDes there are 26 mode values arranged in 8 groups. (See the table below for
the mode values and groups.)
The 16-bit PCIe SerDes (e.g., sd28C_pcie_16b_01) have a different way of specifying
There are three types mode values:
Modes that are set automatically based on the values of input ports on the SerDes macro. These
are the three test timing models: TEST_MODES, JTAG_MODES, and PAR_SCAN_MODES. The user
should not set values for these modes by using set_mode but instead by constraining the ports
Misc Page 1
listed in the ETM document.
Modes that represent timing arcs that will be enabled during mission mode by firmware but that
must be set using set_mode during STA.
Modes that can be set using set_mode to simplify test mode timing.
Ethernet Timing Groups and Modes

The table below lists the timing groups and modes for the Ethernet SerDes.
Group
Mode
RX_CLOCK
RX_F10
RX_F20
RX_FUNCTIONAL_CLK_OFF
TX_CLOCK
TX_F10
TX_F20
TX_FUNCTIONAL_CLK_OFF
RX_FIFO_CLOCK
RX_FIFO_F10
RX_FIFO_F20
RX_FIFO_F40
RX_FUNCTIONAL_FIFO_CLK_OFF
TX_FIFO_CLOCK
TX_FIFO_F10
TX_FIFO_F20
TX_FIFO_F40
TX_FUNCTIONAL_FIFO_CLK_OFF
PHASE_CAL
PHASE_CAL_F10_CAPTURE
PHASE_CAL_F20_CAPTURE
PHASE_CAL_FALSE
TEST_MODES
SCAN_MODE
CAPTURE_MODE
FUNC_MODE
JTAG_MODES
JTAG_ON
JTAG_OFF
PAR_SCAN_MODES PAR_SCAN_ON
PAR_SCAN_OFF
Choosing Timing Modes

For mission mode STA, the user will need two pieces of information about how the SerDes is configured:
The bit width being used with i_tx_in and o_rx_out. This will be one of 10-, 20-, or 40-bit modes.
It is assumed for this discussion that both TX and RX are using the same bit width.
Whether or not phase calibration (AKA, phase beacon) is being used.
With that information in-hand, the timing modes can be properly set for all possible modes. See the
following table for the modes that must be set for STA analysis for all configuration. Remember, some
timing modes will be automatically set by the state of selected inputs to the SerDes.
Misc Page 2
Bit Width Phase Calibration
Test
Timing Modes
10
No
No
FUNC_MODE(TEST_MODES)
TX_F10(TX_CLOCK)
TX_FIFO_F10(TX_FIFO_CLOCK)
PHASE_CAL_FALSE(PHASE_CAL)
RX_F10(TX_CLOCK)
RX_FIFO_F10(TX_FIFO_CLOCK)
20
No
No
TX_F20(TX_CLOCK)
RX_F20(TX_CLOCK)
40
No
No
TX_F20(TX_CLOCK)
RX_F20(TX_CLOCK)
10
Yes
No
TX_F10(TX_CLOCK)
PHASE_CAL_F10_CAPTURE(PHASE_CAL)
RX_F10(TX_CLOCK)
20
Yes
No
TX_F20(TX_CLOCK)
RX_F20(TX_CLOCK)
40
Yes
No
TX_F20(TX_CLOCK)
RX_F20(TX_CLOCK)
--
--
Yes
TX_FUNCTIONAL_CLK_OFF(RX_CLOCK)
TX_FUNCTIONAL_FIFO_CLK_OFF(RX_FIFO_CLOCK)
RX_FUNCTIONAL_CLK_OFF(TX_CLOCK)
RX_FUNCTIONAL_FIFO_CLK_OFF(TX_FIFO_CLOCK)
PCIe Timing Modes

As listed in Table 1 (reproduced in part below) in the 16nm ETM document, for the PCIe SerDes there
are 26 mode values arranged in 8 groups that control which timing arcs are enabled and disabled in a
timing run. The person running STA should understand which modes are appropriate for that particular
timing run.
There are three types mode values:
Misc Page 3
are the three test timing models: TEST_MODES, JTAG_MODES, and PAR_SCAN_MODES. The user
listed in the ETM document.
Modes that represent timing arcs that will be enabled during mission mode by firmware but that
must be set using set_mode during STA.
Modes that can be set using set_mode to simplify test mode timing.
PCIe Timing Groups and Modes

The table below lists the timing groups and modes for the PCIe SerDes.
Group
Mode
RX_CLOCK
RX_F10
RX_F16
RX_F20
RX_FUNCTIONAL_CLK_OFF
TX_CLOCK
TX_F10
TX_F16
TX_F20
PB_TX_F10
PB_TX_F16
PB_TX_F20
TX_FUNCTIONAL_CLK_OFF
RX_FIFO_CLOCK
RX_FIFO_F10
RX_FIFO_F16
RX_FIFO_F20
RX_FUNCTIONAL_FIFO_CLK_OFF
TX_FIFO_CLOCK
TX_FIFO_F10
TX_FIFO_F16
TX_FIFO_F20
TX_FUNCTIONAL_FIFO_CLK_OFF
TEST_MODES
SCAN_MODE
CAPTURE_MODE
FUNC_MODE
JTAG_MODES
JTAG_ON
JTAG_OFF
PAR_SCAN_MODES PAR_SCAN_ON
PAR_SCAN_OFF
Choosing Timing Modes

For mission mode STA, the user will need two pieces of information about how the SerDes is configured:
The bit width being used with i_tx_in and o_rx_out. This will be one of 10-, 16-, or 20-bit modes.
It is assumed for this discussion that both TX and RX are using the same bit width.
Whether or not phase calibration (AKA, phase beacon) is being used.
Misc Page 4
With that information in-hand, the timing modes can be properly set for all possible modes. See the
following table for the modes that must be set for STA analysis for all configuration. Remember, some
timing modes will be automatically set by the state of selected inputs to the SerDes.
Bit Width Phase Calibration
Test
Timing Modes
10
No
No
TX_F10(TX_CLOCK)
RX_F10(TX_CLOCK)
16
No
No
TX_F16(TX_CLOCK)
RX_F16(TX_CLOCK)
20
No
No
TX_F20(TX_CLOCK)
RX_F20(TX_CLOCK)
10
Yes
No
PB_TX_F10(TX_CLOCK)
RX_F10(TX_CLOCK)
16
Yes
No
PB_TX_F16(TX_CLOCK)
RX_F16(TX_CLOCK)
20
Yes
No
PB_TX_F20(TX_CLOCK)
RX_F20(TX_CLOCK)
--
--
Yes
TX_FUNCTIONAL_CLK_OFF(RX_CLOCK)
TX_FUNCTIONAL_FIFO_CLK_OFF(RX_FIFO_CLOCK)
RX_FUNCTIONAL_CLK_OFF(TX_CLOCK)
RX_FUNCTIONAL_FIFO_CLK_OFF(TX_FIFO_CLOCK)
Misc Page 5

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28nm SerDes Timing Modes

Friday, August 28, 2015

Why are there two ETM documents?

Ethernet SerDes Timing Modes

Ethernet Timing Groups and Modes

Choosing Timing Modes

Bit Width Phase Calibration

PCIe Timing Modes

PCIe Timing Groups and Modes

Choosing Timing Modes

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