ELEC 6016 – DIGITAL SYSTEMS SYNTHESIS

ASSIGNMENT 1: SYSTEMC MODELING AND SIMULATION

Rishad Ahmed Shafik and Professor Bashir Al-Hashimi

Part A: N-bit Adder / Multiplier

1. Produce SystemC models of N-bit Adder and multiplier modules (N varies from 1
to 64 bits). The SystemC design should include basic modules, appropriate
testbenches for design validation and top-level modules. Use Modelsim or other tools
to simulate the models.

2. Using the N-bit adder and N-bit multiplier models, produce a model that carries
out (x + y)2, where x and y are 16-bit integer inputs. Use adders and multipliers
only. Assume precision such that overflow is accounted for. Use Modelsim or other
tools to simulate the model.

Part B. An end-to-end Data Communication System

Produce a SystemC model of a data communication system, such as the one shown
below:

Transmitter Channel Receiver

Figure: A data communication System

The data communication system has the following characteristics:

i) The data communication is packet based. Each packet contains 32-bit

data, packet id number and timing information. The communication stops
after 1024 packets are successfully transmitted.

ii) Transmitter transmits a packet on every clock cycle. The channel

introduces a delay in the region of 2-13 clock cycles for data packets from
transmitter to receiver, specified by the user.

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 iii) Receiver sends an acknowledgement on receipt of data packet. Note, no
acknowledgement is sent by the receiver if the received message has the
longest channel delay, which is 13 clock cycles.

iv) The system is clocked and synchronized.

A possible structural design (not necessarily the only one, showing

buffering for communication that may be needed):

CHANNEL ACKNOWLEDGEMENT

sc_fifo (max. capacity = 2)

sc_fifo (max. capacity = 3)

sc_fifo (max. capacity = 4)

sc_fifo (max. capacity = 5)

sc_fifo (max. capacity = 6)

Transmitter sc_fifo (max. capacity = 7) Receiver

sc_fifo (max. capacity = 8)

sc_fifo (max. capacity = 9)

sc_fifo (max. capacity = 10)

sc_fifo (max. capacity = 11)

sc_fifo (max. capacity = 12)

sc_fifo (max. capacity = 13)

PACKET

FIFO Buffers used for

introducing delay for
packets

You are expected to produce two types of channel models:

• Model 1: behavioural to account for channel delays of 2-13 clock cycles
• Model 2: structural; where channel delay is modeled by FIFO of size 2-13 as
shown above.
It is assumed that one delayed packet is transmitted at a given time from the
channel. Other transmissions variations are possible. For example, if two delayed
packets are to be transmitted at the same time from the channel, transmit the
packet with lower id first.

HINTS

Packets can be assumed as a structure of data and information using structuring

tools in c/c++. To make it SystemC port compatible, you would need to incorporate
streaming and tracing abilities.

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Here is a short example of a packet, showing packet data, id number and timing
information:

//packet.h
#include "systemc.h"

struct packet{
sc_uint<32> data;
sc_uint<12> id;
sc_time gen_time;
sc_time rec_time;

inline bool operator == (const packet& rhs) const {

bool status = false;
status = status && (rhs.data == data);
status = status && (rhs.id == id);
status = status && (rhs.gen_time == gen_time);
status = status && (rhs.rec_time == rec_time);
return status;
}
inline friend ostream& operator << (ostream& os, const packet&
temp) {
os << "Data : " << temp.data << ", ID : " << temp.id <<
"Gen time : " << temp.gen_time << "Rec time : " << temp.rec_time
<< endl;
return os;
}
inline friend void sc_trace(sc_trace_file* tf, const packet&
temp, const std::string& name){
sc_trace( tf, temp, name + ".data" );
sc_trace( tf, temp, name + ".id" );
sc_trace( tf, temp, name + ".gen_time" );
sc_trace( tf, temp, name + ".rec_time" );
}
};

and then within any module, you could use sc_out <packet>, sc_in<packet> or
sc_fifo<packet> introduce simple packet based communication. In order to time
stamp the generation and reception time, use the following:

In transmitter:
….
sc_out<packet> outport;
packet pkt;
….
pkt.gen_time = sc_time_stamp();
….
outport.write(pkt);

In receiver:
….
packet pkt;
….
pkt.rec_time = sc_time_stamp();
….

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DELIVERABLES
You should submit a not-more-than 12-page report with codes, simulation results,
any block diagrams or waveforms that you may want to show and possibly a CDR
containing the codes. Commented and conventional coding styles are recommended.

MARKING
This module is assessed by 50% course work and 50%, 2-hour examination. This
assignment constitutes 25% of the total mark for the module. For information on
marking scheme, submission and feedback, see the end of the assignment. PLEASE
MAKE SURE YOU SUBMIT THE COURSE WORK INFORMATION (PAGES 4 and
5) AS PART OF YOUR REPORT TO RECEIVE TIMELY FEEDBACK.

Simplifying the understanding of the code, together with the correct codes,
testbenches and results will merit up to 70%-80% marks. But, additional marks will
be awarded if some of the following features are observed in the code
(a) Well thought out solution to the problem including original thinking and
possibly an "optimal" solution in terms of code length and testbench
generation
(b) Realistic and practical solution. Clear statements made about the
assumptions employed when developing the code.
(c) Note there are NO single solutions to the problems outlined in the
assignment, innovate and justify.

USEFUL INFORMATION
1. Black, D.C., Donovan, J., SystemC : from the Ground Up, Kluwer Academics,
2004.
2. Course Webpage (http://users.ecs.soton.ac.uk/ras06r/notes/elec6016)

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 School of Electronics and Coursework (1 of 2)
Computer Science Instructions

Module: ELEC6016 Title: Digital Systems Synthesis Academic: Bashir M. Al-

Hashimi
Deadline: 20/03/2009 Feedback: Weighting: 25%

Instructions

See Assignment

Submission

The submission deadline is strictly 4:30pm, Friday 20th March 2009, after which
the submissions would be considered late and usual late submission rules would
apply. Submission should be made both in paper and electronic form through ECS
Coursework handin System (CBASS).

Relevant Learning Outcomes (LOs)

1. To gain working experience in modeling and simulation in SystemC.

2. To be able to understand and appreciate the level of abstraction SystemC can
work with (structural to hierarchical abstraction).
3. To be able to work with design issues related to resource and access sharing
in communication systems.

Marking Scheme

Criterion Description LOs Total

Model Description Different SystemC modules with their interconnections 1, 2, 3 13
Report Simulation results, comments and analyses 2 6
Validation/Testbenches The validation through testbenches 1 6

Late submissions will be penalised at 5% per working day.

No work can be accepted after feedback has been given.
Please note the University regulations regarding academic integrity and plagiarism.

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 School of Electronics and Coursework (1of 2)
Computer Science Feedback

Module: ELEC6016 Title: Digital Systems Synthesis Submitted:

Student Name: Tutor: Weighting: 25%

Good features of your work

Advice and Suggestions for Improvement

Marks Breakdown

N/A Inferior Margin Good Excelle Superb

Model Description / 13
Report / 6
Validation/Testbench / 6
Overall: Marked by: Days Late: Final mark: / 25

Note that marks are provisional until the June exam board. Please retain all assignments and associated
paperwork until then.

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