448

IEEE TRANSACTIONS

be ignored, switching speeds for GaAs and silicon will be

similar for comparably
designed structures
operated at
high-bias levels. (This latter conclusion ignores differences
in parasitic
contributions.)
At low-bias
levels, scaling
principles
indicate the silicon delay times will be longer
than those of gallium-arsenide
ties. Intermediate
fields
for gallium-arsenide.

result

H. L. Grubin, D. K. Ferry,
zron., vol. 23, p. 157, 1980.

in shorter

delay

times

Solid-State

MESFET

the

model

detailed

model

is

presented that

circuit

sfmufation

are evaluated

either

from

The model

circuit

(IC)

T
that

HE

PURPOSE

ably

simple

and

of this
for

for

of

and other effects.

paper

more
than

An integrated

is to present

model

for

use in circuit
available

accurate

examples

or from

INTRODUCTION

of presently

criteria

Several

data

of

is dfscossed.

analytical

is appropriate

A number

for use in

The parameters

is shown to be more complete

models, which negleet tramit-time

I.

circuit

MESFET

simulation

models

modeling

logic

a reason-

the GaAs
will

programs.
be reviewed

be presented,

will
simulation

will

be

de-

circuits
studied
programs
acteristics
tors,

ANO

TECHNIQUES,

VOL.

w-28.

NO. 5, MAY 1980

D. P. Kennedy and R. R. OBrien, ZBIU J. Res. Deuelop., vol. 14,

p. 95, 1970.
H. L. Grubin in Proc. Sixth Biennial Cornell Elect. Eng. Conf,
(Cornett University, Ithaca, NY), p. 399, 1977.
H. L. Grubin and T. M. McHugh, So/id-State Electron., vol. 21,
p. 69, 1978.
C. Jacaboni, C. Canali, G. Ottaviani, and A. Albergigj Quaran~
Solid-StateElectron., vol. 20, p. 77, 1977.
B. W. Knight and G. A. Peterson, Phys. Reo., vol. 155, p. 393,

1967.
P. N. Butcher, Rq. Progr. Phys., vol. 30, p. 97, 1967.
W. Shoctdey, Proc. IRE, vol. 40, p. 1365, 1952.
G. C. Daeey and I. M. Ross, Bell Syst. Tech. J., vol. 34, p. 1149,
1955.
P. Greiling, ptivate communication.

of

SENIOR MEMBER, IEEE

mathematical

simulation

of the mathematical

depends

model.

The

totally

on the accuracy

model

must

reflect

the

exact physical properties of the circuit.

The difficulty
with MESFET
devices is that they are
extremely complex internally
and simple external models
cannot accurately describe their behavior under all conditions. Conversely,
a detailed two-dimensional
(internal)
model [1 ][4] of the device, although more accurate, is not
suitable for use with circuit simulation
programs.
One approach is to then develop an external characterization of the particular
MESFET
devices used in the
circuit
under study. That is, the model used will not
attempt

to be complete

enough

for

all ranges

of device

parameters.

scribed.
The

[6]

Elec-

R. CURTICE,

is suitable

programs.

experimental

earffer

design example

[5]

THEORY

Model for Use in the Design

GaAs Integrated
Circuits

tfsae.domsfn

device analysis.

[4]

[10]

WALTER

AbstractA

[3]

[7]
[8]
[9]

and K. R. Gleason,

A MESFET

conventional,

[2]

by the ratio of their nobili-

will

REFERENCES
[1]

ON MICROWAW3

design
(ICS)
using

and
is

aided

high-speed

are available
of

capacitors

development

complex

of

considerably
computers.
for

studying

if

large

dc and
of

However,

integrated

circuits

Many

combinations

and inductors.

GaAs

may

be

computer

transient

transistors,
the success

charresisof the

Manuscript received August 4, 1979; revised Febraary 20, 1980

The author is with the RCA Laboratories, Princeton, NJ 08540.

A number of MESFET
models can be found in the
literature.
Madjar
and Rosenbaum
[5] utilize the twodimensional
model of Yamaguchi
and Kodera [3] to produce analytical
relationships
for drain and gate currents
as a function
of drainsource
voltage, gatesource
voltage, and their derivatives.
This approach appears useful
for studying the interaction
between the device with its
parasitic
multiplier

0018-9480/80/0500-0448$00.75

and its external circuits, such as in frequency

operation.
However,
the technique would not
01980

IEEE

CURTICB: MESFETMODEL FOR G&

lCS

449

DRAIN

tors, and a clamping

diode between gate and source.
Resistors RI, R2, and R3 represent resistance of the contact regions. The only nonlinear elements are 1( V23, V13,T)
and C23( V23). The important

I(VZ3,V13,

y*

GATE ~

II.

.y3

PROPERTIESOF AN AccuRAm

SOURCE

model of a GSAS MESFET

analysis program.

for use with

a circuit

A. Accurate Approximation
Characteristics
The drain

be practical

in the simulation

teracting

and

and

Willing

field

domain.

many

bias

has not

Values

[7].

applied

He

assumption
gate

the

The
circuits

current

been

the

occurs

domain

average

electric

sustaining

field

saturation

drift

MESFET

equivalent

velocity,

K is the

described

here; however,

circuit

model

formulated
due

field

low

under

side
the

gate
is the

mobility).

The

to the circuit

transit

of

to be

time effects

un-

der the gate have been omitted.

The JFET
circuit

model

simulation

deficiencies
be shown,

in SPICE

2 [8] is widely

applied

for

available

for

this model has several

GaAs

MESFETS.

As will

known

voltage

either

of test devices

model

to approximate

this

are required

from

or from

de-

must use

relationship.

and must

be de-

termined by curve fitting techniques. Analytical

analysis
of the symmetrical
JFET model (see Sze [13]) results in a
(gate) voltage-controlled
drain current source (in the current saturation region) of the form
I ~~=~p 1+

[
where ~ is the pinch
more commonly

vG~ + VB1
~
P

off current

(1)

as defined

called saturation

current,

by Sze and

Vp is the pinch

off voltage which is qNOa2/(2c) for uniform doping, V~I is

the built in voltage at the gate (a negative voltage), V& is
the gatesource
voltage, a is the active layer thickness,
and NO is the donor value. N is found to vary between 2.0
and 2.25, depending
upon
the charge
distribution
quite good for real devices.
A second form of control

assumption

characteristic

is

assumed

by

Fair [14] and others is

this model is quite in error with regard to drain

current-voltage
Furthermore,
are omitted.

Control

to drain-source

is usually

assumed. It will be seen that the square-law

studies. However,

when

MODEL

Current

The MESFET

parameters

the

to the for-

as: u$/p(u$

field

is similar

expressions

several

by

and

relationship

measurements

FETs.

at the drain

given

electron

essentially
The

equations

saturation
Gunn

the

Often

to the Drain

voltage

device calculations.

analytical

nonlinear

with
linear.

has

Shocldeys

ampli-

measurements

multiple

has

used

and

with

model

the domain

linear

elements

analytical
that

when

current

gatesource

tailed

a nonlinear-

representing

S-parameter

are considered

for

of a stationary

equals

for

FET

with

elements

from

values

been

mation
the

and

muhiple-in-

simtiated

domain

includes

conditions.

simplified

Shur

that

are determined

bias-independent
A

[6] have

in the time

model

elements
at

with

experimental

oscillators

circuit-type
high

of circuits

devices.

Rauscher
fiers

MESFET

The properties that an MESFET

model must contain
for accurate transient simulation
will now be reviewed.

R3

Fig. 1. Circuit

of

: c,~

61

c23(v23)
4

aspects of the evaluation

these elements will now be described.

T)

,D.=,,l+lv..;v,,, ].

relationships
below current
saturation.
electron transit-time
effects under the gate

(2)

The most complete analytical

model is presented by
Van Tuyl and Liechti [9]. It is similar to the model to be

This equation is also used only in the region of current

saturation.
This form is obtained by assuming that the

described

depletion

here but is slightly

simulation
GHz

of a MESFET

showed

excellent

more complicated.

frequency
agreement

divider
with

Computer

operating

experimental

at 2

thickness

abrupt junction,

is the same as that

tion in the frequency domain.

Fig. 1 is the proposed large-signal
MESFET.
It consists primarily
of
current

source

1( Vzq, V, ~,~), three

interelectrode

capaci-

3)

The current is proportional

to the conduction
channel
width which is a
less expression
(3). By using the
definition
of pinchoff
voltage
derived for the case of uniform
Equations
however,
scribe

model for the GaAs

a voltage-controlled

in an

data

[10].
Pucel et al. [11] present a small signal model and show
how to derive the element values. Krumm et al. [12] use a
similar model but include electron transit-time
effects as a
time delay factor associated with the drain current source.
Good agreement is shown for S-parameter
data over a
broad frequency range (2 to 18 GHz). A MESFET
circuit
model for transient simulations
should not be very different than those models verified for small signal opera-

obtained

or

in

(1)

and

most

experimental
illustration.

(2). Fig.

2 is a graph

V.. Notice

appear

either

devices.

following

Vn,)/

(2) may

cases,

Vp, equation
doping.

Assume

one
This

to be quite
may
can

a MESFET

of ~1~

that it is nearly

(2) can be
different;

be used
be

seen

exactly

as a function

a linear function

to

de-

by

the

follows

of ( V~s +
between

450

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. MTr-28, NO. 5, MAY 1980

ordinate

values of 0.1 and 0.9. Fig. 2 shows a straight

approximation,

vG~ + VB1
lDs=O81~
This

1.0

line

which has the equation

straight

line

percent

(of

ordinate

values

lP)

equation

(1)

1+

1.25 Vp

approximation
error

in

between
with

N=

the

<

results

in

evaluation

0.1 and

0.9.

less

of

than

current

Equation

1P and

and

0,8 -

(4)
0.6

2
H21 w

for

(4) is just

VP multiplied

0.4 -

by

constants. These constants have no physical significance

since Ip and VP would be determined
from experimental
data for 1~~( V~~).
The must serious

difference

between

the straight

0.2 -

line

approximation
and (2) occurs near pinchoff,
where current is quite small. Usually, this introduces little error.
Equation (1) can be put in a standard form as

Equation

(5) is the form

analysis

program

plotting

fi

SPICE

used in

2. ~ and

from

the general
experimental

1, the raw

data

of RI

must

and

first

be processed

R3. This

can easily

circuit
by

70

values
60

to remove

50

the

40 -

be accomplished

30 -

once the values of RI and R3 are determined

either by
measurements
[15] or by calculations.
Since the voltage
drop across R3 is typically not negligible,
R3 usually has a major effect.
The

current

lower

voltages

larger

low

current
out

saturation
than

field

effect.

the hyperbolic

analytical

expression

addition,

one

drain-source
described

SPICE
the

SPICE

Van

Tuyl

for

adding

current

to fit

of current

below

current

2 are derived

and Hodges

effects.

a shunt

pinchoff

2 seems

to

and

in

be

to

able

saturation.

is not
across

The

devices
The

the FET

the

expressions

model

pv,3[2(v23+
[

used

in

well

in

is quite
used

in

of Shichman

V,q > O)

VT)

V13](1+AV13),

0< F713<V23+J7T

where
P23= v~ v~
V13= VI V3
and /3 and A are constants.

fit

1.5

2
VOLTAGE

25
(V)

Fig. 3. Best-fit approximation to experimental MESFET 1 V characteristics of [8] using the current source described by (7)(solid
lines) and by the JFET model of SPICE 2(dashed lines). Constants
are R1=R3=3 Q a=2.3 Vl, fl=13.1 m
VT=2.63 V, A=O.

The

1( V23, V13, ~)

quite

I
DRAIN-SOURCE

In

describe
adequately

o, Vzq+F-=<o
D(V23+VT)2(1 +AV,3),
0< V23+VT<V13

1( V23, V13) =

a good
~aAs.

expression

However

saturation.

[9] point

provides

.5

at

stronger

Liechti

saturation

experimental

from

of the much

in a much

resistor

is lost.

[15] and are (for

because

This

v13s=-1.5V

20 -

of

occurs

function

current

wants

conductance

region

poor

results

the presence

MESFETS

devices

This
tangent

also

by

because

GaAs

in silicon

mobility.

saturation

that

in

1,0

as a function of gate-source voltage for

FE~ devices obeying (2).

Value of ~~

of 1~~ are used, then a current source without

source
resistance is being described. To develop the model of Fig.
effects

1
0.8

gate to

VT are determined

versus V~~. If actual

1
06

VP

(5)

where V= is the threshold voltage measured

source V== VP+ V~I, and 8 = lP/ V;.

I
-0.4

Ves+%1

Fig, 2.

zD~ = /3( v~~ + VT)2

1
-0.2

use of

the

hyperbolic

improves the usefulness

The following
analytical
tion of the current

tangent

function

greatly

of the equation below saturation.

function is proposed for descrip-

source in GaAs

MESFETS:

1( V23, Vlq) = /3( V23+ V~)2. (1 + AVIS) tanh a V13

(7)

where a and A are constants. Notice that there are four

parameters to be evaluated in this expression.
Equation (7) was used to approximate
a set of measured
drain
current-voltage
relationships
presented
by Van
Tuyl
and Liechti
[9]. The experimental
data can be
matched

(6)

quite accurately.

Fig. 3 shows the characteristics

calculated
from (7). For comparison
purpose, the JFET
model of SPICE 2 (6) was also used and these computations are shown in Fig. 3 as dashed lines. Notice that
although
the gate control
is accurately
given by both
models in the region of current saturation,
the SPICE 2
calculations
are quite in error below current saturation
due to the lack of a parameter
to adjust the saturation
point. This is a major deficiency
of the SPICE 2 model
and leads to significant error in computations
of switching
characteristics.

CURTICE: MESFST MODEL FOR GAAS ICS

Equation
mental

451

(7) was also used to approximate

data

MESFET

presented

with

by Pucel

current

voltage

rent than the previous

characteristic

characteristics

calculated
this

a l-pm

quite

diffe-

case. Fig. 4 shows the drain-source

from

the model with

ters listed and the experimental

It is seen that

the experi-

et al. [11] for

simple

points

model

the parame-

are also indicated.

with

analytic

current

expression provides a good approximation

to the experimental devices current-voltage
characteristic.
B. Inclusion
During

of Transit-Time

transient

operation,

current.

This

conduction

current

to

width

a change

results

because
the

in

order

electron

under the gate must be changed

for

depletion

and this occurs by

charge transport at a maximum

velocity of 1 X 107 cm/s,
Thus, it takes of the order of 10 ps for a change in current
after the gate voltage is changed in a l-pm
MESFET.
(Notice that in the physical device,
change is part of the gate capacitance change
the model, we have separated the capacitance
effects.)
delay

The most important

produced

current.

between

Therefore,

gate length
this charge
whereas in
and current

result of this effect is a time

gatesource

the current

voltage

and

drain

source (7)

7),

curately

approximates

The current

We have found

where the derivative

dt
second

that

term

[1

ac-

(8)

as
dV23

(9)

av23 ~,,7

in expression

which may be thought

of l(t T) in time.

dI( V)

W(V)

dI( V) _

The

a technique

the effect but is simple to calculate.

is evaluated

(8) is a correction

term

of as the first term of the expansion

An error

is generated

when

the gate-

to-source

voltage

ever, for
addition,
changes.

small values of ~, the error is quite small. In

the gates capacitance
helps smooth
voltage

Fig.

has a nonzero

5 shows the drain

current

/.52253354
-SOURCE

VOLTAGE

(V)

_llo
a

E 100 -

z
;
a
;

80 -

60 -

Oc

1- 90 -

70 .

4%
o~

source is assumed to be of the form

l(v)7~

x4 v
x

Fig. 4. Best-fit approximation to experimental MESFET 1-V characteristics (X) of [10] using the current source described by (7)(solid
lines).

programs.

3V

ORAIN

V13]

where ~ is equal to the transit time under the gate.

The time delay effect is not easily added to most circuit
analysis

z
n

should be altered to be

1[ v23(t

x~

in gate voltage

change in drain-source

change,

/*

Y//x-----

Effects

does not cause an instantaneous

conduction

#/

second derivative.

calculated

for

How-

20

40

60

80

100120 140 160 180200

TIME ( PS )

Fig. 5. Calculated &ain current as a function of time for a l-~m gate

length MESFET (500-#m width) for a gatevoltage change from 0.5
to +0.5 V in la ps with delay time r as parameter and V~~ = 3.0 V.
Constants are same as in Fig. 3 and C23(0)= 0.5 pF, C12= 0.03 pF,
C13=0.1 pF, VB, =I.O V, i?2=10 $2.

erly time shifted by 10 ps. Fig. 5 shows that if r is not

included at all, then an important
source of delay in any
MESFET
circuit is omitted.
There will also be some transit-time
effect produced by
drain-source
voltage changes if there is a corresponding
change in drainsource
current. This effect should only be
significant for drainsource
voltages below current saturation and is not presently

accounted

for in this model.

The proposed
model includes
transit-time
effects in
driving transistors
and in source-follower
transistors but
not in transistors used for active loads since dV23/dt = O.
A MESFET
logic circuit would use all three types of
operation (see Van Tuyl and Liechti [9]).

a l-pm

MESFET
device with constant drain-source
voltage (3 V)
and a gate voltage change from 0.5 V to +0.5 V in 100
ps. The current delay seen for the case of ~ = O is produced
by the time involved in charging the gate capacitance. The
current delay seen for the case of ~= 10 ps is the total
delay through the device. Here it is seen that there is some
compromise
at the beginning and end of the output current waveform but the majority
of the waveform is prop-

C. Accurate

Evaluation

The charge depletion

of Gate Capacitance
region

beneath

the gate produces

gate capacitance between the gate and the source C23 and
between the gate and the drain C12. Each capacitor may
be thought of as a Schottky-barrier
diode with voltage
dependent capacitance.
For a negative gate-source
voltage and small drainsource
voltage, each diode is back
biased about the same amount and the capacitances C12

ISRBTRANSACTIONS ON MICROWAVS THSORY AND T3?CHNIQUSS,VOL. MIT-28, NO. 5, MAY 1980

452

and C2B are about

equal.

However,

as the drainsource

voltage is increased, more depletion

exists on the drain
side of the gate compared
to the source side and C12
becomes smaller than C23. When drainsource
voltage is
increased beyond the point of current saturation,
C12 is
much more heavily back-biased
than C23, and the charge
depletion

region

even

extends

well

out

from

the

gate

toward the drain. In the case CIZ<< C23. These observation

have. been made by study of the results of the two-dimensional simulation
Since

the

conductive

of MESFETS.

voltage
region

gatesource

drop

beneath

capacitance

between

the

source

the gate is always

C23 is usually

and

the

small,

the

significant

and

dominates
the input impedance
of the MESFET.
For
many MESFET
devices, this capacitance varies much like
a simple Schottky-barrier
diode capacitance. This capacitance
with

can be easily measured

or without

drainsource

drain-source
bias

should

as a function

V23 VOLTAGE

be used while
V2~ must

capacitance

is

be determined
for an
able to

such as
v13 vOLTAGE

C23(0)

C23(V23)
=

~ 1
where
tor

V~l is the built

must

proaches

not

be

in voltage.

allowed

to

V~l. The capacitance

23/

(10)

BI

However,
approach

will increase

enhancement-type
MESFETS.
The built in voltage V~l should be evaluated
tally from capacitance
data. It should
built-in
voltage of the Schottky-barrier

as

V23 ap-

as the deple-

experimen-

be equal
junction

to the
pulse

drop along the conducing

chan-

It is interesting that (10) which is derived from a twoterminal

model is a good approximation
for the threeterminal
MESFET.
The reason seems to be that the
gatesource
capacitance
is a very weak function
of
drainsource
voltage,
once current
saturation
has occurred (in MESFETS
not exhibiting
domain effects). As
the drain voltage is increased (above the voltage of current saturation)
the voltage in the conducting
channel
beneath

the gate changes little

voltage

drop

across

and there is an increased

the conducting

region

between

the

gate and drain.

A two-dimensional
transient
simulation
of a typical
l-pm
gate length
MESFET
was used to study
the
gatesource
and gatedrain
capacitance
due to internal
space charge. This analysis is quite similar to that presented by Yamaguchi
et al. [3] and Wada and Frey [4]
and is an extension
of the two-dimensional
modeling
technique

described

by Curtice

(v]

draingate
capacitance
as a function
of
Fig. 7. Electronic
drain-source voltage V13 calculated from the two-dimensional model
for a l-pm GaAs MESFET with donor density= 7 X 1016/cm3 and
epilayer thickness= 0.25 pm.

the denominazero

tion width reduces and as a forward bias condition occurs,

diffusion
capacitance will become important.
Approximation
of
this
condition
may
be
important
for

some part of the voltage

nel under the gate.

(V)

Electronic
gatesource
capacitance
as a function
of
gatesource voltage V& and drain-source
voltage V13 calculated from
the two-dimensional
model for a l-pm GaAs MESFET
with donor
density =7x 10c/cm3 and epilayer thickness= 0.25 ~m.

of gate bias

An analytical
expression of the form derived
ideal metalsemiconductor
junction
(17) is usually
such data;

APPLIED

Fig. 6.

bias. In the model of Fig. 1,

being measured. The voltage

from V~~ knowing R3.

approximate

~~,,,

[18]. Both C13 and C23 can

be studied

for

a given

device

structure

using

the

two

dimensional
simulation.
Some results are presented
in
Figs. 6 and 7 for a uniformly
doped device of a = 0.25 pm
diffuand donor density = 7 X 101b/cm3 Field-dependent
sion is included and V~l is taken to be 0.5 V.
The gatesource capacitance is evaluated from the total
change

flow

due to gate displacement

by a charge in gate-to-source
tance

is found

from

voltage.

current

gate displacement

change in drain-source
Fig.
6 shows that

voltage.
there
is

produced

Gatedrain

little

capaci-

produced
change

by
in

the

gatesource
capacitance
as a function
of internal
drainsource
voltage V13 above current saturation.
But
observe that the voltage drop across R3 may cause a
change
in gatesource
capacitance
as the external
drainsource
voltage is changed if there is significant
change in drain current (due to finite drain resistance).
Fig. 6 also shows good agreement with (10). However,
the value

of

VB1 that

must

be used is that

due to the

Schottky barrier junction plus a contribution

of about 0.5
V apparently
due to the voltage drop in the conduction
channel under the gate.
The calculated
values

of gatedrain

quite small but increasing

voltage, as shown in Fig.
section, the electrostatic
drain will usually be much

capacitance

were

with reduction of drainsource

7. As we shall see in the next
capacitance
between gate and
larger than these values. How-

ever, if calculations
or measurements
show that Clz is an
important
voltage-variable
capacitance,
then it must be

CURTICE: MSSF5T MODEL FOR GAAS ICS

included

in the model.

453

Willing

et al. [19] present

such a case. This effect is not related

which is fully
loading

when simulation

effect,

is performed

with

on the MESFET.

When
large

included

data for

to the Miller

;he active

enough,

interelectrode

capacitances

for

contact

the metal

each MESFET

thickness

in stationary

and donor

charge

value

accumulation

are

region

under

analysis

to ground)

gate, and

type and in their circuit.

is done by theoretical

layer

and capacitances

pads (source,

drain)

of

This computation

assuming

a ground

plane

the substrate.

A second
MESFET

method

circuits

is to build

scaled-up

and to measure

models

interelectrode

of the
capaci-

can exist beneath the drain edge of the gate and just
above the substrate interface.
The charge accumulation
region together with the charge depletion region adjacent
to it on the drain side form the stationary
high-field
domains reported by Yarnaguchi
et al., Wada and Frey,
and others. For the device studied here, only a small

et al. [10]
tance and capacitances
to ground. VanTuyl
define metal layouts 10 times actual size and on sapphire
substrates. A standard capacitance bridge is used. Excellent agreement
with theoretically
computed
values of

amount

has

the

of charge

case of near

domain

accumulation
zero

is present

gatesource

bias

and only
voltage.

is present over much of the operating

device, the interelectrode

well as the current

capacitances

control

for

If

the

range of the

may be affected

characteristics.

as

The gatedrain

capacitance
is increased
due to the smaller depletion
region and the gatesource
capacitance
may become a
strong function of the drainsource
voltage as well as the
gatesource voltage. Willing et al. [19] show such a case.
Such
domain
effects
can be important
in power
MESFETS
but are usually less important
in devices used
in integrated
thickness

circuit

product

D. Evaluation

are typically

of lower

very

determined

upon

primarily

DrainGate

by

the

simplified

theoretical

calculated

and plotted

electrostatic
From

problem,

They

Pucel

et

the drain-gate

al.

and

is a parameter

be-

of the interof the

[11]

have

source-gate

capacitances
as functions
of electrode separation.
length is a parameter
for drain gate capacitance
length

are

coupling

exact solutions

Gate
and

for sourcedrain

capacitance. The geometry is planar and no ground plane

is present. The authors state that the source-drain
capacitances are in good agreement
ments whereas the draingate
than

0.1 fF/pm

with experimental
measurecapacitances are somewhat

the experimental

gatedrain

and

and 0.15 fF/um,

E. Evaluation

values.

drainsource

of Circuit

Typical

capacitance

values
are

reduce

of parasitic

dramatic

example

is presented

their

This

technique

propagation

capacitances

delay

with improved

of

the

importance

by VanTuyl,

Liechti

of

circuit

et al. [10], [22].

They show that for a given circuit layout, the propagation

delay of a gate is equal to a constant plus a term inversely
proportional
to transistor width. These two terms become
equal at a (buffer) transistor width somewhat less than 10
pm. At this point, the parasitic
have doubled the inherent
delay of the gate.
DUAL-GATE
MESFET

since it is useful

capacitances

biases.

quite independent

nal space charge distribution.

higher

parasitic

The dwd-gate

and

and sourcegate
the operating

conductors,

source (or drain)

reduction

shapes was found.

to

designs.

III.

drain-gate
little

tween parallel

through
layout

them

donor-

Capacitances

Experimental

of simple

enabled

[20].

of Nonelectronic

SourceGate

depend

that

capacitance

for
thus

respectively.

Parasitic

As the MESFET
circuit is made smaller, the pad capacitances and other parasitic
become more important.
For
example, the capacitance-to-ground
of the drain contact
of a driver transistor can cause significant
loading. The
metal line providing
signal transmission
between logic
gates of an IC can also introduce
capacitive
loading
effects to ground and also capacitive coupling (or mutual
capacitance) effects to other signal transmission
lines.
There are several methods
of estimating
the fringe
capacitive effects of a particular
IC layout. Maupin et al.
[21] have computed the complete capacitance matrix (i.e.,

FET MODELING

structure

for performing

must also be modeled

mDing.

Asai

et al. [23]

showed that the dual-gate device behaves similar to two

FETs in series with each device somewhat inhibiting
the
operation of the other.
Fig. 8 shows the equivalent

circuit

tion

The two

of the dual-gate

designated

as FET

voltage-controlled

device.

assumed for simulaequivalent

1 and FET 2 in the figure,

current

source

FETs,

consists of a

and a voltage-variable

gate capacitance as described in Section II.

The saturation
current of the dual-gate

device

than that of a single-gate

the g~ of the

second gate is lower

FET.

In addition,

is less

than the g~ of the first gate because

the second device (FET 2) has the first device (FET 1) as

a source resistance.
To help offset these effects, the second gate section of
the device is usually made 25 to 50 percent wider than the
first

gate.

current

Fig.

9 shows

of the device

how

the

calculated

changes

with

the width

saturation
ratio.

This

calculation
assumes parameters
typical of a l-pm gate
length MESFET.
The width at FET 1 is 500 pm. In
addition to lower current, the dual-gate
knee voltage, i.e., current saturation

FET has a higher

occurs at a larger

drainsource
voltage.
To observe the transient response of the dual-gate device, a logic gate was simulated with two dual-gate FETs
in parallel as drivers. This is the equivalent of two 2-input
NAND gates feeding an OR gate. A width ratio of 1.5 was
used for both
unity.

FETs

and the fanout

Table I shows the calculated

was assumed

propagation

to be

delays for

switching
with either gate and for an equivalent
single
gate driver. The relationship
of the numbers
is quite
similar to the measurements by Van Tuyl et al. [10]. This

NO. 5, MAY

IEEE TRANsACIIONS ON MICROWAV3! THEORY AND I?JCHNIQOSS,VOL. hrrr-28,

454

1980

DRAIN

GATE

GATE

* OuT1-&

FET 2

FET

Fig. 10

MESFET logic gate without the level-shifting circuit. MESFET

T= is the same but one-half the width of MESFET 3.

b SOURCE

Fig. 8.

Equivalent circuit for the dual-gate MESFET.

Gs=OV

40
-05V

80 -

SINGLE

GATE

20

DEVICE

60 -

-Iov

0
0

10

Is

2.0

DRAIN-SOURCE
a
~ 40 -

25

30

(V )

Fig. 1L Drain-source
current-voltage
relationship
for a GaAs
MESFET calculated by the two-dimensional progrant assuming gate
length = 1.0 pm, donor value= 3 x 10]6/cm3, active layer thickness=
0.25 #m, built-in voltage =0.5 V.

1:
: 20 z
v

y~
1.8
WIDTH

RATlO

Fig. 9. Saturation current of the dual-gate MESFET as a function of

the width ratio at the gates. Constants are same as in Fig. 3 and V~~ = O.

.
.
TABLE

R-CAP

CALCULATED PROPAGATE DELAYS

FOR NAND/NOR

/
SPICE 2 +
/

z
:1
z

80
87
67

./
--
00

100

203

300

400
TIME

is thus good justification

for the model.

In addition,

The model

shown

SIMULATION EXAMPLE
in Fig. 1 may be used with

5W

600

1
700

!300

903

(P%)

it is

clear that there is a significant increase in the propagation

delay for dual-gate devices as compared
to single-gate
FETs.
IV.

Propagation Delay (w)

Using Upper Gate:
Using Lower Gate:
Using Single Gate FET:

____

%
52

GATE

>

12. Comparison
of simulation results using R-CAP, SPICE 2 and
the two-dimensional analysis for the device of Fig. 11 with VB = 3.5 V
and for SPICE 2: VT= 2.5 V, /?= 71 pA/V2, A= O, V~, =0.5 V,
C23(0)= 6 fF, CIZ(0) = 1 fF, for R-CAP: a= 1.5/V, p= 65 pA/V2,
VT=2.5 V, V~l = 0.5 V, Cn(0) = 6 fF, C12= 0.3 fF, 7 = 10 ps. For Both:
R1=RZ=R3= C13=0, CL=6 fF, driver width= 10 Y% load width=5
pm.

Fig.

a circuit

simulation
program to study complex integrated
circuits,
The circuit simulation program used here is R-CAP(24).
It
is similar
to SPICE 2 in many respects but has the
advantage that a user-defined
device model can be included
without
difficulty.
The model
for the GaAs
MESFET
was added to R-CAP as a subroutine.
The first circuit example is a MESFET
amplifier
with

first calculated from the two-dimensional

program assuming l-pm gate length, a donor value of 3 x 1016/cm3, an
active layer thickness
0.5 V. The calculated

of 0.25 pm, and a built-in voltage of

drainsource
current-voltage
char-

nonlinear
load and is shown in Fig. 10. This circuit is a
logic gate without the level-shifting
stage. Assuming certain device parameters,
the circuit was simulated
using
R-CAP, SPICE 2 and also by the two-dimensional
model-

acteristics are shown in Fig. 11. The parameters necessary

for SPICE 2 and R-CAP were than evaluated. Fig, 12
shows the results of circuit
simulation
by the three
methods for a specific input (gate) voltage waveform. The
two-dimensional
result is taken to be the most exact. It
can be seen that the result from SPICE 2 has errors in
risetime, gain and propagation
delay whereas the result

ing

using

program.

The

individual

device

characteristic

were

R-CAP

is reasonably

accurate.

For

example,

the

CURTIC13:

MSSF13T MODEL

+Vl

+Vl

FOR G&

+Vl

455

ICS

+V,

+Vl

+V,

V.
A

circuit

model

time-domain

TRIGGER
L

H x,

The

current

control

for

the

&

illustrate

13.

Fig.

Circuit design for a MESFET

!4
- V2

of less than

MESFET

short-puke generator.

timing

come

circuit.

from

detailed

de-

the drain

effects,

gate

discussed.

The

experimental

models,

such

as a

model.

the use of the model,

It

use with
been

describing

has been

must

accurate

internal

simulated,

pulses

model

for
has

transit-time

parasitic

or from

two-dimensional
To

MESFET
programs

characteristics,

measurements

was

GaAs

of accurately

and circuit

parameters

the

simulation

importance

capacitance,

for

circuit

scribed.

CONCLUSION

was

shown

an IC

possible

to

100 ps in a triggerable
Such

circuit

circuit

design

produce
manner

would

be

short
with

useful

an
for

purposes.
ACKNOWLEDGMENT

The

OUTPUT

Y
-o

author

Design

assistance
f

is particularly

Automation
in

the user-defined

the

group,
use

indebted
SSTC,

of R-CAP

to V. Alwin

Somerville,
and

the

NJ

of the
for

development

his
of

model.

u
o
g

o
>

REFERENCES

-1 -

INPUT

[1]

-,o~

[2]
TIME

[pS)

Fig. 14. Calculated output voltage as a function of time for MESFET

pufse generator of Fig. 13 with VI= 4 V, V2 = 3 V; MESFET. ConRL=R3=
stants are A=O, a=2.3 Vl, VT=2.63 V, /3=26.3 pA/pm
0.15 Q/pm,
R2=0.5
Q/pmj
r= 10 ps, V~l= 1.0 V, FET widths:
Drivers = 100 ~m, Load= 75 t.tm source follower= 100 Pm source
foflower load= 75 t,an, dual-gate FET widths: lower= 100 ~~ upper=
150 p~ load capacitor=O.5 pF, C,z =0.06 fF/p~
C13=0.2 fF/pm.

[3]

[4]

[5]

gain predicted

by SPICE

dicts

2.53 and

the

error

in propagation

lated to the neglect

in gain

delay

approximately
characteristics

The second example

triggerable

half-width
width

for

bursts

pre-

is 2.38. The

2 is primarily

re-

the sharply
of Fig. 11.

model

(in

saturating

is an IC design capable of producof

short

of 15 GHz

pulses.

were

The

with

goal

design

R-CAP simulation program. It is seen that the final pulse

width is about 77 ps which is well under the design goal of
100 ps. In addition, the circuits output is not broadened
by triggering with a slow input step, as shown. This is due
to the high gain achieved by the FET inverter gates. The
pulse train can be stopped by returning the input voltage
to the high state.
effect

degradation
studied

upon

the

output

of the individual

by further

simulation.

waveform
MESFETS

[8]

[9]

a gain-band-

to be used. The

[n

was a

developed is a triggerable ring oscillator with a NAND gate

connected across two stages. Fig. 13 illustrates the circuit.
Fig. 14 shows the output pulse train as calculated by the

The

[6]

effects and the error

of the JFET

of 100 ps and MESFETS

product

R-CAP

result

SPICE

of transient-time

is due to the inability

SPICE
2) to
current-voltage
ing

2 is 1.59 whereas

two-dimensional

produced

[10]

[11]

Apr. 1979.
A. Madjar
and F. J. Rosenbaq
A practi&f
ac Iarge-signaf
model for GaAs microwave
MiMFETs~
in Proc. IEEE
MTT-S
1979 Znt. Microwace
$vnp.
(Orlando, FL, IEEE
Cat. No.
79CH1439-9
MTT-S), pp. 399-401,
1979.
C. Rauscher and H. A. Willin&
Quasi-static
approach to simulating nonlinear
GaAs FET behavior?
in Proc. IEEE MTT-S
1979
Int. Microwace
$vnp. (Orlando,
FL IEEE Cat. No. 79CH1439-9
MlT-S),
pp. 40?2-404, 1979.
M. S. Shur, Analytical
model of GaAs MESFETs~
IEEE Trans.
Electron Deuices, vol. ED-25, pp. 612-61S, June 1978.
L. W. Nage~ SPICE 2: A computer program to simulate semiconductor cireuitefl
Electronics
Research Lab, CM. Eng., Univ. Cali-

fornia, Berkeley, Memo. ERL-M520, May 1975.

R, Van Tuyl and C. A. Liechti, Gdfimn
arsenide digitaf integrated eircuits~ Air Force Avionics Lab., AFSC, WFAFB, Tech.
Rept. AFALTR-74-40,
Mar. 1974.
R. L. Van Tuyl, C. A. Liechti, and C. A. Stolte, Gallium arsenide
digitaf integrated circuits:
Air Force Avionics Lab., AFW~
WFAFB, Tech. Rept. AFAL-TR-26-264, Apr. 1977.
R. PUOCLH. Haus, and H. StaZ Signal and noise properties of
gallium arsenide microwave field-effect trrmsistorsfl in Adcunces in
Electronics and Electron P@ics New York: Academic Press, 1975,
38, pp. 195-205.
C. F. Krumm
et aL, Low noise field effect transistors
Huges
Research
Labs,
AFAL-TR-78-182,
Finaf
Rep.
for
AFA~
AFWAL,
AFSC, WPAFB,
Nov, 1978,
S. M. Sze, P@wics of SemiconductorDeeices. New York
Wiley pp.
340-362,
1969.
R. B. Fair, Graphical
desing and iterative
analysis of the &
parameters
of GaAs FETs~
IEEE
Trans. Electron Deoices, vol.
ED4, pp. 357-362, June 1974.
VOL

[12]

[13]
[14]

by

can be easily

M. Reiser, A two-dimensional FET model for de, ac and large

Trans. Electron Deeices, vol. ED-20, pp.
signaf analysis: IEEE
3545, Jan. 1973.
J. J. Barnes, R. J. Loand G. L Hadda~ Finite-element
simulation of GaAs MESFETS with lateral doping profiles and
submicron gates, IEEE Trans. Electron Devices, vol. ED-23, pp.
1042-1048, Sept. 1976.
K. Yamaguchi, S. A@
and H. Koder~
Two-dimensional
numefical analysis of stability criteria of GaAs FETs, IEEE
Tram. Electron Devices, vol. ED-23, pp. 12S312S9, Dec. 1976.
T. Wada and S. Frey, Physicat basis of short-channel MESFET
operator: IEEE Tram Electron Devices, vol. ED-26, pp. 476-490,

[15]

H. Fukui,
Determination
of the basic device parameters
of a
GaAs MESFET~
Bell $vst. Tech. J. vol. 58, no. 3, pp. 771-797,

IEEE TRANSACTIONS ON MICROWAVS THEORY AND TECHNIQUES, VOL. MIT-28, NO. 5, MAY 1980

456

dimensions
on the operation of Gurm devices: Proc. IEEE, vol.
56, pp. 2056-2057,
1968.
J. Maupin,
P. Greiling, and N. Alexopoulos, Speed power

Mar. 1979.
[16]

[17]
[18]

[19]

[20]

D. A Hodges, Modeling and simulation of

insulated-gate field-effect transistor switching circuits, IEEE J.
Solid-State
Circuits, vol. SC-3, pp. 285-289, Sept. 1968.
Devices. New York: Wiley,
S. M. Sze, Physis of Semiconductor
1969, p. 371.
W. R. Curtice, Analysis of the properties of three-tenninaf transTrans. Electron Devices, VOL
ferred-electron logic gates: IEEE
ED-24, pp. 1353-1359, Dec. 1977.
H. A. Willing, C. Rauscher, and P. deSantis, A technique for
predicting large-signal performance of a GSAS MESFETfl IEEE
Trans. Microwave
TheoV Tech. vol. MTT-26, pp. 10171023, Dec.
1978.
G. S. Kino and P. N. Robson, The effect of small transverse
I-L Shichman

and

[21]

tradeoff in GSAS FET integrated circuits: paper presented at 1st

Specialty Conf. Gigabit Logic for Microwave Systems, Orlando,
FL, May 1979.
R. L. Van Tuyl, C. A. Liechti, R. E. Lee, and E. Gowen, GsAs
MESFET logic with 4-GHz clock rate: IEEE J. Solid State
Circuits, vol. SC-12, pp. 485-496, Oct. 1977.
S. Asai, F. Murai, and H. Kodera, GaAs dual-gate Schottkybarner FETs for microwave frequencies, IEEE Trans. Electron

[22]

[23]

Devices, vol. ED-22, p. 897, Oct. 1975.

C. Davis and M. Payne, The R-CAP
program,
an integrated
circuit simulator:
RCA Eng., vol. 21, no. 1, p. 66, 1975.

[24]

Intrinsic
Response Time
MESFETS
of GaAs,
MASAYUKf

INO

AND

MASAMICHI
Invited

MMmct-A

time of

response

normafly

off MESFETS

of Normally
Off
Si, and Inl?
OHMORI,

Paper

for high-speed

logic operation

of a normafly

off FET.

lXENT~Y,
R
on

used
F~T,

dissipation

for

MES~ETs

high-speed

logic

a propagation

delay

power

of

circuits.
per

41

have

mW

gate

been

Iy ly

ND=1x 106cm-3

The two-dirrtensionaf

Using
($J

was

of

II.

actively

a normally
34 ps with

obtained

[1].

For

normally
off FETs,
77 ps of ~~ with
977 pW
of Pd, has
been achieved [2], and 72 ps with 890 pW as the latest
data [3]. From these experimental
results, the superiority
of GaAs to Si as basic material has been made clear. Since
~d of several tens picosecond
has been achieved, it is

significant
to estimate
the FET itself.

ly

h\\\\\\

analytical

model

for MESFET,

INTRODUCTION

GaAs

(PJ

1.

h\\\\\v

I
Fig.

I.

r-

and ~ wascalculatedusing a twu-dfrnensiorml mnnericaf analysis. The resofts indicate Uhat ~aAs is the best
rnateriaf amongthem. Ilte step responseof the I@ FET fs not as fast as
expectedfrom o/E chamcteristics due to low electric field in the channel
bgfc circmits made of GaA% Si

for low-power

MEMBER IEEE

an intrinsic

In this paper, tin, for normally

response

time (tti~

off MESFETS

model

analysis

M13SFET

with

Fig.

1. For

convenience

tion,
is

the

an

a semi-insulating

donor

concentration

1 ~m

equations

made of

and

where

simplicity

substrate

is not

is 1 x 106 cm-3.

the

sourcedrain

V2q =

q/6.

&r/i3t=

V(nw+

constant,

electric

field,
order

Over-Relaxation

0018-9480/80/0500-0456$00.75

and

layer
of

the

gate
is

in

calcula-

considered.

The

distance

planar

as shown

The

length

3 pm.

(/g)
Basic

are as follows:

ity.
(1)

active

of

(IdD

the

01980

(1)
(2)

q.D. Vn+
q is the

is

the

o is the drift
to

n)

D. Vrr)

q is the potential,

In

is a two-dimensional

n-type

VJtOt= V(q.n.v+

dielectric
Manuscript received July 24, 1979; revised January 10, 1980.
The authors are with the Musashino Electrical Communication
Laboratory, Nippon Telegraph and Telephone Public Corporation,
Musashino-shi, Tokyo 180, Japan.

the

type

of

GaAs, Si, and InP have been calculated

using a twodimensional
numerical analysis and the results compared.

for

ANALYTICAL MODEL

c.aE/at)=O

electronic

electron

velocity,

solve

these

method

was

and

equations,
used

for

Successive-under-l?elaxation

IEEE

(3)

charge,
density,

c is the

E is the

D is the diffusivthe

Successive-

Poissons

equation

method

was