COURSE CODE : ECE419

COURSE NAME : DIGITAL VLSI DESIGN

PART A
Q1(a) What do you mean by excitation table of flip flop? Draw it for JK FF.[2.5 Marks]

table that lists the required inputs for a given change of state. Such a list is called the excitation table.

Q(next)

(b) Differentiate between Latch and Flip Flop.

[2.5 Marks]

Both Latches and flip flops are circuit elements wherein the output not only depends on the current
inputs, but also depends on the previous input and outputs. The main difference between the latch
and flip flop is that a flip flop has a clock signal, whereas a latch does not. Basically, there are four
types of latches and flip flops: SR, D, JK and T. The major differences between these types of flip
flops and latches are the number of i/ps they have and how they change the states. There are
different variations for each type of latches and flip-flops which can enhance their operations.
(c) What do you mean by module?

[2.5 Marks]

Verilog provides the concept of a module. A module is the basic building block in
Verilog. A module can be an element or a collection of lower-level design blocks.
Typically, elements are grouped into modules to provide common functionality that is
used at many places in the design. A module provides the necessary functionality to
the higher-level block through its port interface (inputs and outputs), but hides the
internal implementation. This allows the designer to modify module internals without
affecting the rest of the design.
module <module_name> (<module_terminal_list>);
...
<module internals>
...
endmodule
(d) What are the various design approaches?

[2.5 Marks]

(e) What is implicit net declaration?

[2.5 Marks]

There are two basic types of digital design methodologies: a top-down design
methodology and a bottom-up design methodology. In a top-down design methodology,
we define the top-level block and identify the sub-blocks necessary to build the toplevel block. We further subdivide the sub-blocks until we come to leaf cells, which are
the cells that cannot further be divided.
In a bottom-up design methodology, we first identify the building blocks that are
available to us. We build bigger cells, using these building blocks. These cells are then
used for higher-level blocks until we build the top-level block in the design.

If a signal name is used to the left of the continuous assignment, an implicit net declaration will be
inferred for that signal name. If the net is connected to a module port, the width of the inferred net is
equal to the width of the module port.
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// Continuous assign. out is a net.

wire i1, i2;
assign out = i1 & i2; //Note that out was not declared as a wire
//but an implicit wire declaration for out
//is done by the simulator
(f) Design a 2:1 multiplexer using bufif gates

[2.5 Marks]

(g) What is the difference between blocking and nonblocking assignment?

[2.5 Marks]
Blocking assignments block the execution of the next statement while it is being executed.
a=1'b1;
b=1'b0;
Here assignment to 'b' happens only after assignment to 'a' is done
Whereas, non-blocking statement does not block the execution of the other statements.
a<=1'b1;
b<=1'b0;
Here assignments to 'a' and 'b' occur simulatneously.
Non-blocking statements are normally used in the modeling of the sequential logic.
(h) What is the significance of task and function?

[2.5 Marks]

Tasks are used in all programming languages, generally known as procedures or subroutines. The lines of
code are enclosed in task....end task brackets. Data is passed to the task, the processing done, and the result
returned. They have to be specifically called, with data ins and outs, rather than just wired in to the general
netlist. Included in the main body of code, they can be called many times, reducing code repetition.
A Verilog HDL function is the same as a task, with very little differences, like function cannot drive more
than one output, can not contain delays. Functions are declared with the keywords function and
endfunction.

Functions are used if all of the following conditions are true for the procedure:

There are no delay, timing, or event control constructs in the procedure.

The procedure returns a single value.
There is at least one input argument.
There are no output or inout arguments.
There are no nonblocking assignments

(i) What is the difference between resistive switch and normal switch in switch level modeling?
[2.5 Marks]

MOS, CMOS, and bidirectional switches discussed before can be modeled as corresponding
resistive devices. Resistive switches have higher source-to-drain impedance than regular switches
and reduce the strength of signals passing through them. Resistive switches are declared with
keywords that have an "r" prefixed to the corresponding keyword for the regular switch. Resistive
switches have the same syntax as regular switches.
rnmos
rcmos
rtran

rpmos
rtranif0

rtranif1

//resistive nmos and pmos switches

//resistive cmos switch
//resistive bidirectional switches.

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There are two main differences between regular switches and resistive switches: their source-todrain impedances and the way they pass signal strengths.
Resistive devices have a high source-to-drain impedance. Regular switches have a low source-todrain impedance.

Resistive switches reduce signal strengths when signals pass through them. The changes are
shown below. Regular switches retain strength levels of signals from input to output. The
exception is that if the input is of strength supply, the output is of strong strength

(j) Differentiate between distributed and lumped delays.

[2.5 Marks]

Distributed Delay
Distributed delays are specified on a per element basis. Delay values are assigned to individual elements in
the circuit. An example of distributed delays in module M.Distributed delays provide detailed delay
modeling. Delays in each element of the circuit are specified
Lumped Delay
Lumped delays are specified on a per module basis. They can be specified as a single delay on the output
gate of the module. The cumulative delay of all paths is lumped at one location
Lumped delays models are easy to model compared with distributed delays.
PART B
Q2(a) Design a 4 bit gray to binary code converter and write its Verilog code using gate level
modeling style.
[15 Marks]

OR
(b) What is race around condition and how to overcome from this problem in Flip Flops. Justify your
answer using waveform.
[15 Marks]

When the input to the JK flip-flop is j=1 and k=1, the race around condition occurs, i.e
it occurs when the time period of the clock pulse is greater than the propagation delay
of the flip flop. so the output changes or toggles in a single clock period. If it toggles
even number of times the output is same but if it toggles odd number of times then
the output is complimented. To avoid race around condition we cant make the clock
pulse smaller than the propagation delay so we use Positive or negative edge
triggering Since the hardware cost of msjk is more edge triggering is preferred to msjk.

Q3(a) Design a full adder using decoder and write the Verilog code for it.

[15 Marks]

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OR
(b) Design a BCD to Excess-3 code converter and write its Verilog code using gate level modeling
style.

[15 Marks]
Q4(a) Explain the advantage of non blocking assignment over blocking assignment using suitable
example.
[15 Marks]

Blocking assignment statements are executed in the order they are specified in a sequential block. A
blocking assignment will not block execution of statements that follow in a parallel block.
The = operator is used to specify blocking assignments.
Nonblocking assignments allow scheduling of assignments without blocking execution of the
statements that follow in a sequential block. A <= operator is used to specify nonblocking
assignments. Note that this operator has the same symbol as a relational operator,
less_than_equal_to. The operator <= is interpreted as a relational operator in an expression and as an
assignment operator in the context of a nonblocking assignment. To illustrate the behavior of
nonblocking statements and its difference from blocking statements.
OR
(b) Explain the different timing control in behavior modeling with suitable example.

[15 Marks]

Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no
timing control statements, the simulation time does not advance. Timing controls provide a way to
specify the simulation time at which procedural statements will execute. There are three methods of
timing control: delay-based timing control, event-based timing control, and level-sensitive timing
control.
Delay-Based Timing Control

Delay-based timing control in an expression specifies the time duration between when the statement
is encountered and when it is executed. We used delay-based timing control statements when
writing few modules in the preceding chapters but did not explain them in detail. In this section, we
will discuss delay-based timing control statements. Delays are specified by the symbol #. Syntax for
the delay-based timing control statement is shown below.
delay3 ::= # delay_value | # ( delay_value [ , delay_value [ ,
delay_value ] ] )
delay2 ::= # delay_value | # ( delay_value [ , delay_value ] )
delay_value ::=
unsigned_number
| parameter_identifier
| specparam_identifier
| mintypmax_expression
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Delay-based timing control can be specified by a number, identifier, or a mintypmax_expression.

There are three types of delay control for procedural assignments: regular delay control, intraassignment delay control, and zero delay control
Event-Based Timing Control
An event is the change in the value on a register or a net. Events can be utilized to trigger execution
of a statement or a block of statements. There are four types of event-based timing control: regular
event control, named event control, event OR control, and level-sensitive timing control.
Level-Sensitive Timing Control
Event control discussed earlier waited for the change of a signal value or the triggering of an event.
The symbol @ provided edge-sensitive control. Verilog also allows level-sensitive timing control,
that is, the ability to wait for a certain condition to be true before a statement or a block of
statements is executed. The keyword wait is used for level-sensitive constructs.
always
wait (count_enable) #20 count = count + 1;

In the above example, the value of count_enable is monitored continuously. If count_enable is 0, the
statement is not entered. If it is logical 1, the statement count = count + 1 is executed after 20 time
units. If count_enable stays at 1, count will be incremented every 20 time units.

Q5(a) Design a D-ff using UDP with all possible combinations.

[15 Marks]

//Define level-sensitive latch by using UDP.

primitive latch(q, d, clock, clear);
//declarations
output q;
reg q; //q declared as reg to create internal storage
input d, clock, clear;
//sequential UDP initialization
//only one initial statement allowed
initial
q = 0; //initialize output to value 0
//state table
table
//d clock clear : q : q+ ;
?

: ? : 0 ; //clear condition;
//q+ is the new output value

1
0

1
1

0
0

: ? : 1 ; //latch q = data
: ? : 0 ; //latch q = data

?
0
endtable

: ? : - ; //retain original state if clock = 0

= 1
= 0

endprimitive
OR
(b) Design a 4to1 multiplexer using UDP with all possible combinations.

[15 Marks]

// 4-to-1 multiplexer. Define it as a primitive

primitive mux4_to_1 ( output out,input i0, i1, i2, i3, s1, s0);
table
// i0 i1 i2 i3, s1 s0 : out
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1
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endtable
endprimitive

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;
;
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Q6(a) With the help of a neat diagram explain the Architecture of FPGA.

[15 Marks]

FPGAs comprise an array of uncommitted circuit elements, called logic blocks, and
interconnect resources, but FPGA configuration is performed through programming by
the end user. An illustration of a typical FPGA architecture appears in Figure 2. As the
only type of FPD that supports very high logic capacity, FPGAs have been responsible
for a major shift in the way digital circuits are designed.

In the figure, equivalent gates refers loosely

to number of 2-input NAND gates. The chart
serves as a guide for selecting a specific device
for a given application, depending on the logic
capacity needed. However, as we will discuss
shortly, each type of FPD is inherently better
suited for some applications than for others. It
should also be mentioned that there exist other
special-purpose devices optimized for specific
applications (e.g. state machines, analog gate
arrays, large interconnection problems).
However, since use of such devices is limited
they will not be described here. The next subsection discusses the methods used to
implement the user-programmable switches that are the key to the user-customization of FPDs.
OR
(b) What are the features of FPGA? Explain in detail.
Large Complex Functions
Programmability, Flexibility.
Massively Parallel Architecture
Processing many channels simultaneously cf MicroProcessor sequential processing
Fast Turnaround Designs
SRAM Based. Standard IC Manufacturing Processes (Memory Chips)
Leading Edge of Moores Law
Mass produced. Inexpensive.
Many variants. Sizes. Features.
Not Radiation Hard
Power Hungry

[15 Marks]

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-- End of Question Paper --

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