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The DMA I/O technique provides direct access to the memory while the microprocessor is
temporarily disabled.
DMA
Direct Memory Access.
In memory-memory or memory-peripherals communication, the processor is a middleman
which is not really needed.
Used with HOLD HOLDA signals.
DMA requires another processor - The DMA Controller or DMAC- to generate the memory and
I/O addresses.
8237 is a DMAC.
In IBM PC, 8237 was used to speed up the read or write operation by the slow 8088
processor.
Nowadays, It is usually used by sound cards and by memory controllers to generate row
address for refreshing.
Direct memory access (DMA) is a feature of modern computer systems that allows certain
hardware subsystems to read/write data to/from memory without microprocessor intervention,
allowing the processor to do other work.
Used in disk controllers, video/sound cards etc, or between memory locations
.
Typically, the CPU initiates DMA transfer, does other operations while the transfer is in progress,
and receives an interrupt from the DMA controller once the operation is complete.
Can create cache coherency problems (the data in the cache may be different from the data in the
external memory after DMA)
Basic DMA concept
DMA channel: system pathway used by a device to transfer information directly to and from
memory. There are usually 8 in a computer system
DMA controller: dedicated hardware used for controlling the DMA operation
Single-cycle mode: DMA data transfer is done one byte at a time
Burst-mode: DMA transfer is finished when all data has been moved
BASIC DMA TERMINOLOGY
8237 pins
<number>
CLK: System clock
CS: Chip select (decoder output)
RESET: Clears registers, sets mask register
READY: 0 for inserting wait states
HLDA: Signals that the p has relinquished buses
DREQ3 DREQ0: DMA request input for each channel
DB7-DB0: Data bus pins
IOR: Bidirectional pin used during programming
and during a DMA write cycle
IOW: Bidirectional pin used during programming
and during a DMA read cycle
EOP: End of process is a bidirectional signal used as input to terminate a DMA process or as
output to signal the end of the DMA transfer
A3-A0: Address pins for selecting internal registers
A7-A4: Outputs that provide part of the DMA transfer address
HRQ: DMA request output
DACK3-DACK0: DMA acknowledge for each channel.
AEN: Address enable signal
ADSTB: Address strobe
MEMR: Memory read output used in DMA read cycle
MEMW: Memory write output used in DMA write cycle
8237
8237/
8257
IOR:
IOR:
It is active low ,tristate ,buffered ,Bidirectional lines.
In the slave mode it function as a input line. IOR signal is generated by microprocessor to read
the contents 8257 registers.
In the master mode it function as a output line. IOR signal is generated by 8257 during write
cycle
IOW:
IOW:
It is active low ,tristate ,buffered ,Bidirectional control lines.
In the slave mode it function as a input line. IOR signal is generated by microprocessor to write
the contents 8257 registers.
In the master mode it function as a output line. IOR signal is generated by 8257 during read
cycle
CLK:
CLK:
It is the input line ,connected with TTL clock generator.
This signal is ignored in slave mode.
RESET:
Used to clear mode set registers and status registers
A0-A3:
These are the tristate, buffer, bidirectional address lines.
In slave mode ,these lines are used as address inputs lines and internally decoded to access
the internal registers.
In master mode, these lines are used as address outputs lines,A0-A3 bits of memory address
on the lines.
CS:
CS:
It is active low, Chip select input line.
In the slave mode, it is used to select the chip.
In the master mode, it is ignored.
A4-A7:
These are the tristate, buffer, output address lines.
In slave mode ,these lines are used as address input lines.
In master mode, these lines are used as address outputs lines,A0-A3 bits of memory address
on the lines.
READY:
READY:
It is a asynchronous input line.
In master mode,
When ready is high it receives the signal.
When ready is low, it adds wait state between S1 and S3
In slave mode ,
this signal is ignored.
HRQ:
It is used to receiving the hold request signal from the output device.
HLDA:
HLDA:
It is acknowledgment signal from microprocessor.
MEMR:
It is active low ,tristate ,Buffered control output line.
In slave mode, it is tristated.
In master mode ,it activated during DMA read cycle.
MEMW:
It is active low ,tristate ,Buffered control input line.
In slave mode, it is tristated.
In master mode ,it activated during DMA write cycle.
TC (Terminal Count):
TC (Terminal Count):
It is a status of output line.
It is activated in master mode only.
It is high ,it selected the peripheral.
It is low ,it free and looking for a new peripheral.
MARK:
It is a modulo 128 MARK output line.
It is activated in master mode only.
It goes high ,after transferring every 128 bytes of data block.
HLDA becomes active to indicate the processor has placed its buses at high-impedance state.
as can be seen in the timing diagram, there are a few clock cycles between the time
that HOLD changes and until HLDA changes
HLDA output is a signal to the requesting device that the processor has relinquished control
of its memory and I/O space.
one could call HOLD input a DMA request input and HLDA output a DMA grant
signal
Description
It containing Five main Blocks.
Data bus buffer
Read/Control logic
Control logic block
Priority resolver
DMA channels.
Modes of Operation
Rotating priority Mode:
The priority of the channels has a circular sequence.
Fixed Priority Rotating Mode:
The priority is fixed.
TC Stop Mode
Auto Load mode
Extended Write mode
DMA Cycles
DMA read
DMA write
DMA Verify