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Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
E91Y46F64-TE
CXD2500BQ
0.3 to +7.0
0.3 to +7.0
0.3 to +7.0
20 to +75
40 to +125
0.3 to +0.3
0.3 to +0.3
V
V
V
C
C
V
V
V
C
V
1 VDD value of 4.75 V (min.) is for the double-speed playback mode at vari-pitch control reset. For the low
power consumption special playback mode, VDD value is 3.6 V (min.). 2 In the normal-speed playback
mode VDD value is 4.5 V (min.)
2 Low power consumption, special playback mode
Set the internal operation of LSI at the double-speed mode, and half the crystal oscillation frequency. This
will result in the normal-speed playback mode.
3 VDD value of 5.25 V (max.) is for the double-speed playback mode at vari-pitch control reset. For normalspeed playback and the low power consumption special playback mode, the VDD value is 5.5 V (max.).
I/O Capacity
Input pins
CI 12 pF max.
Output pins
CO 12 pF max. at high impedance
Note: Test Conditions
VDD=VI=0 V
fM=1 MHz
CXD2500BQ
VCKI
VPCO
53
XTAO
XTAI
56
XTSL
FSTT
Block Diagram
54
53
17
19
C4M 57
23 AVDD
Clock
generator
C16M 58
21 AVSS
32K RAM
PDO 11
Digital PLL
vari-pitch
double speed
EFM
demodulator
12 VSS
Address
generator
PCO 20
FIL1 19
Priority
encoder
FIL0 18
Sync
Protector
CLTV 22
D/A
data processor
RF 24
ASY1 26
52 VSS
Serial/Parallel
processor
VCO0
73 VDD
Register
VCO1
33 VDD
30 PSSL
49 DAO 1 to 6
MUX
68 MUTE
ASY0 27
ASYE 28
Timing
Generator
WFCK 62
Peak detector
SCOR 63
EXCK 65
Digital out
Subcode
P-W
Processor
SBSO 64
60 DOUT
59 MD 2
EMPH 61
71 DATA
SQCK 67
SQSO 66
MON
Error corrector
Subcode
Q
Processor
74 CLOK
CPU interface
72 XLAT
FSW
MDP
CLV
processor
MDS 43
Noise
shaper
TEST 10
77 DATO
Servo
auto
sequencer
Timing
Generator 2
79 CLKO
78 XLTO
18-times
over samplling
filter
NC
Asymmetry
correction.
32
31
75 69
76
80
WDCK
SEIN
MIRR
CNIN
FOX
SENS
51
LRCK
LOCK
50
APTL
APTR
70
XRST
CXD2500BQ
DA08
DA09
45 44
43 42
41
DA07
46
DA06
DA04
48 47
DA05
DA03
50 49
DA02
52 51
DA01
VSS
53
APTR
XTAI
55 54
APLL
XTAQ
57 56
XTSL
59 58
FSTT
MD2
60
C4M
DOUT
62 61
C16M
EMPH
64 63
WFCK
SCOR
SBSO
Pin Configuration
EXCK
65
40
DA10
SQSO
66
39
DA11
SQCK
67
38
DA12
MUTE
68
37
DA13
SENS
69
36
DA14
XRST
70
35
DA15
DATA
71
34
DA16
XLAT
72
33
VDD
D2500B
77
28
ASYE
XLTO
78
27
ASYO
CLKO
79
26
ASYI
MIRR
80
25
BIAS
10 11
12
13 14
15 16
17 18
19
20 21
22 23
24
CLTV
AVSS
PCO
FILI
FILO
VCKI
VPCO
NC
PDO
RF
DATO
AVDD
NC
NC
29
NC
76
VSS
CNIN
TEST
PSSL
VCOI
30
VCOO
75
NC
SEIN
LOCK
WDCK
MDS
CLOK
31
MDP
LRCK
74
MON
32
FSW
73
FOK
VDD
CXD2500BQ
Pin Description
Pin
No.
1
2
3
4
5
Symbol
I/O
Description
FOK
FSW
MON
MDP
MDS
I
O
O
O
O
Z, 0
1, 0
1, Z, 0
1, Z, 0
LOCK
1, 0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
NC
VCOO
VCOI
TEST
PDO
VSS
NC
NC
NC
VPCO
VCKI
FILO
FILI
PCO
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
NC
30
PSSL
31
32
33
WDCK
LRCK
VDD
O
O
34
DA16
35
DA15
36
DA14
37
38
39
40
DA13
DA12
DA11
DA10
O
O
O
O
Focus OK input. Used for SENS output and servo auto sequencer.
Output used to switch the spindle motor output filter.
Output for spindle motor ON/OFF control
Output for spindle motor servo control
Output for spindle motor servo control
Output is H when the GFS signal sampled at 460 Hz is H. Output is
L when the GFS signal is L 8 or more times in succession.
O
I
I
O
1, 0
1, Z, 0
O
I
O
I
O
I
I
I
I
O
I
1, Z, 0
Input used to switch the audio data output mode. L for serial output,
H for parallel output.
1, 0
D/A interface for 48-bit slot. Word clock f=2Fs
1, 0
D/A interface for 48-bit slot. LR clock f=Fs
Power supply (+5 V)
Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot
1, 0
(2s complements, MSB first) when PSSL=0.
1, 0
Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0.
Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2s
1, 0
complements, LSB first) when PSSL=0.
1, 0
Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0.
1, 0
Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0.
1, 0
Outputs DA11 when PSSL=1, or GTOP when PSSL=0.
1, 0
Outputs DA10 when PSSL=1, or XUGF when PSSL=0.
5
CXD2500BQ
Pin
No.
Symbol
I/O
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
DA09
DA08
DA07
DA06
DA05
DA04
DA03
DA02
DA01
APTR
APTL
VSS
XTAI
XTAO
XTSL
O
O
O
O
O
O
O
O
O
O
O
56
FSTT
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
C4M
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
MUTE
SENS
XRST
DATA
XLAT
VDD
CLOCK
SEIN
CNIN
DATO
XLTO
CLKO
O
O
I
O
O
O
O
O
I
O
I
I
I
I
I
80
MIRR
I
O
I
I
I
I
O
O
O
Description
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
CXD2500BQ
Note:
The data at the 64-bit slot is output in 2s complements on an LSB-first basis. The data at the 48-bit slot is
output in 2s complements on an MSB-first basis.
GTOP monitors the state of Frame Sync protection. (H: Sync protection window released)
XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is
effected..
XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK
coincides with a change point of the EFM signal.
The GFS signal turns H upon coincidence between Frame Sync and the timing of interpolation protection.
RFCK is a signal generated at 136-s periods using a crystal oscillator.
C2PO is a signal to indicate data error.
XRAOF is a signal issued when a jitter margin of 28F is exceeded by the 32K RAM.
CXD2500BQ
Item
Input voltage.
H level
Input voltage
L level.
Input voltage
H level
Input voltage
L level
Input voltage
Output
voltage (3)
Output voltage
H level
Output voltage
L level
Output voltage
H level
Output voltage
L level
Output voltage
L level
Output
voltage (4)
Output
voltage (2)
Output
voltage (1)
Input
voltage (3)
Input
voltage (2)
Input
voltage (1)
Electrical Character
DC characteristics
Output voltage
H level
Output voltage
L level
Min.
Typ.
Max.
0.7VDD
VIH (1)
Unit
Related pins
V
1
VIL (1)
VIN (2)
VIN (2)
VIN (3)
0.3VDD
Schmitt circuit
input
0.8VDD
V
2
0.2VDD
VSS
VDD
VDD0.5
VDD
Analog input
4
VOL (1)
IOL=1 mA
0.4
VDD0.5
VDD
V
5
VOL (2)
IOL=2 mA
0.4
VOL (3)
IOL=2 mA
0.4
VDD0.5
VDD
7
VOL (4)
IOL=0.36 mA
0.4
ILI
VI=0 to 5.25 V
1, 2, 3
ILO
VO=0 to 5.25 V
Related pins
1 XTSL, DATA, XLAT, MD2, PSSL
2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, MIRR, VCKI, ASYE
3 CLTV, FILI, RF
4 MDP, PDO, PCO, VPCO
5 ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO,
XLTO, SENS, MDS, DA01 to DA16, APTR, APTL, LRCK, WFCK
6 FSW
7 FILO
8 SENS, MDS, MDP, FSW, PDO, PCO, VPCO
CXD2500BQ
AC Characteristics
(1) XTAI and VCOI pins
1) During self-oscillation
Item
Oscillation frequency
Symbol
fMAX
Min.
7
Typ.
Max.
34
Unit
MHz
tWHX
13
500
tWLX
13
500
Pulse period
tCX
26
1,000
Input H level
VIHX
VDD1.0
ns
V
Input L level
VILX
0.8
Rising time
Falling time
tR, tF
10
ns
tCX
tWHX
tWLX
VIHX
VIHX0.9
VDD/2
XTAI
VIHX0.1
VILX
tR
tF
3) With sine waves input to XTAI and VCOI pins via capacitor
(Topr=20 to +75 C, VDD=AVDD=5.0 V5 %)
Item
Input amplitude
Symbol
V1
Min.
2.0
Typ.
Max.
VDD+0.3
Unit
Vp-p
CXD2500BQ
Symbol
fCK
tWCK
tSU
tH
tD
tWL
fT
tWT
Min.
Typ.
Max.
0.65
750
300
300
300
750
Unit
MHz
ns
MHz
ns
300
1/fCK
tWCK
tWCK
CLOK
DATA
XLAT
tSU
tH
tD
EXCK
CNIN
SQCK
tWT
tWL
tWT
1/fT
SUBQ
SQCK
tSU
tH
Description of Functions
1
CPU Interface and Commands
CPU interface
This interface is used to set various modes using DATA, CLOK, and XLAT.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
D1
D2
Data
D3
D0
D1
D2
D3
Address
750ns or more
XLAT
Registers 4 to E
Valid
300ns max
The command addresses of the CXD2500B and the data capable of being set are shown in Table 1-1.
When XRST is set to 0, the CXD2500B is reset, causing its internal registers to be initialized to the values
listed in Table 1-2.
10
11
CLV CRTL
CLV mode
counter setting
Traverse monitor
Audio CTRL
Func specification
MODE specification
KICK (D)
Brake (B)
Auto sequence
D3
Command
name
Register
Commands
D1
Address
D2
D0
D1
AS0
D0
DSPB
D CLV
A SEQ
Mute-F
D OUT
8,192
2.9 ms
D PLL
WSEL
4,096
1.45 ms
0.09 ms 0.045 ms
CM3
PWM MD
DCLV
MDP1
Gain
32,768
UP
Vari
CM2
TB
MDP0
Gain
16,384
Down
Vari
CM1
TP
MDS1
Gain
8,192
Mute
Table 1-1
CM0
Gain
CLVS
MDS0
Gain
4,096
ATT
16,384
5.8 ms
0.18 ms
AS1
Data 1
AS2
D2
CDROM
32,768
11.6 ms
0.36 ms
0.18 ms
AS3
D3
2,048
PCT1
MAIN
BiliGL
2,048
D3
1,024
PCT2
SUB
BiliGL
D1
512
FLFC
512
Data 2
1,024
D2
256
256
D0
128
128
D3
64
64
32
32
D1
Data 3
D2
16
16
D0
D3
D1
Data 4
D2
D0
CXD2500BQ
12
CLV CRTL
CLV mode
counter setting
Traverse monitor
Audio CTRL
Func specification
MODE specification
Auto sequencer
KICK (D)
Brake (B)
Auto sequence
Command
name
Register
Reset Initialization
D3
D2
D1
Address
D0
D3
D2
Data 1
D1
Table 1-2
D0
D3
D2
Data 2
D1
D0
D3
D2
D1
Data 3
D0
D3
D2
D1
Data 3
D0
CXD2500BQ
CXD2500BQ
1
Meanings of Data Set at Command Addresses
$4X Command
Command
CANCEL
FOCUS-ON
1 TRACK JUMP
10 TRACK JUMP
2N TRACK JUMP
M TRACK MOVE
AS3
0
0
1
1
1
1
AS2
0
1
0
0
1
1
AS1
0
1
0
1
0
1
AS0
0
1
RXF
RXF
RXF
RXF
RXF=0 FORWARD
RXF=1 REVERSE
If a Focus-ON command ($47) is canceled during execution, $02 is issued and the auto sequence operation
is discontinued.
If a Track Jump or Track Move command ($48 to $4F) is canceled during execution, the auto sequence
operation is discontinued.
$5X Command
Used to set timers for the auto sequencer.
Timers set: A, E, C, and B
Command
Blind(A, E), Overflow(C)
Brake(B)
Example:
D3
0.18 ms
0.36 ms
D1
0.045 ms
0.09 ms
D0
0.022 ms
0.045 ms
D2
5.8 ms
D1
2.9 ms
D0
1.45 ms
Data 3
D3 D2 D1 D0
Data 4
D3 D2 D1 D0
27
23
$6X Command
Used to set a timer for the auto sequencer.
Timer set: D
Command
D3
KICK (D)
11.6 ms
Example:
D2
0.09 ms
0.18 ms
$7X Command
Used to set the number of auto sequencer track jumps/moves.
Data3
Data 2
Command
D3 D2 D1 D0 D3 D2 D1 D0
Auto sequencer track
jump number setting
215
214
213
212
211
210
29
28
26
25
24
22
21
20
This command sets the value of N for 2N track jump and M track move execution using the auto sequencer.
13
CXD2500BQ
The maximum number of tracks that can be counted is 65,535. However, in the case of 2N track jumps, it is
subject to mechanical restrictions due to the optical system.
When the number of tracks to be jumped is smaller that 15, the signals input from CNIN are counted. When
it is 16 or larger, the signals input from the MIRR pin are counted. This count signal selection contributes
toward improving the accuracy of high-speed track jumping.
Command
D3
D2
MODE specification
CDROM
$8X Command
Command
C2PO timing
CDROM=1
1-3
CDROM=0
1-3
Command bit
D. out Mute F=1
D. out Mute F=0
D1
D. OUT
Mute-F
AS0
WSEL
Processing
CDROM mode is entered. In this mode, average value
interpolation and preceding value holding are not performed.
Audio mode is entered. In this mode, average value
interpolation and preceding value holding are performed.
Processing
When Digital Out is ON (pin MD2=1), DA output is muted.
Da output muting is unaffected by the setting of Digital Out.
D/A Out D.out Mute with F=1
MD2=1
(D. out-ON)
dB
dB
Mute-ON
Mute-OFF
Command bit
WSEL=1
WSEL=0
MD2=0
(D. out-OFF)
dB
0dB
$9X Command
Command
Func specification
Data 1
D3
DCLV
ON-OFF
D2
DSPB
ON-OFF
D1
A. SEQ
ON-OFF
14
D0
D. PLL
ON-OFF
D3
BiliGL
MAIN
Data 2
D2
BiliGL
Sub
D1
FLFC
CXD2500BQ
Command bit
CLV mode
DCLV ON-OFF=0
DCLV ON-OFF=1
(FSW and MON are
unnecessary)
Contents
FSW=L, MON-H, MDS-Z, MDP=servo control signal, with carrier
In CLVS mode
frequency of 230 Hz at TB=0 and 460 Hz at TB=1
FSW=Z, MON=H, MDS=speed control signal with carrier frequency of
In CLVP mode
7.35 kHz, MDP=phase control signal with carrier frequency of 1.84 kHz
MDS= PWM polarity signal. Carrier
DCLV when
frequency=132 kHz
PWM, MD=1
MDS= PWM absolute value output (binary).
In CLVS or
Carrier frequency=132 kHz
CLVP mode
MDS= Z
DCLV when
MDP= ternay PWM output.
PWM, MD=0
Carrier frequency=132 kHz
In the Digital CLV servo mode with DCLV ON-OFF set to 1, the sampling frequency of the internal digital filter
is switched at the same time as the switching between CLVP and CLVS.
Therefore, for CLVS, the cut-off frequency fC is 70 Hz when TB is set to 0, and 140Hz when TB is set to 1.
Command bit
DSPB=0
DSPB=1
Processing
Normal-speed playback. ECC quadruple error correction is made. Vari-pitch
control is enabled.
Double-speed playback. ECC double error correction is made. Vari-pitch control
is disabled.
Set FLFC at 1 when in double-speed playback mode (exclude the low power consumption special playback
mode). However, FLFC can be set to 0 during PLL pull-in (lock). Set to 0 for all other modes.
SENS Output
Microcomputer serial register
values (Latching unnecessary)
$0X
$1X
$2X
$3X
$4X
$5X
$6X
$AX
$BX
$CX
$EX
$7X, 8X, 9X, DX, FX
ASEQ=0
ASEQ=1
Z
Z
Z
Z
Z
Z
Z
GFS
COMP
COUT
OV64
Z
SEIN (FZC)
SEIN (A, S)
SEIN (T. Z. C)
SEIN (SSTOP)
XBUSY
FOK
SEIN (Z)
GFS
COMP
COUT
OV64
0
15
CXD2500BQ
COUT
OV64
Command bit
DPLL=0
DPLL=1
Command bit
BiliGL SUB=0
BiliGL SUB=1
Meaning
SENS is at High-Z state.
SEIN signal, which was input to the CXD2500B, is output from SSP.
L when auto sequencer is in operation; H when terminated.
Output of the signal (normally FOK input from RF) input to the FOK pin. H when
Focus OK is received.
H when regenerated Frame Sync is obtained at the correct time.
Used in counting the number of tracks set in register B. H when the count is
latched to register B twice in succession. It is reset to L level when the count of
CNIN inputs equals the originally set number for register B.
Used in counting the number of tracks set in register B. H when the count is
latched to register B, then to register C. It is toggled every time the count of CNIN
inputs reaches the value set in register B.
L when after passing through the sync detection filter, the EFM signal become
longer than the 64 channel clocks.
Meaning
RFPLL enters analog mode. PDO, VCOI, and VCOO are used.
RFPLL enters digital mode. PDO becomes Z.
BiliGL
MAIN=0
STEREO
SUB
BiliGL
MAIN=1
MAIN
Mute
16
CXD2500BQ
$AX Command
Command
Audio CTRL
Data 1
D3
Vari
UP
D2
Vari
DWN
Data 2
D1
D0
D3
D2
Mute
ATT
PCT1
PCT2
Vari UP
Vari DWN
Pitch
+0.2% +0.1%
+0%
Command bit
Meaning
Mute=0
Muting is off unless condition to make muting occurs.
Mute=1
Muting is on. Peak register reset.
-0.1% -0.2%
XTal 0%
Command bit
Meaning
ATT=0
Attenuation is off.
ATT=1
12dB
17
CXD2500BQ
D3
Gain
MDP1
D2
Gain
MDP0
D1
Gain
MDS1
D0
Gain
MDS0
Gain
CLVS
Explanation
Only DCLV=1 is effective.
DCLV=1 and DCLV=0 are both
effective.
This command is used to externally set the spindle servo gain when DCLV=1.
Gain setting for CLVS mode: GCLVS
Gain
Gain
Gain
MDS1
MDS0
CLVS
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
GCLVS
Note:
12dB
6dB
6dB
0dB
0dB
+6dB
Gain
MDP0
0
1
0
GMDP
6 dB
0 dB
+ 6dB
Gain
MDS1
0
0
1
18
Gain
MDS0
0
1
0
GMDS
6dB
0dB
+6dB
CXD2500BQ
$DC Command
Command
D3
D2
CLV CTRL
DCLV
PWM MD
TB
D1
TP
D0
CLVS
Gain
See $CX Command.
Command bit
DCLV PWM MD=1
DCLV PWM MD=0
Command bit
TB=0
TB=1
TP=0
TP=1
Description
In CLVS or CLVH mode, bottom value is held at periods of RFCK/32.
In CLVS or CLVH mode, bottom value is held at periods of RFCK/16.
In CLVS mode, peak value is held at periods of RFCK/4.
In CLVS mode, peak value is held at periods of RFCK/2.
CM3
0
1
1
1
1
1
0
STOP:
KICK:
BRAKE:
CLVS:
CLVP:
CLVA:
CM2
0
0
0
1
1
1
1
D3
CM3
D2
CM2
D1
CM1
CM1
0
0
1
1
0
1
1
CM0
0
0
0
0
0
1
0
Mode
STOP
KICK
BRAKE
CLVS
CLVH
CLVP
CLVA
D0
CM0
Explanation
See Timing Chart 1-7.
See Timing Chart 1-8.
See Timing Chart 1-9.
19
20
C2PO
CDROM=1
C2PO
CDROM=0
WDCK
LRCK
Rch C2 pointer
Lch C2 pointer
If C2 pointer=1,
data is NG
48bit Slot
CXD2500BQ
21
SQSO
SQCK
WFCK
SQSO
SQCK
CRCF
80
81
CRCF
D0
D2
16 bit
96 clock pulses
D1
Sub-Q Data
See "Sub Code interface"
L/R
96 bit data
Hold section
96 clock pulses
D4
D5
D6
R/L
CRCF
15-bit peak-data
Absolute value display, LSB first
D3
750ns to 120s
D13
D14
96
Peak data
L/R flag
L/R
CXD2500BQ
SQCK
WFCK
96 clock pulses
Measurement
CRCF
Measurement
CRCF
96 clock pulses
Measurement
CRCF
CXD2500BQ
22
CXD2500BQ
Z
n236 (nsec) n=0 to 31
Acceleration
MDP
Z
132KHz
7.6Sec
Deceleration
Acceleration
MDP
n236 (nsec) n=0~31
7.6Sec
MDP
FSW
MON
MDP
MDP
L
CXD2500BQ
KICK
DCLV=0
MDS
MDP
FSW
MON
MDS
MDP
H
Z
7.6s
MDP
H
L
24
CXD2500BQ
BRAKE
DCLV=0
MDS
MDP
FSW
MON
MDP
MDS
MDP
25
CXD2500BQ
2
Subcode Interface
In this section, the subcode interface will be explained.
The contents of the subcode interface can be externally read in two ways. The subcodes P through W totaling
8 bits can be read from SBSO by inputting EXCK to the CXD2500B.
Sub-Q can be read after conducting a CRC check on the 80bits of information in the subcode frame. First,
check SCOR and CRCF, then input 80 clock pulses to SQCK and read the data.
2-1 P-W Subcode Read
These subcodes can be read by entering EXCK immediately after the fall of WFCK. (See Timing Chart 2-1.)
2-2 80-bit Sub-Q Read
Figure 2-2 shows a block diagram of the peripheral part of the 80-bit Sub-Q register.
The Sub Q regenerated on a bit-per-frame basis is input to the 80-bit serial/parallel register and the CRC
circuit.
When the results of CRC of the 96-bit Sub-Q are OK, CRCF is set to 1 and the 96-bit data is output to
SQSO.
Furthermore, it is loaded into the 80-bit, parallel/serial register.
If SQSO is H after the output of SCOR, it can be taken that CPU has been loaded a new set of CRCOK
data.
When 80-bit data is loaded into CXD2500B, MSB and LSB are reversed within each byte of the data.
Therefore, the bits are ordered LSB-first within each byte, even though the byte arrangement is kept
unchanged.
When 80 bits of data are confirmed to have been loaded, SQCK is input to read the data. Subsequently in
the CXD2500B, the input of SQCK is detected and the retriggerable monostable multivibrator is reset during
Low.
The time constant of the retriggerable monostable multivibrator ranges from 270 to 400 s. If the time of
High for SQCK is less than this time constant, the monostable multivibrator will keep resetting, preventing the
contents of the P/S register from being loaded into the P/S register.
While the monostable multivibrator is resetting, data loading into the peak detection parallel/serial register
and 80-bit parallel/serial register is forbidden.
Therefore, while data read operation is carried out at clock periods shorter than the time constant of the
monostable multivibrator, the contents of these registers are retained without being rewritten by CRCOK, etc.
The CXD2500B permits the peak detection register to be connected to the shift-in of the 80-bit P/S register.
For Ring Control 1, the input and output are short-circuited during peak meter and level meter mode.
For Ring Control 2, the input and output are short-circuited during peak meter mode only.
The Ring Controls are arranged in this way in order for the registers to be reset each time their contents are
read in the level meter mode, while preventing destructive read in the peak meter mode.
To enable this control, 96 clock pulses must be input to the peak meter mode.
As afore mentioned, in the peak meter mode, the absolute time following the generation of a peak value is
stored.
These operations are shown in Time chart 2-3.
Note: To perform the above operations, the duration of the clock pulse input to SQCK must be between 750ns
and 120 s for both High and Low.
26
CXD2500BQ
Internal
PLL c lock
4.3218MHz
WFCK
SCOR
EXCK
750ns max
SBSO
S0S1
WFCK
SCOR
EXCK
SBSO
S0S1 Q R S T U V W S0S1
Same
P1
QR S T U VW
P1
Same
27
P2
P3
SUB-Q
SI
(ASEC)
LD
LD
SUBQ
LD
28
SO
LD
LD
Peak detection
SI
Ring control 2
SHIFT
LD
16
Monostable
multivibrator
LD
LOAD CONTROLE
CRCC
SHIFT
Mix
CRCF
ADDRS CTRL
LD
Ring control 1
(AMIN)
Order
Inversion
H G F E D C B A
A B C D E F G H
SIN
(AFRAM)
SQSO
SQCK
SO
CXD2500BQ
LD
29
SQSO
SQCK
SQCK
SQSO
SCOR
WFCK
CRCF
Monostable
multivibrator
(Internal)
CRCF 1
300ns max
ADR1
CRCF 1
ADR2
ADR3
CTL0
94
Determined by mode
93
92
91
80 or 96 Clock
750ns to 120s
Order
Inversion
ADR0
95
CTL1
96
CTL2
97
CTL3
CRCF 2
98
CXD2500BQ
CXD2500BQ
Other Functions
30
CXD2500BQ
16,9344MHz
(384Fs)
1/1000
1/4
Phase comparator
OSC
X'Tal
XTSL
1/4
1/1000+n
VPCO
LPF
VCO
19. 78 to 13.26MHz
VCKI
2/1 MUX
Vari-pitch
Up down counter
n=-217 to 168
Phase comparator
I/M
I/N
PCO
FILI
FILO
VCO
Digital PLL
RFPLL
D2500B
31
CLTV
CXD2500BQ
MNT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MNT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MNT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C1:
C1:
C1:
C1:
C1:
C1:
C2:
C2:
C2:
C2:
C2:
C2:
C2:
Description
No error detected.
C1 pointer reset.
1 error corrected.
C1 pointer set.
No error detected.
C1 pointer set.
1 error corrected.
C1 pointer set.
2 errors corrected.
C1 pointer set.
Uncorrectable error.
C1 pointer set.
No error detected.
C2 pointer reset.
1 error corrected.
C2 pointer reset.
2 errors corrected.
C2 pointer reset.
3 errors corrected.
C2 pointer reset.
4 errors corrected.
C2 pointer reset.
Uncorrectable error.
C1 pointer copied.
Uncorrectable error.
C2 pointer set.
32
CXD2500BQ
t=Dependent on error
condition
MNT3
C2 correction
C1 correction
MNT2
MNT1
MNT0
Strobe
Strobe
C4M
MNT0 to 3
Valid
Valid
Invalid
3-4 DA Interface
The CXD2500B has two modes of DA interface.
a) 48-bit slot interface
This is an MSB-first interface made up of LRCK signals with 48-bit clock cycles per LRCK cycle. While
the LRCK signal is High, the data going through this interface is of the left channel.
b)
33
34
DA16
WDCK
DA15
(4.23M)
LRCK
(88.2K)
R0
L ch MSB (15)
1 2
L ch MSB (15)
DA16 R0
WDCK
DA15
(2.12M)
LRCK
(44.1K)
6
L14
10
L13
11
L12
12
L0
24
L11
L9
R ch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2500BQ
35
DA 14
DA 13
(5.64M)
DA 12
(88.2K)
DA 14
DA 13
(2.82M)
DA 12
(44.4K)
R ch LSB (0)
L15
R ch LSB (0)
10
10
11
12
15
13
14
15
20
20
25
30 31 32
10
11
12
9 10 11 12 13 14 15 L ch LSB
13
30
32
14 R15
31
L ch LSB (0)
CXD2500BQ
CXD2500BQ
From sub-Q
ID0 ID1 COPY Emph
0
10
11
12
13
14
15
0/1
32
48
0
176
Bits 0-3: Sub-Q control bits required to pass the CRC twice in succession.
bit 29: Varipitch: 1 X'tal: 0
Table 3-6 Digital Out C bits
3-6 Servo Auto Sequencer
The servo auto sequencer controls a series of operation including auto-focusing and track jumping. When an
auto sequence command is received from CPU, the servo auto sequencer automatically executes autofocusing, 1-track jumping, 2N track jumping and M track moving.
During auto sequence execution (X Busy=Low), as SSP (servo signal processing LSI) is used exclusively,
commands from CPU are not transferred to SSP. Instead, the commands can be sent to CXD2500B.
To make this servo auto sequencer usable, connect a CPU, RF and SSP to the CXD2500B as shown in
Figure 3-7 and set A.SEQ ON-OFF of Register 9 to ON.
When the CLOK changes from Low to High while XBUSY is at Low, from that point on to a maximum of 100
sec, X BUSY does not become High.
Due to the monostable multivibrator which is reset when CLOK is Low (XBUSY=Low), transfer of erroneous
data to SSP is prevented when XBUSY changes from Low to High.
36
CXD2500BQ
(a)
RF
MIRR
FOK
MIRR
FOK
DATA
CLOK
XLAT
SENS
CXD2500B
SSP
C.out
SENS
DATA
CLK
XLT
CNIN
SEIN
DATO
CLKO
XLTO
Figure 3-7
37
Micro-computer
CXD2500BQ
Auto focus
Focus search up
Checking whether FZC has stayed High
longer than time E set in Register 5.
FOK=H
NO
YES
FZC=H
NO
YES
FZC=L
NO
YES
Focus servo ON
END
$47 latch
XLAT
FOK
SEIN(FZC)
BUSY
Command to SSP
Blind E
$03
$08
CXD2500BQ
(b)
Track Jump
Track jump operation includes 1, 10 and 2N track jumps. Do not perform this track jump unless the focus,
tracking and sled servos are on. Such steps as tracking gain up and braking are not included in this track
jump. Therefore, the commands for tracking gain up and brake ON ($17) must be issued in advance.
1-track jump
When a $48 is received from CPU (or a $49 from REV), the servo auto sequencer executes a FWD
(REV) 1-track jump as shown Figure 3-9. The values of blind A and brake B must be set in Register 5.
10-track jump
When a $4H is received from CPU (or a $4B from REV), the servo auto sequencer executes a FWD
(REV) 10-track jump as shown in Figure 3-10. The principal difference between the 1-track and 10-track
jumps is whether the sled is kicked or not. In the 10-track jump, the actuator after being kicked is braked
when CNIN has been counted 5 tracks. When the actuator has adequately slowed down as a result of
braking, the tracking and sled servos are turned on (this actuator slow-down is detected by checking
whether the CNIN period has exceeded overflow C specified in Register 5).
2N track jump
When a $4C is received from CPU (or a $4D from REV), the servo auto sequencer executes a FWD
(REV) 2N track jump. The number of tracks to be jumped is determined by N, set Register 7 beforehand.
The maximum permissible number is 216. In actual use, however, it is subject to limitation imposed by the
actuator.
When N is smaller than 16, the jumps are counted by means of counting CNIN signals. If N is 16 and
above, MIRR signals are counted instead of CNIN signals.
The 2N track jump sequence is basically the same as the 10-track jump sequence. The only difference
between them is that, in the 2N track jump sequence, the sled is kept moving for time D specified in
Register 6 after the tracking servo is turned on.
M track move
When a $4E is received from CPU (or a $4F from REV), the servo auto sequencer executes a FWD
(REV) M-track move as shown in Figure 3-12. The maximum value that can be set from M is 216. The
track moves are counted in the same way as for 2N track jumps. That is, when M is smaller than 16, the
moves are counted by means of counting CNIN signals. If M is 16 and above, MIRR signals are counted
instead of the CNIN signals. In this M track move, only the sled is moved. This method is suitable for a
large track move ranging from several thousand to several tens of thousand tracks.
39
CXD2500BQ
1 Track
Track Kick
Sled servo
WAIT
(Blind A)
CNIN=
NO
YES
Track REV
Kick
WAIT
(Brake B)
Track sled
Servo ON
END
CNIN
BUSY
Blind A
Commands to SSP
$28 ($2C)
Brake B
$2C ($28)
40
$25
CXD2500BQ
10 Track
Track, Sled
FWD Kick
WAIT
(Blind A)
CNIN=
5?
NO
YES
Track, REV
FWD Kick
C=Overflow?
NO
YES
Track, Sled
Servo ON
END
CNIN
BUSY
Blind A
Commands to SSP
CNIN 5count
$2A ($2F)
Overflow C
$2E ($2B)
$25
CXD2500BQ
2N Track
Track, Sled
FWD Kick
WAIT
(Blind A)
For the first 16 times CNIN is counted.
After that MIRR is counted.
CNIN (MIRR) =N
NO
YES
Track, REV
Kick
C=Overflow
NO
YES
Track Servo
ON
WAIT
(Klick D)
Sled Servo
ON
END
CNIN
(MIRR)
BUSY
Blind A
Commands to SSP
$2A ($2F)
Kick D
CNIN (MIRR)
N count
Overflow
$2E ($2B)
$26 ($27)
$25
CXD2500BQ
M Track move
WAIT
(Blind A)
CNIN is counted for M<16, MIRR
is counted for M16.
CNIN (MIRR) =M
NO
YES
Track, Sled
Servo ON
END
CNIN
(MIRR)
BUSY
Blind A
Commands to SSP
$22 ($23)
$25
43
CXD2500BQ
Digital CLV
Gain
CLVS U/D
MDS Error
MDP Error
0, 6dB
Measure
Measure
CLV P/S
Over Sampling
Filter-1
2/1 MUX
Gs(Gain)
GP(Gain)
CLV P
1/2
Mux
CLV S
CLV P/S
Over Sampling
Filter-2
Noise Shape
Modulation
MDP
Mode Select
MDS
DCLVMD
44
CXD2500BQ
D2500B
28
ASYE
ASYO
RF
24
R1
27
R1
R2
R1
ASYI
26
R1
25
BIAS
R1
R2
2
5
45
CXD2500BQ
Application Circuit
R1
C9
FESRCH
FEO
FLB
FGD
FS3
VC
FE
SENS
LDON
FOK
MUTE
SQCK
RV2
FOK
BCLK (64)
LRCK (64)
GTOP
RV1
FSW
SENS
RF
XRST
DATA (64)
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DATA
XRST
BCLK (64)
TE
MIRR
FOK
MON
MOP
C17
LOCK
MOS
AVSS
CLTV
VDD
GND GND
C15
22
RF
AVDD
DATA (64)
GND
C11
C16
NC
VCOO
DVCC 3 6
NC
VCOI
13
14
NC
TEST1
15
VPCO
10
16
VCKI
FILO
PDO
17
PCO
FILI
12
18
11
7
34
33
DFCT
19
VSS
NC
35
CC2
CC1
FOK
30
31
EFM 3 2
ASY
DFCT
27
20
23
21
SUBQ
CLOK
WDCK (48)
GND
MIRR 2 9
SENS
25
26
COUT
XRST
DGND 2 8
CP
CB
GND
TGU
XLT
DATA
48 47 46 45 44 43 42 41 40 39 38 37
CNIN
SEIN
24
C4M
C16M
DOUT
MO2
EMPH
WFCK
SBSO
SCOR
54
56
57
58
59
61
62
63
64
FSTT
53
55
60
XTAI
XTSL
XTAO
MNT3
RADF
MNT2
MNT1
MNT0
APTL
APTR
44
45
47
48
49
50
42
46
51
C2PO
43
52
RFCK
41
VSS
GFS
PLCK
WFCK
DOUT
PLCK
GFS
RFCK
RAOV
GND
TRACK-D
GND
FOCUS-D
C10
NC
PSSL
GND
GND
MNT0
MNT1
MNT2
MNT3
GND
STTP
UGFS
46
GND
SLED-D
GND
C23
C26
RFO
13 14 15 16 17 18 19 20 21 22 23 24
R4 R3
DATO
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
200p
GND
GND
WDCK
GND
GND
C2PO
MUTE
SPIND-D
GND
RFI
CLK
MUTE
ASYE
VCC
V0
VCC
DVee
DIRC
LOCK
GFS
CLK
XLT
VDD
TG2
AVCC
TAO
TA-
CXA1372Q
AVee
XLAT
DATA
CXD2500BQ
LRCK (48)
10
11
12
C27
GND
GND
C14
TE
TZC
SSTOP
SSTOP
GND
R2
R7
C28
R6
R11
C35
GND
GND
R12
AVDD
FE
TE
RF
LDON
C13
TDFCT
ISET
R13
VCC
GND
R10
R14
Vee
SL-
SQSO
EXCK
XUGF
ATSC
FSET
SCOR
SQCK
XLTO
GND
FE
FZC
VCC
MIRR
CLKO
BIAS
FD
GND
R5
R9
GND
GND
GND
C12
FDFCT
SL+
SLO
GND
GND
GND
GND
ASTI
ASTO
GND
1M
TD
SLD
SPD
BCLK
DATA
LRCK
DEMP
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
CXD2500BQ
Package Outline
Unit : mm
CXD2500BQ
80PIN QFP (PLASTIC)
23.9 0.4
+ 0.1
0.15 0.05
+ 0.4
20.0 0.1
64
0.15
41
65
16.3
17.9 0.4
+ 0.4
14.0 0.1
40
A
80
+ 0.2
0.1 0.05
24
0.8
0.12
+ 0.15
0.35 0.1
0.8 0.2
25
+ 0.35
2.75 0.15
0 to 10
DETAIL A
PACKAGE STRUCTURE
SONY CODE
QFP-80P-L01
EIAJ CODE
QFP080-P-1420-A
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.6g
CXD2500BQ
80PIN QFP (PLASTIC)
24.0 0.3
+ 0.4
20.0 0.1
+ 0.
0.15 1
0.05
25
24
0.8
0.12 M
+ 0.15
0.35 0.1
16.6
80
0.7 0.
40
+ 0.4
14.0 0.1
65
41
18.0 0.3
64
+ 0.2
0.1 0.05
2.7 0.1
0 to 10
3.1 MAX
0.15
22.6
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L121
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420-AX
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.6g
JEDEC CODE
47
CXD2500BQ
CXD2500BQ
QFP 80PIN (PLASTIC)
23.9 0.2
20.0 0.2
0.15 0.05
15
24
1
0.35 0.1
.2
15
25
4 1.0
14.0 0.2
40
80
C1
4 0.8
0.15
1.45
0.8 0.15
0.15
0 to 10
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L051
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420-AH
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.6g
JEDEC CODE
48
1.95 0.15
15
2.94 0.15
15
0.24 0.15
+ 0.20
2.7 0.16
17.9 0.2
65
0.8
41
64