Implementation of

Synchronous FIFO Memory Module

Introduction
A synchronous FIFO is a First-In-First-Out
queue consisting of a storage array with control
logic that manages the read and write of data
and generates status flags. The number of rows
of the array is called the DEPTH of the FIFO,
and the bit length of each row (i.e., the number
of columns of the array) is called the WIDTH
of the FIFO.A Synchronous FIFO has a single
clock port for both data-read and data-write
operations. Data presented at the module's datainput port (DIN) is written into the next
available empty FIFO location on a rising clock
edge when the write-request input (WR) is high

Write
Dout
Read
Din
Clock

Empty

Reset

Full

The FIFO full status output (FULL) indicates

that no more empty locations remain in the
module's internal array. Data can be read out of
the FIFO via the module's data-output port
(DOUT) in the order in which it was written by
asserting read-request (RD) prior to a rising
clock edge. The FIFO-empty status output
(EMPTY) indicates that no more data resides in
the module's internal memory

The FIFO status cannot be corrupted by

invalid requests. Requesting a read operation
while the EMPTY flag is active will not cause
any change in the current state of the FIFO.
Similarly, a write operation while the FULL
flag is active will not cause any change in the
current state of the FIFO. The RESET signal
clears internal control logic and . the status
flags.

Architecture
The basic building blocks of a synchronous FIFO
are: memory array, flag logic, and expansion
logic. Figure 1 shows the logic block diagram of a
synchronous FIFO. The memory array is built
from dual-port memory cells. These cells allow
simultaneous access between the write port and
the read port. This simultaneous access gives the
FIFO its inherent synchronization property. There
are no timing or phase restrictions between
accesses of the two ports. This means that while
one port writes to the memory at one rate, the
other port can read at another rate, independent of
one another. This also enables optimization of the
speed at which data is written to and read from the
memory array. Cypress offers the synchronous
FIFO CY7C42x5 in x9 & CY7C42x5 in x18 bit
width. Both provide a high speed of 66 MHz and
100 MHz operation respectively. Data is steered
into and out of the memory array by two pointers,
a read address pointer and write address pointer.
After each operation, the respective pointer is
incremented to allow access to the next address
sequentially in the array. See the tutorial on
synchronous FIFOs for more information. The
flag logic compares the value in each of the two
address pointers.

independent of one another. The only restriction

placed is that the simultaneous read and write
access should not be
If the difference between the two pointers is from/to the same
zero, the FIFO is empty and the empty flag is memory location.
asserted. If the difference between the two
values is equal to the depth of the part, the FIFO The
Synchronous
is full and the full flag is asserted. Other flags, FIFO has a single
such as half-full, programmable almost-empty clock port clk for
and programmable almost-full flags, are both data-read and
generated by the same means. The data-write
programmable flags are generated by comparing operations.
Data
the values programmed in an offset register with presented at the
the number of words in the FIFO. Finally, module's data-input
expansion logic is used to create logically deeper port write_data is
FIFOs, by cascading multiple parts in depth written into the next
expansion. In the normal non-depth cascading available
empty
operation, each of the address pointers wraps memory location on
back to zero when it reaches its maximum value. a rising clock edge
In the depth expansion mode, when an address when the writepointer reaches its maximum value, a pulse is enable
input
driven to an expansion pin, which passes a token write_enable
is
to another FIFO. After the token is passed, the high. The full status
address pointer does not increment until the output
fifo_full
token returns. Essentially, the responsibility for indicates that no
handling the write or read operation is passed to more
empty
another device. At any given time, only one locations remain in
FIFO in a depth expansion configuration handles the
module's
read operations and only one handles write internal
memory.
operations. When the token returns, the address Data can be read out
pointer is reset to zero and the operation of the FIFO via the
resumes.
module's
dataoutput
port
read_data in the
order in which it
The memory array can be implemented either
was written by
with array of flip-flops or with a dual-port
asserting
readread/write memory. Both of these
enable
signal
implementations allow simultaneous read and
read_enable prior to
write accesses. This simultaneous access gives
a rising clock edge.
the FIFO its inherent synchronization property.
The memory-empty
There are no restrictions regarding timing
status
output
between accesses of the two ports. This means
fifo_empty indicates
simply, that while one port is writing to the
that no more data
memory at one rate, the other port can be reading
resides
in
the
at another rate totally
module's
internal
memory. There are almost empty and almost full
flags too viz. fifo_aempty and fifo_afull which
can be used to control the read and write speeds
of the requestor and the source.

Functional Description