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SpyGlass CDC
Comprehensive, Low-Noise Clock Domain Crossing Verification
Overview
Among the many verification
challenges confronting system-on-chip
(SoC) designers today, clock domain
crossings (CDC) ranks near the
top in difficulty. Todays SoCs have
dozens or sometimes even hundreds
of asynchronous clock domains,
making it very difficult to verify using
conventional simulation or static
timing analysis (STA). RTL simulation
is not designed to verify metastability
effects which cause data transfer
issues across asynchronous clock
boundaries and STA does not address
asynchronous clock domains issues.
Introduction
CDC issues have become a leading cause of design errors. Such errors can add
significant time and expense to the design-and-debug cycle, and may even find their
way into silicon, necessitating costly respins. Besides the traditional CDC issues,
Reset Clock Domain (RDC) issues can also cause metastability in signals. Use of
asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up/boot sequences, etc. As a consequence, RDC issues are causing
more and more design errors. (Please refer to the SpyGlass RDC Datasheet for more
information about these reset domain crossing capabilities.) For both of these types of
issues, SpyGlass provides a high-powered, comprehensive solution.
SpyGlass RTL Signoff
Lint
Clock & reset verification
Power estimation & reduction
Power intent verification
Timing constraint verification
Design for test
F1
clk_B
EN
clk_A
D
F1
F2
F3
F4
clk_B
clk_A
F1
F2
F3
X
10
01
clk_A
clk_B
D1
rst_n
D1
D2
clk_B
rst_n
clk_B
clk_B
D2
F6
F7
F3
clk_A
clk_B
F2
F8
Y
F2
X
Y
F3
o_rst_n
o_rst_n
Synchronous de-assert
01 01 11 10 10 10
clk_A
EN
clk_B
clk_B
Reset synchronization
``
Hierarchical SoC flow to support IP
based design methodologies to deliver
quickest turnaround time for very
large size SoCs
Hierarchical
Intuitive debug
Low noise
Performance
Signoff QoR
``
Low learning curve and ease
of adoption
SpyGlass CDC
Simple setup
``
Integrated with other SpyGlass solutions
for RTL signoff for lint, constraints,
DFT and power
``
CDC-centric debug capabilities
Market Leader
Methodology
CDC Bugs
The success of static CDC verification
tools is determined by two critical
measuresthe time taken to sign off
the RTL and the completeness of CDC
verification. Conventional CDC analysis
tools fall short in both areas. They
generate large amounts of noise (false
violations), extending the verification cycle,
and provide poor coverage on various
types of CDC issues. Figure 2 describes
the class of bugs/scenarios, which, if
not verified correctly, can cause design
respins. These bugs can be structural as
well as functional in nature.
SpyGlass CDC
``
Hierarchical SoC flow to support IPbased design methodologies to deliver
quickest turnaround time for very
large SoCs
``
Integrated with the SpyGlass solution
which targets other RTL analysis, like
Lint, DFT, constraints and power
``
Fast performance
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