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XB8801R Series
An X-Scan Imaging XB8801R linear detector array is constructed of CMOS silicon photodiode array detector
chips mounted on a single printed-circuit board. The imaging circuit of each detector chip consists of a
contiguous linear array of photodiodes, a timing generator, digital scanning shift register, an array of charge
integrating amplifiers, sample-and-hold circuits, and signal amplification chain. Each detector array generates an
End-Of-Scan (EOS) pulse that can be used to initiate the scanning of the next detector array. Thus, a longer,
continuous detector array can be formed from a daisy chain of smaller detector arrays.
For x-ray scanning applications, a scintillator material tailored to the users application is attached to the surface
of the detector array to convert x-ray photons into visible light for detection by the photodiode array. The
XB8801R photodiode array is uniquely designed and processed to reduce radiation damage from the x-ray flux.
The signal processing circuits are positioned 2 mm away from the photodiode array. These circuits are shielded
from direct x-ray radiation using an external heavy-metal shield. The precision alignment of the metal shield
with respect to the signal processing circuits is performed at the factory using a special molded housing and chipon-board (COB) technology.
Key Features
Large element pitch with two selectable resolution modes: 0.1 mm and 0.2 mm
Different array lengths available:
o 2.0 inches (512 pixels at 0.1 mm, 256 pixels at 0.2 mm)
o 4.0 inches (1024 pixels at 0.1 mm, 512 pixels at 0.2 mm)
5-V power supply operation
Simultaneous integration by using an array of charge
integrating amplifiers
Sequential readout with a digital scanning shift register
Integrated CDS circuits allow low noise and wide dynamic range up to > 4000
User-specified scintillator material GOS:Tb, CsI:Tl etc.
Extended radiation hardness lifetimes
Applications
Linear x-ray imaging for industrial and food inspection
Linear x-ray imaging for homeland security and contraband screening
2014 X-Scan Imaging Corp.
Symboli
XB8801R-2.0
(high resolution
0.1-mm mode)iv
0.1
0.085
XB8801R-4.0
(low resolution
0.2-mm mode)
0.2
0.170
XB8801R-4.0
(high resolution
0.1-mm mode)
0.1
0.085
Unit
P
W
XB8801R--2.0ii
(low resolution
0.2-mm
mm mode)iii
0.2
0.170
Element pitch
Element
diffusion width
Element height
Number of
elements
Active area
length
0.300
256
0.150
512
0.300
512
0.150
1024
mm
51.2
51.2
102.4
102.4
mm
mm
mm
Parameter
Supply voltage
Reference voltage
Digital input voltages
Operating temperaturev
Storage temperature
v
Symbol
VDD
VREF
Min
0.3
0.3
0.3
5
10
Topr
Tstg
Max
+6
VDD + 0.3
VDD + 0.3
+60
+70
Unit
V
V
V
o
C
o
C
Symbol
VDD
VREF
Min.
4.75
Typ.
5
4.50
Max.
5.25
Unit
V
V
High level
Low level
Symbol
Min.
Typ.
Max.
Unit
f(CLK)
Vih
Vil
Ci
Ii
Voh
Vol
Co
40
VDD1.2
0
10
VDD0.75
0
VDD
0
40
+10
VDD
0
4000
VDD
0.8
VDD
0.4
50
KHz
V
V
pF
A
V
V
pF
Rref
Cfhs
0.5
pF
Cfls
1.5
pF
Zv
Cv
1
100
K
pF
200
mW
vi
Parameter
Symbol
Vos
High sensitivity
Low sensitivity
High sensitivity
X-ray sensitivityxii
Low sensitivity
Photo response non-uniformityxiii
High sensitivity
Noisexiv
Low sensitivity
Saturation output voltage
Dark offset voltagexi
Vd
S
PRNU
N
Vsat
XB8801R
(0.2 mm mode)
Min.
Typ.
Max.
VREF
40
40
40
40
900
300
10
10
2.0
0.7
3.0
XB8801R
(0.1 mm mode)
Min.
Typ.
Max.
VREF
40
40
40
40
450
150
10
10
1.0
0.6
3.0
Unit
V
mV
V/R
%
mVrms
V
Video output is negative-going output with respect to the output offset voltage.
Difference between output signal under dark conditions and Vref with an integration time of 1 ms.
xii
Measured with tube energy of 70KVp. Other scintillations with different sensitivity are available.
xiii
Measured without scintillation. When the photodiode array is exposed to uniform light which is 50% of the saturation exposure,
the Photo Response Non Uniformity (PRNU) is defined as follows:
PRNU = X X 100%
where X is the average output of all elements and X is the difference between the maximum and minimum outputs.
xiv
Measured with a video data rate of 750 KHz and an integration time of 1 ms in dark state.
xi
Saturation Output
Voltage (Vsat)
Output Offset
Voltage (Vos)
Saturation State
GND
RESET 1
VMS
VDD
GND
Timing Generator
3 TRIG
CLK 2
8 EOS
Shift Register
9 VIDEO
Hold Circuit
VREF 10
SNS 11
RS 12
N-1
Photodiode Array
Timing chartxv
1
5 14 15 16 17 18 19 20
CLK
tplw (RESET)
RESET
tphw (RESET)
~7.5 Clocks
~6.5 Clocks
Integration Time
n-1
TRIG
EOS
tf (CLK)
tr (CLK)
tplw (CLK)
th
tphw (CLK)
th
ts
ts
tplw (RESET)
tf (RESET)
Parameter
Clock pulse low/high width
Clock pulse rise/fall times
Reset pulse low widthxvi
Reset pulse high widthxvii
Reset pulse rise/fall times
Reset pulse setup timexviii
Reset pulse hold time
tphw (RESET)
tr (RESET)
Symbol
tplw (CLK), tphw (CLK)
tr (CLK), tf (CLK)
tplw (RESET)
tphw (RESET)
tr (RESET), tf (RESET)
ts
th
Min.
100
0
12 / f(CLK)
20
0
40
40
Typ.
20
16 / f(CLK)
20
Max.
30
30
Unit
ns
ns
ms
s
ns
ns
ns
xv
The falling of Video just before the 19th falling edge of CLK after transition of RESET from High to Low corresponds to the first
pixel. The video output for the first pixel should be read around the 20th falling edge and before the subsequent rising CLK edge while
Trig is high. After the first pixel, a pixel output appears on Video at every 4th clock cycle.
Care should be taken to prevent the rising edge of the RESET during the video output. Improper positioning of the RESET edges
can lead to interference with the read-out.
The falling edge of the RESET should follow the last pixel of the previous lines read-out. Thus, one cycle of RESET pulses cannot
be set shorter than the time equal to (17 + 4 N) clock cycles, where N is the number of pixels.
EOS of each detector chip appears during the output of the last pixel.
xvi
RESET must stay Low [tplw(RESET)] for at least twelve clock cycles.
xvii
The falling edge of RESET pulse determines the end of the integration time and the start of signal read-out, while the rising edge of
the RESET pulse determines the start of the integration time. As a result, the signal-charge integration time can be controlled
externally with the width of the RESET pulse [tphw(RESET)]. However, the charge integration does not start at the rise of a RESET
pulse but starts at the 8th falling edge of clock after the rise of the RESET pulse and ends at the 7th falling edge of clock after the fall of
the RESET pulse.
xviii
The rising and falling edges of RESET must observe the setup and hold time requirements around the falling edges of CLK.
xix
Pin
connections
Pin
No.
1
2
3
4
5
Symbol
Name
Description
RESET
CLK
TRIG
EXTSP
VMS
Reset Pulse
Clock Pulse
Trigger Pulse
External Start Pulse
Master/Slave
Selection Voltage
6
7
8
9
10
11
VDD
GND
EOS
VIDEO
VREF
SNS
Supply Voltage
Ground
End of Scan
Video Output
Reference Voltage
Sensitivity Selection
12
RS
Resolution Selection
Operation Mode
Master configuration:
Parallel readout: all detectors
Serial readout: 1st detector only
Slave configuration:
Serial readout: 2nd and later detectors
VMS
EXTSP
VDD
Dont care
GND
Readout circuit
In order to minimize noise and to maximize performance, an operational amplifier should be placed as close
to the detector to amplify the Video signal.
Information furnished by X-Scan Imaging is believed to be accurate and reliable. However, no responsibility is assumed by X-Scan Imaging Corporation for its use.
Users are responsible for their products and applications using X-Scan Imaging components. To minimize the risks associated with users products and applications,
users should provide adequate design and operating safeguards. No responsibility is assumed by X-Scan Imaging Corporation for any infringements of patents or
other rights of third parties that may result from the use of the information. No license is granted by implication or otherwise under any patent or patent rights of XScan Imaging Corporation.
2014 X-Scan Imaging Corp.
www.x-scanimaging.com