CHAPTER 8(2):

( )
SYNCHRONOUS
SEQUENTIAL CIRCUITS

Mealy state model

output = f (current state, current inputs)

Clock cycle:
w::
w
z:

t0
0
0

t1
1
0

t2
0
0

t3
1
0

t4
1
1

t5
0
0

t6
1
0

t7
1
1

t8
1
1

t9
0
0

Reset
w = 1z= 0
w = 0z= 0

B
w = 0z= 0

w = 1z= 1

t10
1
0

State table for the FSM

A
B

Next state

Output z

Present
state

w= 0

w= 1

w= 0

w= 1

A
B

A
A

B
B

0
0

0
1

Next state

Output

Present
state

w= 0

w= 1

w= 0

w= 1

0
1

0
0

1
1

0
0

0
1

Implementation
z
w

Clock

Resetn
(a) Circuit
t0
Clock

1
0

1
0

1
0

1
0

t1

t2

t3

t4

t5

(b) Timing diagram

t6

t7

t8

t9

t 10

Synchronous Mealy Machine

Synchronous (or registered) Mealy Machine

registered state AND outputs

avoids glitchy outputs

easy to implement in PLDs

Clock
Xi
I
Inputs
t

Zk
Outputs

Combinational
Logic for
Outputs and
Next State
State Register

Clock

state
feedback

Synchronous Mealy Machine

implementation
z

Q
Clock
Resetn
(a) Circuit
t0
Clock

1
0

1
0

1
0

1
0

1
0

t1

t2

t3

t4

t5

(b) Timing diagram

t6

t7

t8

t9

t 10

State diagram for Mealy machine :

register swapping
w= 0

w=0
A No transfer

Reset

Reset

A
w = 1

w = 1 R2
B R2 = 1, R3 = 1
out
in
w = 0
w = 1

w= 0
w= 1

D R3 = 1, R1 = 1, Done = 1
out
in

Moore type

= 1, R 3

in

= 1

C R1 = 1, R2 = 1
out
in
w = 0
w = 1

out

w = 0
w = 1

R1

w = 0
w = 1

R3

= 1, R 2

out

in

= 1

C
out

= 1, R 1

M l type
Mealy

in

= 1 , Done = 1

Implementation of the FSM

Interconnection wires

R
Resetn
Clock
Y2

y2
D

Q
Q

w
PAL-like block
Y1

y1
D

Q
Q

y1

D Q

Clock

Resetn

z
D Q

(Other macrocells are not shown)

y2

Clock

Gnd

Resetn
w

The circuit from the example

1 44

39

10

36

EPM7032
13
z

16
22

25
V DD

19

28

State minimization

High-level synthesis may generate many

redundant states
Fewer states may mean fewer F/Fs

Boundaries are power of two number of states

Fewest states usually leads to more opportunities for don't cares
May reduce the number of gates needed for implementation

D fi iti
Definition

Two states Si and Sj are said to be equivalent iff for every

possible input sequence
sequence, the same output sequence will be
produced regardless of whether Si or Sj is the initial sate.

State minimization,
minimization contd
cont d

Two conditions for two states to be

equivalent

output must be the same in both states

must transition to equivalent states for all input combinations

Algorithmic Approach to state minimization

very tedious to perform manually

automated for use in CAD tools

Partitioning Minimization Procedure

t show
to
h
th
thatt some states
t t are d
definitely
fi it l nott

terms

equivalent

0-successor of Si : the destination state when the input signal

w=0 is applied to the machine in state Si

1-successor
1
successor of Si : the destination state when the input signal
w=1 is applied to the machine in state Si
k-successors of Si : the destination states when the multiple
input signals are applied to FSM in state Si

k represents the set of all possible combinations of the inputs

Definition

A partition consists of one or more blocks

blocks, where each block
comprises a subset of states that may be equivalent, but the
states in a given block are definitely not equivalent to the stated

in other blocks

State table for Example 8

8.5
5

P1 = (ABCDEFG)
P2=(ABD)(CEFG)

0-successors
0
successors
1-successors
0-successors
1
1-successors

of (ABD): (BDB)
of (ABD): (CFG)

of (CEFG): (FFEF)
off (CEFG):
(CEFG) (ECDG)

P3=(ABD)(CEG)(F)

0-successors of (ABD): (BDB)

1-successors of (ABD): (CFG)

different outputs

P4=(AD)(B)(CEG)(F)

0-successors
1-successors
0-successors
1-successors

of (AD): (BB)
of (AD): (CG)

of (CEG): (FFF)
of ((CEG):
) (ECG)
(
)

P5=(AD)(B)(CEG)(F)

Next state
Present
state w = 0 w = 1
A
B
C
D
E
F
G

B
D
F
B
F
E
F

C
F
E
G
C
D
G

Output
z
1
1
0
1
0
0
0

Minimized state table

Nextstate

Present
state

w= 0

w= 1

Output
z

A
B
C
F

B
A
F
C

C
F
C
A

1
1
0
0

A vending machine design

Specification

nickels and dimes

15 cents
t ffor a piece
i
off candy
d tto b
be released
l
d ffrom th
the machine
hi
if 20 cents is deposited, it will not return the change, but it will
credit the buyer with 5 cents and wait for the buyer to make a
second
d purchase
h

Coin sensing signal generation

Clock
sense
N
sense
D
N
D

( ) Ti
(a)
Timing
i di
diagram
N
sense
N
Clock

Q
Q

Q
Q

(b) Circuit that generates N

State diagram
DN
Reset
DN
S1 0

DN

DN
DN

DN
D
S4 1

15c N

S2 0

10c

5
5c
S3 0

10c

S7 1

15c

DN
S6 0

S5 1 20c

15c

DN

20c
S8 1

S9 1

DN

State table

P1=(S1,S2,S3,S4,S5,S6,S7,S8,S9)
(S1 S2 S3 S4 S5 S6 S7 S8 S9)

P2=(S1,S2,S3,S6)(S4,S5,S7,S8,S9)

P3=(S1)(S3)(S2,S6)(S4,S5,S7,S8,S9)

P4=(S1)(S3)(S2,S6)(S4,S7,S8)(S5,S9)

P5=(S1)(S3)(S2,S6)(S4,S7,S8)(S5,S9)

Next state
Present
state DN =00 01 10 11

Output
z

S1

S1

S3 S2

S2
S3
S4
S5
S6
S7
S8
S9

S2
S3
S1
S3
S6
S1
S1
S3

S4 S5
S6 S7

S8 S9

0
0
1
1
0
1
1
1

Minimized state table and diagram

DN

Next state
Present
Output
state DN =00 01 10 11
z

S1 0
N

DN
D
DN

S3 0
N

DN

S1
S2
S3
S4
S5

10c

S2 0
N

5c

DN
S5 1

20
20c
15c

S4 1

S1
S2
S3
S1
S3

S3 S2
S4 S5
S2 S4

0
0
0
1
1

Mealy-type
Mealy
type FSM
DN 0

S1
N0

D1

DN 0
N1

D 0

S3
N0

D1
S2

DN 0

Incompletely specified FSMs

In general, the partitioning procedure is less

useful when incompletely specified FSMs are
involved.
Next state

Output z

Present
state

w= 0

w= 1

w= 0

w= 1

A
B
C
D
E
F
G

B
D
F
B
F
E
F

E
G
C
D

0
0
0
0
0
0
0

1
0
1
1

Incompletely specified state table

assume the unspecified outputs are 0s

Present

Next state

Outputz

state w = 0 w = 1 w = 0 w = 1
A
B
C
D
E
F
G

B
D
F
B
F
E
F

E
G
C
D

0
0
0
0
0
0
0

1
0
1
1

assume the unspecified outputs are 1s

P1=(ABCDEFG)
P2=(ABDG)(CEF)
P3=(AB)(D)(G)(CE)(F)
(AB)(D)(G)(CE)(F)
P4 =(A)(B)(D)(G)(CE)(F)
P5=P4
6 states
P1=(ABCDEFG)
P2=(AD)(BCEFG)
P3=(AD)(B)(CEFG)
P4 =(AD)(B)(CEG)(F)
P5=P4
4 states

the choice of values assigned to unspecified

outputs is of considerable importance

State minimization

State minimization

it is possible to develop a minimization techniques that

searches
h ffor equivalent
i l t states
t t based
b
d di
directly
tl on equivalent
i l t
relations

reducing
g number of states in a g
given FSM will not necessarily
y
lead to a simpler implementation

the effect of assignment may have a greater influence on the

simplicity of implementation than does the state minimization
relies on the CAD tools to implement FSM efficiently

Example: Modulo-8 counter using

the sequential circuit approach
w = 0

A/0

w= 0

w= 1

B/1

w= 0

w= 1

C/2

w= 0

w= 1

w= 1

w= 1

H/7

G/6
w= 1

w= 0

D/3

F/5
w= 1

w= 0

E/4
w= 1

w= 0

State diagram
g
for the counter

w= 0

State table for the counter

Next state

Present
state

w= 0

w= 1

A
B
C
D
E
F
G
H

A
B
C
D
E
F
G
H

B
C
D
E
F
G
H
A

State minimization ??

Output
0
1
2
3
4
5
6
7

State-assigned
State
assigned table for the counter

Present
state
y2 y1 y0
A
B
C
D
E
F
G
H

000
001
010
011
100
101
110
111

Next state
w= 0

w= 1

Y2 Y1 Y0

Y2 Y1 Y0

000
001
010
011
100
101
110
111

001
010
011
100
101
110
111
000

Count
z2z1z0
000
001
010
011
100
101
110
111

Karnaugh maps for D flip-flops for

the counter
y1y0

wy2

y1y0

00

01

11

10

00

01

11

10

wy2

00

01

11

10

00

01

11

10

Y0 = wy0 + wy0

Y1 = wy1 + y1y0 + wy0y1

y1y0

wy
y2

00

01

11

10

00

01

11

10

Y2 = wy2 + y0y2 + y1y2 + wy0y1y2

Circuit diagram for the counter implemented

with
ith D fli
flip-flops
fl
w

Y0

y0

Y1

y1

Y2

Q
Q

Clock
Resetn

y2

FSM as an arbiter circuit

to control access by various devices to a

shared resources in a given system

only one device can use the resource at a time

positive edge triggered

signals
i
l

request, grant for each device

assume there are three devices in the system
y
device 1, device 2, device 3
device 1 has the highest priority
no preemption

State diagram for the arbiter

000

Reset

r 1r 2 r 3

Reset
Idle

Idle
0
0xx

r1

1
1xx

gnt1 g1 = 1

gnt1 g1 = 1
x0x

1xx

r2

01x

x1x
gnt3 g3 = 1
xx1

r1

r 1r 2

gnt2 g2 = 1

t2 g2 = 1
gnt2
xx0

r1

001

r3

r2
gnt3 g3 = 1
r3

r 1r 2 r 3

VHDL code for the arbiter

WHEN gnt2 =>

LIBRARY ieee;
USE ieee.std_logic_1164.all;

IF r(2) = '1' THEN y <= gnt2 ;

ELSE y <= Idle ;

ENTITY arbiter IS
PORT (
Clock, Resetn

END IF ;

: IN STD_LOGIC ;

WHEN gnt3 =>

r : IN STD_LOGIC_VECTOR(1
STD LOGIC VECTOR(1 TO 3) ;
g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;

IF r(3) = '1' THEN y <= gnt3 ;

END arbiter ;

ELSE y <= Idle ;

ARCHITECTURE Behavior OF arbiter IS

TYPE State_type
State type IS (Idle, gnt1, gnt2, gnt3) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0'
0 THEN y <= Idle ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN Idle =>
IF r(1) = '1' THEN y <= gnt1 ;
ELSIF
SIF r(2)
r( ) = '1'
1 THEN
TH N y <= gnt2
gnt ;
ELSIF r(3) = '1' THEN y <= gnt3 ;
ELSE y <= Idle ;
END IF ;
WHEN gnt1 =>
IF r(1)
( ) = '1' THEN
N y <= g
gnt1 ;
ELSE y <= Idle
END IF ;

END IF ;
END CASE ;
END IF ;
END PROCESS ;
g(1) <= '1' WHEN y = gnt1 ELSE '0' ;
g(2) <= '1' WHEN y = gnt2 ELSE '0' ;
g(3) <= '1' WHEN y = gnt3 ELSE '0' ;
END Behavior ;

Incorrect VHDL code for the grant

signals
.
.
.
PROCESS( y )
BEGIN
G
IF y = gnt1 THEN g(1) <= '1' ;
ELSIF y = gnt2 THEN g(2) <= '1' ;
ELSIF y = gnt3 THEN g(3) <= '1'
1 ;
END IF ;
END PROCESS ;
END Behavior ;

incorrect code

.
.
.
PROCESS(( y )
BEGIN
g(1) <= '0' ;
g(2) <= '0' ;
g(3) <=
< '0' ;
IF y = gnt1 THEN g(1) <= '1' ;
ELSIF y = gnt2 THEN g(2) <= '1' ;
ELSIF y = gnt3
g
THEN g(3)
g( ) <= '1' ;
END IF ;
END PROCESS ;
END Behavior ;

correct code

Implementation of the arbiter circuit

a large version of the arbiter that controls eight

devices

requestt signals
i
l : r1, r2, ,r8
grant signals : g1,g2, ,g8

Implementation in a CPLD

four F/Fs

idle: 0000, gnt1=0001, , gnt8=1001

g8 = y4 y3 y2 y1

Y4 = r1r2 r3 r5 r6 r7 r8 y1 y2 y3 y4 + r1r2 r3r4 y1 y2 y3 + r8 y1 y2 y3 y4 + r4 y1 y2 y3 y4

complex output and next function

Simulation results for the arbiter

circuit

Output delays in the arbiter circuit

g 8 = y4 y3 y2 y1

Implementation in an FPGA

one-hot
h t lik
like encoding
di
iinstead
t d off using
i
ffour
F/Fs

why?
idle = 000000000, gnt1=110000000, , gnt8=100000001

g8=y1

Y8 = r1 y8 + r1 y 9
output
p and next state ffunctions are relativelyy simple
p

Speed of operation

two versions of the circuit implemented in an FPGA chip

nine state F/Fs : maximum clock rate of 88.5 MHz

four F/Fs : maximum clock rate of 54.1 MHz

Output delay when using one-hot

encoding