BW Chapt 02 PDF

Assembly Language for Intel-Based
Computers, 5th Edition

Kip Irvine
Chapter 2: IA-32 Processor

Architecture
Slides prepared by the author

Revision date: June 4, 2006
(c) Pearson Education, 2006-2007. All rights reserved. You may modify and copy this slide show for your personal use,
or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.
Chapter 2 Outline
2.1 General Concepts
2.2 IA-32 Processor Architecture
2.3 IA-32 Memory Management
2.4 Components of an IA-32 Microcomputer
2.5 Input-Output System
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
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2.1.1 Basic microcomputer design
2.2.2 Instruction execution cycle
2.2.3 Reading from memory
2.2.4 How programs run
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2.1.1 Basic Microcomputer Design

The central processor unit (CPU): where all the calculations and logic
operations take place
Clock: synchronizes internal CPU operations with other
components
Control unit (CU): coordinates sequence of execution steps
Arithmetic logic Unit (ALU): performs arithmetic and bitwise
processing
data bus
registers
Central Processor Unit
(CPU)
ALU
CU
Memory Storage
Unit
I/O
Device
#1
I/O
Device
#2
clock
control bus
address bus
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Basic Microcomputer Design (Cont.)

The memory storage unit: where instructions and
data are held while a computer program is running.
A bus: a group of parallel wires that transfer data
from one part of the computer to another.
Data bus
Transfer instruction and data
Address bus
Hold the address of instruction and data
Control bus
Synchronize the actions of all devices
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Clock
Clock: repeatedly pulses at a constant time
Synchronizes all CPU and BUS operations
Machine cycle (clock cycle time): the most basic unit of
time for machine instruction
A machine instruction requires at least one clock cycle
to execute.
A few instructions (e.g., the multiply instruction) require in
excess of 50 clocks
one cycle
1
0
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Clock (Cont.)
The duration of a clock cycle is the reciprocal of the
clock
s speed
1 GHz ( 1 billion oscillations per second)
=> clock cycle time = 1 ns (nanosecond)
Synchronous operation: need a clock

Clock is used to trigger events
Asynchronous operation: does not require a system

clock
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Examples
2.1.2 Instruction Execution Cycle

The execution of a single machine instruction can be
divided into a sequence of individual operations.
Three primary operations: fetch, decode and execute.
Two more steps are required when the instruction uses a
memory operand: fetch operand and store output
operand
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2.1.2 Instruction Execution Cycle (cont.)
PC
I-1
memory
op1
op2
fetch
read
registers
registers
instruction
I-1 register
decode
write
Fetch
Decode
Fetch operands
Execute
Store output
write
program
I-2 I-3 I-4
flags
ALU
execute
(output)
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Examples
Instruction Execution Cycle (Cont.)

Fetch
Fetch the instruction indexed by PC (program counter)
Copy it from memory into the CPU
Increment the PC
Decode
The control unit (CU) determine the type of instruction and
tell the ALU
Fetch operand
If a memory operand is needed, the CPU retrieve the
operand from memory
Execute
Store output operand
If the output operand is in memory, write it back
p.s.
Each step takes at least one clock cycle
Each processor has its own steps, e.g, IA-32 has six stages
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10
Multi-Stage Pipeline
Pipelining makes it possible for processor to execute instructions in
parallel
Instruction execution divided into discrete stages
Stages
1
S1
I-1
S3
S4
8
9
10
S6
I-1
I-1
5
6
7
S5
I-1
3
4
Cycles
Example of a nonpipelined processor.

Many wasted cycles.
S2
I-1
I-1
I-2
I-2
I-2
I-2
11
I-2
12
I-2
For k states and n instructions, the number of required cycles is:

n*k
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11
Pipelined Execution
More efficient use of cycles, greater throughput of instructions:
S ta g e s
Cycles
1
2
3
4
S1
S2
I- 1
I- 2
I-1
I-2
5
6
7
S3
S4
I-1
I-2
I-1
I-2
S5
I-1
I-2
S6
I-1
I-2
For k states and n instructions, the number of required cycles is:

k + (n 1)
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12
Wasted Cycles (pipelined)

When one of the stages requires two or more clock cycles, clock
cycles are again wasted.
Cycles
S ta g e s
S2
S3
S1
I-1
2
3
I-2
I-3
I-1
I-2
I-1
4
5
I-3
I-2
I-3
exe
S4
S5
I-1
I-1
6
7
I-2
I-2
I-1
8
9
I-3
I-3
I-2
10
11
S6
I-1
I-2
I-3
I-3
For k states and n instructions, the number of required cycles is: k + (2n 1)
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Superscalar
A superscalar processor has multiple execution pipelines. In the
following, note that Stage S4 has left and right pipelines (u and v).
S ta g e s
S4
Cycles
S1
S2
S3
S5
S6
I-1
2
3
I-2
I-3
I- 1
I- 2
I-1
I-4
I- 3
I-2
I-1
I- 4
I-3
I-1
I- 2
I-4
I-3
I- 2
I-1
I-3
I- 4
I- 4
I-2
I-3
I-1
I-2
I-4
I-3
5
6
7
8
9
10
I-4
For k states and n instructions, the number of required cycles is: k + n
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14
2.1.3 Reading from Memory

Memory access is a bottleneck and multiple machine cycles are
required when reading from memory
It responds much more slowly than the CPU.
The steps are:

Address placed on address bus
Read Line (RD) set low to notify memory that a value is to be read
CPU waits one cycle for memory to respond
Read Line (RD) goes to 1, indicating that the data is on the data
bus
Cycle 1
Cycle 2
Cycle 3
Cycle 4
CLK
Address
ADDR
RD
Data
DATA
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15
Cache Memory
High-speed expensive static RAM both inside and
outside the CPU.
Level-1 cache: inside the CPU
Level-2 cache: outside the CPU
Cache hit: when data to be read is already in cache

memory
Cache miss: when data to be read is not in cache
memory.
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How a Program Runs

User
sends program
nam e to
O perating
system
gets starting
cluster from
searches for
program in
returns to
System
path
loads and
starts
Directory
entry
Current
directory
Program
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How a Program Runs (Cont.)

The user issues a command to run a certain program.
The OS searches for the program
s filename (in the
current directory or predetermined list of directories)
If found, the OS retrieves basic information, like file
size, physical location, about the program
s file from
the disk directory.
The OS loads the program file into memory.
The CPU begins to execute the program (process) by
jumping to the first instruction of the program
Now, the program is called a process
The process runs by itself

When the process ends, OS removes its handle and
memory
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Multitasking
OS can run multiple programs at the same time.
A process may optionally contains multiple threads of
execution.
Scheduler assigns a given amount of CPU time to
each running program.
Rapid switching of tasks
Gives illusion that all programs are running at once
The processor must support task switching.
The processor saves the state (e.g., registers, variables,
program counter) of each task before switching to a new
one
OS can assign varying priorities to tasks
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19
Chapter 2: What's Next

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20

2.2.1 Modes of operation
2.2.2 Basic execution environment
2.2.3 Floating-point unit
2.2.4 Intel Microprocessor history
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21
2.2.1 Modes of Operation

Protected mode
The native mode of the processor and all instructions and
features are available
Used by Windows and Linux
Programs are given separate memory areas (called
segments) with proper protection
Real-address mode
Native MS-DOS
Implements the programming environment of the Intel 8086
processor
All Intel processors boot in Real-address mode
Then the OS may switch to another mode
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Modes of Operation (cont.)

System management mode
Provides an operating system with a mechanism for
implementing
power management, system security, diagnostics
Implemented by computer manufactures
Virtual-8086 mode
While in Protected mode, the processor can directly execute
Real-address mode program in a safe multitasking environment.
Each program has its own 8086 computer
A special case of Protected Mode, so it is called Virtual
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2.2.2 Basic Execution Environment

Addressable memory
General-purpose registers
Index and base registers
Specialized register uses
Status flags
Floating-point, MMX, XMM registers
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Addressable Memory
Protected mode
4 GB
32-bit address
Real-address and Virtual-8086 modes

1 MB space
20-bit address
Protected mode while running program in Virtual8086 mode

Each program can access its own separate 1MB
memory
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25
Registers
Registers are high-speed storage locations directly inside the CPU
Intel registers
8 general-purpose registers
6 segment registers
EFLAGS: processor status flag
EIP: instruction pointer
32-bit General-Purpose Registers
EAX
EBP
EBX
ESP
ECX
ESI
EDX
EDI
16-bit Segment Registers

EFLAGS
EIP
CS
ES
SS
FS
DS
GS
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General-Purpose Registers
Used for arithmetic and data movement
EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP
Use 8-bit name, 16-bit name, or 32-bit name

Applies to EAX, EBX, ECX, and EDX
8
AH
AL
AX
EAX
8 bits + 8 bits
16 bits
32 bits
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27
Accessing Parts of Registers

Use 8-bit name, 16-bit name, or 32-bit name
Applies to EAX, EBX, ECX, and EDX
8
AH
AL
AX
EAX
8 bits + 8 bits
16 bits
32 bits
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28
Index and Base Registers

Some registers have only a 16-bit name for their
lower half:
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29
Some Specialized Register Uses (1 of 3)

EAX extended accumulator register
Used by multiplication and division instructions)
ECX loop counter

ESP stack pointer, extended stack pointer
register
ESI, EDI index registers
Extended source/destination index registers
EBP extended frame pointer (stack)

Used by high-level languages to reference function
parameters and local variables
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Segment register: as base locations for pre-assigned memory areas
CS code segment
Hold instruction
DS data segment
Hold variables
SS stack segment
Hold local variables and function parameters
ES, FS, GS - additional segments

EIP instruction pointer
Containing the address of the next instruction to be executed
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31

EFLAGS
Status and control flags
Each flag is a single binary bit
Control Flag
Control the operation of the CPU
Example, IF Flag (interrupt flag)
Status Flag
Reflect the outcome of some CPU operations
Example
Carry Flag (CF)
Overflow Flag (OF)
Sign Flag
Zero Flag
Auxiliary Carry Flag
Parity Flag
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32
Flags
Control Flags
Direction
Interrupt
Status Flags
Carry
unsigned arithmetic out of range
Overflow
signed arithmetic out of range
Sign
result is negative
Zero
result is zero
Auxiliary Carry
carry from bit 3 to bit 4
Parity
sum of 1 bits is an even number
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33
System Registers
System registers
Only permit access by programs running at the highest
privilege level (level 0), e.g., the Window XP
IDTR (Interrupt Descriptor Table Register)
GDTR (Global Descriptor Table Register)
LDTR (Local Descriptor Table Register)
Task Registers
Control Registers: CR0, CR2, CR3, CR4
Model-Specific Registers
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2.2.3 Floating-Point, MMX, XMM Registers

Floating-point unit: eight 80-bit floatingpoint data registers
ST(0)
ST(1)
ST(0), ST(1), . . . , ST(7)
ST(2)
arranged in a stack
ST(3)
used for all floating-point arithmetic
ST(4)
Registers for multimedia programming
ST(5)
Eight 64-bit MMX registers
ST(6)
Eight 128-bit XMM registers for singleinstruction multiple-data (SIMD) operations
Web site
ST(7)
Examples
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2.2.4 Intel Microprocessor History

Intel 8086, 80286
IA-32 processor family
P6 processor family
CISC and RISC
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36
Early Intel Microprocessors

Intel 8080
64K addressable RAM
8-bit registers
CP/M operating system
S-100 BUS architecture
8-inch floppy disks!
Intel 8086/8088
Mark the beginning of the modern Intel Architecture
family
IBM-PC Used 8088
1 MB addressable RAM
16-bit registers
16-bit data bus (8-bit for 8088)
separate floating-point unit (8087)
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37
The IBM-AT
Intel 80286
16 MB addressable RAM
Protected memory
several times faster than 8086
introduced IDE bus architecture
80287 floating point unit
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38
Intel IA-32 Family

Intel386
4 GB addressable RAM, 32-bit registers,
paging (virtual memory)
Intel486
instruction pipelining
Pentium
superscalar, 32-bit address bus, 64-bit
internal data path
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Intel P6 Family
Pentium Pro
advanced optimization techniques in microcode
Pentium II
MMX (multimedia) instruction set
Pentium III
SIMD (streaming extensions) instructions
Pentium 4 and Xeon

Intel NetBurst micro-architecture, tuned for
multimedia
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CISC and RISC

CISC complex instruction set
large instruction set
high-level operations
High-level language compilers would have less work
requires microcode interpreter
Complex instructions require a long time for the
processor to decode and execute
examples: Intel 80x86 family
RISC reduced instruction set
simple, atomic instructions
small instruction set
directly executed by hardware
examples:
ARM (Advanced RISC Machines)
DEC Alpha (now Compaq)
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Chapter 2 Outline: What's Next

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42

2.3.1 Real-address mode
2.3.2 Calculating linear addresses
2.3.3 Protected mode
2.3.4 Multi-segment model
2.3.5 Paging
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43
IA-32 Memory Management

Real-address mode
Processor can run only one program at a time
Each program can address up to 1MB
1 MB RAM maximum addressable

(00000~FFFFFh)
Application programs can access any area of memory

Single tasking
Supported by MS-DOS operating system
Protected mode
Processor can run multiple program at the same time with
each process a total of 4GB memory
MS-Windows and Linux
Virtual-8086 mode
Simulate an 80x86 running in real-address mode while in
protected mode
Command windows in MS-Windows
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44
Real-Address Mode
Real-address mode can address up to 1MB memory

(20-bit address)
However, the original 8086 processor had only 16-bit

registers, which can not directly represent a 20-bit address
Solution: segmented memory addressing
Memory is divided into 64KB (16-bit address) units called

segment
Segment-offset address: use two 16-bit numbers to calculate
20-bit address
A 16-bit segment value stored in segment register
A 16-bit offset value
Thus, absolute (linear) address is a combination of a 16-bit

segment value added to a 16-bit offset
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45
Segmented Memory Map, Real-address Mode
F0000
E0000
8000:FFFF
D0000
C0000
one segment
B0000
linear addresses
A0000
90000
80000
70000
60000
8000:0250
50000
0250
40000
30000
8000:0000
20000
10000
seg
00000
ofs
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46
Calculating Linear Addresses

Given a segment address, multiply it by 16 (add a
hexadecimal zero), and add it to the offset
Example: convert 08F1:0100 to a linear address
Adjusted Segment value: 0 8 F 1 0
Add the offset:
0 1 0 0
Linear address:
0 9 0 1 0
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47
Your turn . . .
What linear address corresponds to the segment/offset
address 028F:0030?
028F0 + 0030 = 02920
Always use hexadecimal notation for addresses.
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48
Your turn . . .
What segment addresses correspond to the linear address
28F30h?
Many different segment-offset addresses can produce the

linear address 28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .
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Protected Mode (1 of 2)
4 GB addressable RAM
(00000000 to FFFFFFFFh)
Each program assigned a memory partition which

is protected from other programs
Described by segment descriptor tables
Designed for multitasking

Supported by Linux & MS-Windows
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50
Protected Mode (2 of 2)
Program structure
code, data, and stack areas
CS, DS, SS segment descriptors
global descriptor table (GDT)
Has two memory model

Flat segmentation model
Multi-segment model
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51
Flat Segmentation Model

All segments are mapped to the entire 32-bit physical
address space of the computer.
At least two segments: one for program code and one
for data
Each segment is defined by a segment descriptor,

a 64-bit value stored in a table known as the global
descriptor table (GDT)
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Multi-Segment Model
Each program has a local descriptor table (LDT)
Holds descriptor for each segment used by the program
RAM
L o c a l D e s c rip to r T a b le
26000
base
lim it
00026000
0010
00008000
000A
00003000
0002
access
8000
3000
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53
Paging
Supported directly by the CPU
A segment is further divided into 4096-byte (4KB)
blocks of memory called pages
Allow the memory used by programs can be larger
than the computer
s actual memory
Virtual memory v.s. physical memory
Part of running program is in memory, part is on disk
Virtual memory manager (VMM) OS utility that

manages the loading and unloading of pages
Page fault issued by CPU when a page must be
loaded from disk
Page in: bring a requested page into memory
Page out: evict an unused page to the disk
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54

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Examples
55

2.4.1 Motherboard
2.4.2 Video output
2.4.3 Memory
2.4.4 Input-output ports
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56
2.4.1 Motherboard
CPU socket
External cache memory slots
Main memory slots
BIOS chips
Sound synthesizer chip (optional)
Video controller chip (optional)
IDE, parallel, serial, USB, video, keyboard, joystick,
network, and mouse connectors
PCI bus connectors (expansion cards)
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Examples
57
Intel D850MD Motherboard

Video
mouse, keyboard,
parallel, serial, and USB
connectors
Audio chip
PCI slots
memory controller hub
Pentium 4 socket
AGP slot
dynamic RAM
Firmware hub
I/O Controller
Speaker
Battery
Power connector
Diskette connector
Source: Intel Desktop Board D850MD/D850MV Technical Product

Specification
IDE drive connectors

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2.4.2 Video Output

Video controller
on motherboard, or on expansion card
AGP (accelerated graphics port technology)*
Video memory (VRAM)

Video CRT Display
uses raster scanning
horizontal retrace
vertical retrace
Direct digital LCD monitors

no raster scanning required
* This link may change over time.

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Examples
59
Sample Video Controller (ATI Corp.)

128-bit 3D graphics
performance powered by
RAGE 128 PRO
3D graphics performance
Intelligent TV-Tuner with
Digital VCR
TV-ON-DEMAND
Interactive Program Guide
Still image and MPEG-2 motion
video capture
Video editing
Hardware DVD video playback
Video output to TV or VCR
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Examples
60
2.4.3 Memory
ROM
read-only memory
EPROM
erasable programmable read-only memory
Dynamic RAM (DRAM)
inexpensive; must be refreshed constantly
Static RAM (SRAM)
expensive; used for cache memory; no refresh required
Video RAM (VRAM)
dual ported; optimized for constant video refresh
CMOS RAM
complimentary metal-oxide semiconductor
system setup information
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Examples
61
2.4.4 Input-Output Ports and Device Interfaces

USB (universal serial bus)
intelligent high-speed connection to devices
up to 12 megabits/second
USB hub connects multiple devices
enumeration: computer queries devices
supports hot connections
Parallel
short cable, high speed
common for printers
bidirectional, parallel data transfer
Intel 8255 controller chip
Web site
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62
2.4.4 Input-Output Ports and Device Interfaces

(cont)
Serial
RS-232 serial port
one bit at a time
uses long cables and modems
16550 UART (universal asynchronous receiver
transmitter)
programmable in assembly language
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63

Web site
Examples
64
2.5.1 Levels of Input-Output

Level 3: Call a library function (C++, Java)
easy to do; abstracted from hardware; details hidden
slowest performance
Level 2: Call an operating system function
specific to one OS; device-independent
E.g., writing entire strings to files, reading string from the
keyboard, allocating blocks of memory for application programs
medium performance
Level 1: Call a BIOS (basic input-output system) function
may produce different results on different systems
knowledge of hardware required
usually good performance
Level 0: Communicate directly with the hardware
May not be allowed by some operating systems
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65
Displaying a String of Characters

When a HLL program displays a string of
characters, the following steps take place:
1. Application program writes the string to
standard output.
2. The library function calls OS, passing a
string pointer.
3. OS passes the ASCII code and color of
each character to BIOS. OS also calls
BIOS function to control the cursor.
4. BIOS maps each character to a particular
system font and sends it to a hardware
port attached to the video controller card.
5. The video controller card generates
hardware signals to the video display.
Web site
Application Program
Level 3
OS Function
Level 2
BIOS Function
Level 1
Hardware
Level 0
Examples
66
ASM Programming levels

ASM programs can perform input-output at
each of the following levels:
ASM Program
OS Function
Level 2
BIOS Function
Level 1
Hardware
Level 0
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67
Playing a WAV File

At the OS level, you do not have to know what type of
device was installed and the card
s features
At the BIOS level, you would query the sound card and
find out whether it belongs to a certain class of sound
cards
At the hardware level, you would fine-tune the program
for certain brands of audio cards, to take advantage of
each card
s special features
Not all operating system permit user programs to directly
access system hardware
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Examples
68
Tradeoff
Tradeoff
Control (efficiency) v.s. portability
However, some OSs, like Windows and Linux, do not
permit user programs to directly access system
hardware
Web site
Examples
69
Summary
Central Processing Unit (CPU)
Arithmetic Logic Unit (ALU)
Instruction execution cycle
Multitasking
Floating Point Unit (FPU)
Complex Instruction Set
Real mode and Protected mode
Motherboard components
Memory types
Input/Output and access levels
Web site
Examples
70

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Assembly Language for Intel-Based

Computers, 5th Edition

Chapter 2: IA-32 Processor

Slides prepared by the author

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.1 General Concepts

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.1.1 Basic Microcomputer Design

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Basic Microcomputer Design (Cont.)

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Synchronous operation: need a clock

Asynchronous operation: does not require a system

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.1.2 Instruction Execution Cycle

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.1.2 Instruction Execution Cycle (cont.)

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Instruction Execution Cycle (Cont.)

Example of a nonpipelined processor.

For k states and n instructions, the number of required cycles is:

For k states and n instructions, the number of required cycles is:

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Wasted Cycles (pipelined)

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

For k states and n instructions, the number of required cycles is: k + n

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.1.3 Reading from Memory

The steps are:

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Cache hit: when data to be read is already in cache

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

How a Program Runs

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

How a Program Runs (Cont.)

The process runs by itself

OS can assign varying priorities to tasks

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Chapter 2: What's Next

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.2 IA-32 Processor Architecture

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.2.1 Modes of Operation

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Modes of Operation (cont.)

Implemented by computer manufactures

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

2.2.2 Basic Execution Environment

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Real-address and Virtual-8086 modes

Protected mode while running program in Virtual8086 mode

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

16-bit Segment Registers

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Use 8-bit name, 16-bit name, or 32-bit name

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Accessing Parts of Registers

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Index and Base Registers

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Some Specialized Register Uses (1 of 3)