FUTURE OF DIGITAL

CH13

THE RACE FOR SUPERCOMPUTING POWER

World Fastest supercomputer

From China: 2.5petaflops/s

IBM Exascale Super computer

Project 2020

World Upcoming fastest supercomputer

Blue Gene /Q-Mira from IBM 10petaflops/s

INTEL CMOS Integrated Silicon

Nanophotonics Computer Chip
Project 2010

THE NEXT BIGGEST SUPERCOMPUTER POTENTIAL BREAKTHROUGH

Quantum Computer

In theory, quantum computers would be able to process infinite computations across

multiple "dimensions".
The quantum computer took a step closer to reality in January 2011 when Oxford
University physicists unveiled a successful test of a quantum chip.

ITRS Roadmap

FREQUENCY
10000

1000
Frequency (Mhz)

Core i7 (3.3GHz)

Doubles every
2 years
P4

100
486
10

8085

1
0.1
1970

8086 286

P6

Pentium proc

386

8080
8008
4004
1980

1990
Year

2000

2010

Lead Microprocessors frequency used to double every 2 years

Courtesy, Intel

CHIP POWER OF INTEL PROCESSORS

POWER DISSIPATION
100

Power (Watts)

P6
Pentium proc
10
8086 286
1
4004

8008

486
386

8085
8080

0.1
1971

1974

1978

1985

1992

2000

Year

Lead Microprocessors power continues to increase

Courtesy, Intel

POWER: MAJOR PROBLEM

100000

18KW
5KW
1.5KW
500W
Core i7
(130W)
Pentium proc

Power (Watts)

10000
1000
100

286
486
8086
10
386
8085
8080
8008
1 4004
0.1
1971

1974

1978 1985 1992

Year

2000 2004

2008

Power delivery and dissipation will be prohibitive

To maintain Moores Law
Courtesy, Intel

Active and Passive Components of

CMOS Power

DELAY VS. VT/VDD

Need to minimize VT with respect to VDD

TEM OF THIN GATE OXIDE

TUNNELING THROUGH SiO2

Dealing with Short Channel Effects in bulk MOSFET

1.Increasing body doping concentration
2.Using halo implant

High doping density results in:

Lower carrier mobility;
high tunneling effect which increases off-state currents;
Larger depletion capacitors leading to high sub-threshold swing which
increases off-state currents;
Larger parasitic capacitance, Cgd, Cds.

Limit of Bulk CMOS Scaling

BULK CMOS SCALING LIMIT

To reduce short channel effects, we need to reduce Xdep (channel depletion
layer thickness), Xj ( Junction depletion width), tox (oxide layer thickness
under gate). Defining a figure of merit

For bulk MOSFET gate length

Lbulk >

AFTER SCALING PROCESS REACHES LIMITS ...

New ideas, technologies, and concepts will be required for continued

performance improvements.
Examples of new ideas, technologies, and concepts:
Silicon on insulator (S0I) technology
Depleted MOSFETS and FinFETS
SiGe and SiC technology
3D integration
Optical interconnects
Nanowire transistors

2010

2015

2020
9. 17

SOI CMOS

anneal

SIMOX PROCESS

Dealing with Short Channel Effects in

FULLY DEPLETED SILICON ON INSULATOR (FD-SOI)

Use ultra-thin film (tsi is small) as the conducting body, depletion layer is
confined in the film.( Xdep <= tsi).
Eliminate the junction parasitic capacitors.
Cuff off the leakage current path from drain to substrate.