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Stephan Henzler
Mixed-Signal-Electronics 2011/12
VDD
+2V
4V
0V
2V
-2V
0V
positive signals
AGND
negative signals
VSS
Even more complex supply concepts in use check for available voltages and definitions before starting with design
Stephan Henzler
Mixed-Signal-Electronics 2011/12
Stephan Henzler
Mixed-Signal-Electronics 2011/12
Condutance G
VSS
Stephan Henzler
VDD
Mixed-Signal-Electronics 2011/12
Chapter 2
Sample and Hold Circuits
Stephan Henzler
Mixed-Signal-Electronics 2011/12
Stephan Henzler
Mixed-Signal-Electronics 2011/12
Stephan Henzler
Mixed-Signal-Electronics 2011/12
Stephan Henzler
Mixed-Signal-Electronics 2011/12
Mixed-Signal-Electronics 2011/12
6. Clock jitter
7. Droop in hold mode: leakage currents discharge hold cap
8. Linearity
Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Sampling error:
Stephan Henzler
Mixed-Signal-Electronics 2011/12
12
Signal-to-Noise Ratio
maximum achievable SNR for given jitter
frequency dependent, i.e. the larger the bandwidth the higher
the clock requirements
Stephan Henzler
Mixed-Signal-Electronics 2011/12
13
Impact of Offset-Voltage
Vo
Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Remarks:
Sampling makes this a little bit more complicated as noise is a wide band signal so there is aliasing of replica
spectra. However, the noise power in the baseband is still kT/C
This is only a lower bound of noise power, buffers contribute also to overall noise power
Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Hold mode:
Input opamp is configured as voltage follower
fast settling when circuit returns to track mode
Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Stephan Henzler
Mixed-Signal-Electronics 2011/12
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Stephan Henzler
Mixed-Signal-Electronics 2011/12
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