LAB 5 MOSFET Amplifier Design

Background/Theory:

Our goal in this lab is simple. We would like to use a 2N7000 N-Channel Enhancement Mode FET to
design an amplifier using only information from the manufactures data sheet (that is, we want to
eliminate, to the extent possible, any effects of component tolerances introduced by the FET).

This is easier said than done. Unlike silicon BJTs, which have a known VBE that is approximately 0.7V
when forward biased, MOSFETs have a fairly wide tolerance for VTH (or VGS at any given drain current).
For the 2N7000, its data sheet specifies VGS(th) to be in the range of 0.8V to 3.0 volts with a typical value
being 2.1V. Lets suppose we want to bias our FET at 1mA drain current and we have a 12Vdc supply
available. There are two target values we need to select to accomplish this. Consider figure 1 below.
LTSpice does not include the 2N7000 so we will use a NDC7002N which is a part of the same family of
transistors. Remember to use the 2N7000 in your experiment.

Comment [HBC1]:
BJT: VBE= 0.7v
FET: VGS= 0.8-3v

Figure 1: MOSFET Biasing

The dominant two parameters under our control that effect Id (drain current) are VG and the value
for R1. The drain current can be given by:

Id = (VG- VGS) / R1
Looking at this equation, if VG is small compared to VGS, then Id will be a strong function of
VGS. This is clearly what we are trying to avoid. Lets plug in some numbers to illustrate this
point. Lets choose VG = 3.5V and R1 = 1K ohm. The bias point for a typical 2N7000 with VGS
= 2.1V then becomes:
Id = (3.5- 2.1) / 1000 = 1.4mA
Now if we plug in the tolerance extremes of VGS = 0.8V and VGS = 3.0V, we get Id equal to
2.7mA and 0.5mA respectively! This variance is over 5 to 1 and is unacceptable in most
applications.

Now lets consider choosing a higher value for VG. Assuming we are stuck with the +12V
supply shown in the figure, and knowing we want to leave some voltage drop from drain to
source for our output, lets choose 8V for VG, (Higher VG less sensitive Lower VG higher
sensitivity) and to keep the current in the same range, R1 = 5.6K. The typical case now
becomes:

Id = (8.0- 2.1) / 5600 = 1.1mA

plugging in the extremes again for VGS, we get Id equals 1.3mA and 0.9mA respectively. This is
still not perfect, but plus or minus 20% sure beats a ratio of 5 to 1. Remember: If VG is 1V then
it is below the VGS value and you will not see an output signal. If VG is 12V then your signal
will be clipping. Choose a correct DC bias point (8-10v).

Now lets better define some of the specifications for the amplifier we would like to build. Lets
shoot for:
Nominal ac Gain A = 10 @ 1KHz
Nominal quiescent current Id = 1mA (Q-point)
Minimum output voltage: 2Vpkpk
We will assume that the source driving our amplifier is 50 ohms (very small compared to our
input) and that the load to our amplifier is a very high impedance (i.e. the load will not affect our
gain)
Using the amplifier topology given below in figure 2, determine component values to meet the
requirements listed above. Follow the procedure outlined below.

Comment [P2]:

Figure 2: FET Amplifier Topology

Procedure:
1) Choose desired dc bias point for the FET source. (a voltage between 8 and 10
volts might be good)
2) Choose resistor values for R3 and R4 that will provide the proper bias voltage on
the FET gate. Make the resistor large. A FET has a very high input impedance
and it would be good to preserve this. This will also keep the input dc blocking
capacitor small keeping cost down.
3) Choose a value for R1. Aim for a bias current of 1mA in the FET.
4) Choose a value for R2 that will place the drain voltage half way between the
source voltage of the FET and the power supply voltage (+12V)
5) Choose a value for R5. For a FET that has a large forward transconductance
(Gm), the voltage gain can be approximated (exact for Gm=infinity) as the ratio of
the resistance seen by the drain, divided by the total resistance seen by the
source. For our circuit, this can be written:
Av = R2/(R1//R5)
6) Choose capacitor values that are insignificant in the circuit at a frequency of
1KHz.

Once you have finished the design, build the circuit on your whiteboard and test it at one of the
lab benches. Verify the circuit bias voltages, voltage gain and maximum output voltage swing
(without clipping). Record these values along with measured values for your resistors. Record
anything else you think is interesting or might be meaningful to explain in your report.
Remember to include the circuit from Figure 2 and all of the calculations from the Design
Procedure. Also, include the output signal images from LTSpice and from the lab experiment.
Finally, answer all of the questions below.

Notes:
-If V1 is too large clipping will occur
Choose a value lower than 1v
-Change the frequency to see if the gain changes. If
so, then capacitor problems
-There should be no oscillations between R5 and C1.
If so, then C1 is too small
-C3 should be smaller than C1 because the resistors
are large so the caps will be small
-What happens if C2 is added to the circuit?
-DC Bias is removed. Signal oscillates around 0v.
Comment [P3]: Avoid Clipping!

Comment [P4]: Voltage Divider is used to make

the gate have a voltage of 10 (2v under 12v).

= 12
= 10.1

Comment [P5]: Is=Id=1mA which is the current

through R1. Also, the voltage at VS is 8V because of
the 2.1v VGS typical drop and the 10v gate voltage.
Using Ohms Law R1=8k
Comment [P6]: between 12v supply and the
desired VD
-R2 and R3 are in parallel
-If R2 is too large clipping will occur

= 2

Comment [P7]: Use gain equation to find R5

Comment [P8]: Capacitors should be chosen
using Z=-j/2fc where Z = 16 because it would be
much smaller than R5. Remember that C3 should be
smaller than C1 because the resistors are large so the
caps would be small.
-Impedance needs to be smaller than the resistance
(R5)
-Change the frequency of V1 to see if the gain
changes. If so, caps have problems.
-If C1 is too low it will affect the gain of your
circuit. Check for oscillations between R5 and C1.
There should be none.

Evaluation and Review Questions:

1. Design procedure. How did you pick component values and why?

Comment [P9]: See Design Procedure notes

2. Effects of part tolerances. What range of bias voltages would you expect to see over the
range of resistor values and FET tolerances? How much will the gain be effected by the
resistor tolerances?

Comment [P10]:

3. Was your measured gain what you expected? If not, what assumptions did you make that
might explain the discrepancy?
Comment [P11]: Resistor tolerances, non-ideal
resistor values, higher or lower than expected bias
voltage.