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A 30 W Power Supply
Operating in QuasiSquare
Wave Resonant Mode
Prepared by: Christophe Basso
ON Semiconductor
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APPLICATION NOTE
INTRODUCTION
230
Ip
170
Lf
Ctot
110
50
10
1.69U
1.73U
1.77U
1.81U
1.85U
What is QuasiResonance?
The main problem with this technique lies in the very high
voltage generated at the switch opening. Most of the time,
these resonant offline designs require around 1.0 kV BVdss
MOSFETs whose price is clearly incompatible with high
volume markets. As a result, designers orientate their choice
toward another compromise called quasisquare wave
resonant power supplies.
AND8129/D
1
2
Lleak Ctot
Drain Voltage
Core is Reset
2
Vds is Minimum
Lp Ctot
Ip
Drain Current
is
Ip
(eq. 1) where Ctot lumps all capacitances
Ctot
Leak
Ctot
700
Rp
1:N
+
Lp
500
1
(Vout + Vf )
N
1
(Vout + Vf )
N
t=0
Rp
t
2Lp
Vout
Vin
300
Lleak
+
Vin
100
Drv
Ctot
tvalley
Vds
Multiple valleys
100
1.005M
1.015M
1.025M
1.035M
1.045M
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2
(eq. 3)
AND8129/D
When the transformer core resets, primary and
with:
1
2
We can see from Figure 4 that the drain is the seat of various
voltage drops when going down the ringing wave. These drops
are called valleys. If we manage to switch the MOSFET right
in the middle of these valleys, we ensure minimum turnon
losses, particularly those related to capacitive dissipation:
Pavgcap 1 Ctot Vds2 Fsw (eq. 7) 0. Thus, quasi
2
(eq. 4)
Rp
(eq. 5) (the damping factor), fprim =
2 Lp
Lp Ctot
(eq. 6)
Ipeak
S = N . (Vout + Vf) / Lp
S = Vin / Lp
ON
OFF
Ip = 0
1st Valley
0
Lp
Ip
VinDC
Lp
Np
(Vout Vf)
Ns
Tw 1 1
2 ft 2
2 fprim
fprim
(eq. 11)
(eq. 8)
Ip
tan
(eq. 9)
. This gives: Tw
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3
1
2 fprim
Lp Cp
(eq. 12)
AND8129/D
However, this result is valid only for low damping
coefficient, that is to say, et 1. Experience shows that
it is good enough for the vast majority of cases.
1
VinDC
Ton Toff Tw Ip Lp
1
2
Pin Pout
2 Lp Ip Fsw
from eq. 15, Ip
2 Pout
Lp Fsw
1
1 Tw Lp Ip2
VinDC
Pout 2
Vreflect
Ip
(eq. 14)
Tw = Lp Cp
(eq. 15)
(eq. 16)
(eq. 16a)
with:
Vreflect =
Lp Cp 1
Fsw
(Vout Vf)
1
Np
Ns
(eq. 13)
Np
[Vout Vf]
Ns
( Lp Vin Vreflect)
(eq. 17)
Fsw
(eq. 18)
(eq. 19)
2*105
6*104
1.5*105
f(Po)
f(VinDC)
5*104
4*104
1*105
3*104
5*104
2*104
1*104
100
150
200
250
300
350
400
VinDC
20
40
60
80
100
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4
AND8129/D
3.5
Ip(VinDC)
2.5
1.5
100
150
200
250
300
350
400
VinDC
d
(eq. 20) .
dt
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AND8129/D
20.0
10.0
0
10.0
20.0
N.Vin
20.0
10.0
N.Vin
Flyback operation
Forward operation
65mV
0
10.0
20.0
Leakage contribution
Watch out for possible restart!
Figure 12. Core Reset Detection Signal Coming From Either
a Forward or Flyback Winding
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AND8129/D
Demag
Rlimit
R
C
HV
Max Ip
Vcc
Aux
+
Low Line
Operation
Vout
Overpower
Max Ip
Drv
CS
High Line
Operation
1k
HV
Vcc
Aux
+
Demag
Rlimit
Vout
R
C
Drv
CS
Rsense
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AND8129/D
Low Standby Power: If SMPS naturally exhibits a
Pout nominal = 30 W
Vout = 16.8 V
Universal input voltage = 90265 VAC
Vdc min 100 VDC (including losses and ripple)
Vdc max 370 VDC
Shortcircuit protection
Standby power less than 300 mW at noload
The design of a quasiresonant converter featuring low
standby power requires the understanding of several
parameters before calculating anything:
1. Do we need to ensure true Zero Voltage Switching
(ZVS) operation over a large operating input
range?
2. If we ensure high switching frequency at
maximum power and low mains, while it
minimizes the magnetics, the frequency foldback
will eventually take place at higher input voltages.
3. At what peak current level do we authorize the
frequency foldback to avoid acoustical noise in the
transformer?
Answer 1:
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8
AND8129/D
generate burst of pulses to drive the MOSFET. The
discontinuity associated with the burst sequence is more
favorable to trigger mechanical resonances compared to
evenly spaced pulses. Suppose that a 550 mA peak current
is offering the best value with your transformer. Since the
1205 folds back at 30% of the maximum primary current,
you will select a maximum peak current of 1.0 V/1.65 A or
an Rsense of 0.6 . Iterations using the dedicated Excel
spreadsheet will therefore help to select the right primary
inductance and turnsratio to reach good performance in
standby without making noise.
Lets now follow the below design steps to build our 30 W
QR SwitchMode Power Supply:
1. In our opinion, the very first element to dimension
is the primary to secondary turn ratio. In effect, it
will condition, among other parameters, a) the
drainsource stress of the MOSFET at its opening
b) the Peak Inverse Voltage (PIV) of the secondary
rectifier at the switch closing c) the area where the
supply operates in Zero Voltage Switching (ZVS).
As we have seen before, if we select an 800 V
MOSFET, we can select the turn ratio by (including
a 10% safety margin):
Np
max VinDC
(Vout Vf) 800 V10%
Ns
(eq. 22)
+
Vin
PULSE
Current
Reading
Ip max 2 Pout
1
Np
Ns
min VinDC
Np
Ns
(Vout Vf)
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AND8129/D
obviously one of the most sensitive parameters
which influences others. Increasing the reflected
voltages to keep a wider ZVS operating range has
a price on other numbers:
The switching frequency increases (reset voltage on
Lp is stronger)
The primary peak current and conduction losses are
improved (if Fsw goes up, the peak demand goes
low)
The secondary peak current and conduction losses
increase
The MOSFET undergoes a bigger stress at the
switch opening
MOSFET turnon losses can be really null (if ZVS
is achieved)
7. Final values will be obtained due to the
design spreadsheet available to download from
ON Semiconductor web site which includes
parasitic elements (such as the leakage inductance
and the Cds capacitor) and whose formulae are
described in AND8089. After we entered our
desired operating conditions, the below numbers
were extracted from the spreadsheet:
Lp = 1.2 mH
Lleak (measured) = 15 H
Np/Ns = 16.6
Ip max = 1.5 A, to include various tolerances
Rshunt = 2 x 1.2 in parallel
Creso = 1.5 nF/1.0 kV
Calculated frequency at nominal load and minimum
input voltage = 50 kHz (120 VDC and 30 W)
Calculated frequency at nominal load and
maximum input voltage = 87 kHz (370 VDC and
30 W)
Fsw min 2 Pout
Np
(VoutVf)Vin min
Ns
Vin min
2
Np
(VoutVf)
Ns
(eq. 23)
Lleak
Np
Vds max Vin Ns
(Vout Vf)2
Ip2
(eq. 24)
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AND8129/D
X4
XFMRAUX
RATIO_POW = 0.06
RATIO_AUX = 0.06
Rprim
0.5
Iout
+
X1
MBR20100
Icoil
VCoil
Resr1
60 m
Idiode
Lprim
1.2 mH
dem
R6
5.6 k
Cout1
2.2 mF
IC = 16
C6
330 p
Vout
Vout
Rload
9.4
Lleak
15 u
Vin
360
X2
Free Run DT
R1
22 k
dem
1
fb
Id
fb
Rled
1k
IReso
6
Free
Run
Vout
Feedback
3
4
Vdrain
Creso
1.5 n
C5
10 n
Rsense
0.5
X7
MOC8101
Figure 17. A Simplified FreeRunning Controller Eases the Simulation Setup and Increases Speed
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11
D4
BV = 15.6
AND8129/D
Figure 18.
Figure 19.
It becomes difficult to differentiate the simulation from the real world . . . Figure 18 is simulation,
Figure 19 is measured.
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12
AND8129/D
1 id
2 icoil
3 idiode
4 ireso
5 i(cout1)
plot1
id in amperes
1.20
1
800m
400m
0
Plot2
icoil in amperes
400m
1.20
800m
400m
0
Plot4
ireso in amperes
Plot3
idiode in amperes
400m
28.7
21.6
14.6
7.51
434m
1.00
600m
200m
200m
Plot5
i(cout1) in amperes
600m
30.0
20.0
10.0
0
10.0
2.01m
2.03m
2.05m
Time in Seconds
2.07m
2.09m
Figure 20. Typical Waveforms Obtained by a Spice Simulation of the QuasiResonant Converter
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D3, D5 = 1N4148
R32
6.8 k
Rclamp
T1
1000 F/25 V
C15/C16/C17
Ground
R21 3.3 k
R22
1k
R20 33
7
6
5
10
R14
3W
NCP1205
IC4
18 k
R17
C20
1 nF
C2
220
pF
R24
39 k
R2 1 k
Optional
Network
+ 47 F/
25 V
C22
M2
800 V/4 A
IC5
SFH61562
R25
1.2
R26
1.2
C18
18 k
6.8
nF
R23
IC6
TLV431
C23
2.2 nF
Y1 Type
R30
3.9 k
AND8129/D
1.5 nF/1 kV
C14
WYMAFKP1
1000 V
2 x 27 mH
CM L4
Schaffner
RN11408/02
Universal
Input
D5
C13 82 pF
R19
100 k
14
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220 F
C1
X2
R15 2.2 k
Optional Network
B1
2KBP08M
R16
1 Meg
Not
Wired
R1
00
Dclamp
13.5 V @ 2.5 A
+ 220 F/
25 V
C19
R31
6.8 k
Coilcraft
PCV210305
L3
10 H
D7 MBR20100
D3
Cclamp
C12
47 F/
400 V
Lp = 1.2 mH
1:0.06 (power)
1:0.06 (aux.)
AND8129/D
Demoboard Performance and Typical Waveforms
P4
P3
P2
P1
Figure 23. At high line and nominal power, the drain level is kept below
the MOSFET breakdown.
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AND8129/D
Figure 24. At high line, an output short circuit does not jeopardize the
MOSFETs life.
Figure 25. An output bangbang test (1 to 2.5 A) does not reveal any
instability. The spikes are related to the LC filter installed on the output.
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AND8129/D
Bill of Materials
All resistors are 1/4 W 5% SMD unless otherwise noted.
Part Value
Designator
Type
Manufacturer
Reference
Comments
00
R1
1.0 k
R2
10
R14
2.2 k
R15
18 k
R17
100 k
R19
33
R20
18 k
R23
1.2
R26
1.0 W
1.2
R25
1.0 W
3.3 k
R21
1.0 k
R22
39 k
R24
3.9 k
R30
6.8 k
R31
Through Holes
6.8 k
R32
Through Holes
220 nF
C1
Through Holes
220 pF
C2
47 F/400 V
C12
82 pF
C13
1.5 nF/1.0 kV
C14
1000 F/25 V
C15
Vertical
1000 F/25 V
C16
Vertical
1000 F/25 V
C17
Vertical
6.8 nF
C18
220 F/25 V
C19
1.0 nF
C20
47 F/25 V
C22
2.2 nF
C23
Roederstein
WY Series Y1
10 H
L3
Coilcraft
PCV210305
2 x 27 mH
L4
Schaffner
RN11408/0.2
Snapin
BRIDGE D8
BC Comp.
222205756479
Wima
1500FKP1
KBU8J
MBR20100
D7
ON Semiconductor
STP5NB80
M2
ST
NCP1205P
IC4
ON Semiconductor
SFH61562
IC5
Infineon
TLV431
IC6
ON Semiconductor
30 W Transformer
T1
Coilcraft
Z9508A
PulseEngineering
PF0137
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TO92
AND8129/D
Transformer Vendor Details
Coilcraft
1102 Silver Lake Road
Cary, Illinois 60013 USA
Tel.: (847) 6396400
Fax: (847) 6391469
Email: info@coilcraft.com
http://www.coilcraft.com
Pulse Engineering
Site dOrgelet
Zone industrielle
39270 ORGELET
Tel.: 33 (0)3 84 35 04 04
Fax: 33 (0)3 84 25 46 41
http://www.pulseeng.com/
Email: vpelletier@pulseeng.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
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AND8129/D