Questions

Sl No.

Marks

What are application specific processors ?

2 Marks

Write about the features of VLIW architecture.

2 Marks

Write about the memory hierarchy.

2 Marks

What do you mean by a state machine ?

2 Marks

Mention about the advantages of using automation in design technology.

2 Marks

Mention about the design metrics of an embedded system.

2 Marks

Write about the advantages of using pipelining..

2 Marks

Write about the cache impact on system performance.

2 Marks

Write about the models vs. languages.

2 Marks

10

What do you mean by logic synthesis?

2 Marks

11

Define general purpose processes and application specific processes

2 Marks

12

Mention about the memory heirarchy

2 Marks

13

Draw the structure of a basic state machine model

2 Marks

14

Define automation.

2 Marks

15

List the bus standards.

2 Marks

16

Mention the design metrics of an embedded system.

2 Marks

17

Enumerate the benefits of pipelining.

2 Marks

18

What do you mean by storage permanence ?

2 Marks

19

What is the need for text and graphics in process modeling ?

2 Marks

20

Mention any two new challenges posed by cores to processor providers and users.

2 Marks

21

What is VLIW architecture?

2 Marks

22

What is cross compiler?

2 Marks

23

What are the different cache replacement policies?

2 Marks

24

What is 'process suspend and resume' ?

2 Marks

25

Define automation and reuse

2 Marks

26

Explain about the design challenges faced in an embedded system.

5 Marks

27

Write about the sequential logic design.

5 Marks

28

Explain about the arbitration methods in detail.

5 Marks

29

Explam about the executable specification design of a digital camera

5 Marks

30

Write about the role of an appropriate model language.

5 Marks

31

Write about the parallel evolution of compilation and synthesis.

5 Marks

32

Explain about the working of Timers and counters.

5 Marks

33

Explain about the compilation/ synthesis mehanism in IC technology.

5 Marks

34

Explain about the memory management unit.

5 Marks

35

Write about the principle of operation involved in wireless communication.

5 Marks

36

Explain about the features of QNX.

5 Marks

37

Explain about FSM synthesis.

5 Marks

38

Write the principal of operation involved in full custom ASIC.

5 Marks

39

Explain about the working of debugging process.

5 Marks

40

Explain the working of DRAM.

5 Marks

41

Write about the state charts language.

5 Marks

42

Explain the various synthesis levels.

5 Marks

43

Explain the PSM model in detail.

5 Marks

44

Write a short nole on VLIW architecture.

5 Marks

45

Explain in detail about working of timers and counters.

5 Marks

46

Explain in detail about memory management unit.

5 Marks

47

Write about the informal functional and non-functional specifications of a simple digital camera.

5 Marks

48

Write about the synchronization methods of concurrent process model.

5 Marks

49

Explain in detail about multilevel logic minimization.

5 Marks

50

What are the different design metrics of embedded system?

5 Marks

51

Describe different cache mapping techniques.

5 Marks

52

Explain HCFSM.

5 Marks

53

Explain Gajski's Y-chart.

5 Marks

54

What is timer?

5 Marks

55

Explain Daisy chain arbitration

5 Marks

56

Explain in detail about the full custom NLSI and semi-custom ASIC technology.

10 Marks

57

Explain about the custom single purpose processor design and optimization.

10 Marks

58

Explain in detail about the replacement and write techniques used in cache memories

10 Marks

59

Explain the principles of operation involved in parallel and serial communication.

10 Marks

60

Explain about the FSM with datapath model FSMD .

10 Marks

61

Write in detail about the concurrent process model.

10 Marks

62

Explain about the register-transfer synthesis and behavioural synthesis.

10 Marks

63

Write about the intellectual property cores aud the new challenges posed by cores to processor provides and users. 10 Marks

64

Explain about the instruction set, program' and data memory space of VLIW architecture.

10 Marks

65

Explain in detail about the custom single purpose precess or design andeptimization.

10 Marks

66

Explain in detail about the cache mapping techniques.

10 Marks

67

Explain about Microprocessor interfacing in detail.

10 Marks

68

Explain in detail about the program state machine model (PSM).

10 Marks

69

Explain about the interprocess communication mechanism.

10 Marks

70

Explain about the two-level and multi-level logic minimization.

10 Marks

71

Write in detail about the intellectual property cores.

10 Marks

72

Expain in detail about the application specific processors.

10 Marks

73

Explain the working of semi-custom ASIC in detail.

10 Marks

74

Explain in detail about the memory mapping techniques

10 Marks

75

Explain the working of different types of memories.

10 Marks

76

Explain in detail about finite state machines.

10 Marks

77

Define inter process communication.Exolain its working.

10 Marks

78

write in detail about the hardware/software co-design.

10 Marks

79

Explain in detail about intellectual property cores in an embedded system.

10 Marks

80

Discuss in detail about optimizing design metric and common design metrics in designing an embedded system.

10 Marks

81

Explain in detail about the working of basic combinational and sequential logic design.

10 Marks

82

Discuss in detail about cache mapping techniques.

10 Marks

83

Explain about microprocessor interfacing in detail.

10 Marks

84

Explain in detail about program state machine model.

10 Marks

85

Discuss in detail about create, terminate, suspend and resume operations of a concurrentprocess model.

10 Marks

86

Explain in detail about the parallel evolution of compilation and synthesis.

10 Marks

87

Explain in detail about intellectual property cores.

10 Marks

88

Explain IC technology and design technology for embedded system design.

10 Marks

89

Design controller part and datapath part for a custom single purpose processor that computes GCD of two numbers. 10 Marks

90

Explain advanced RAM that can be used in embedded systems.

10 Marks

91

Explain interrupts in microprocessor interfacing of embedded system.

10 Marks

92

Describe three computation models commomnly used to describe embedded systems and/or their peripherals.

10 Marks

93

Descibe communication and synchronization among concurrent processes.

10 Marks

94

Describe synthesis techniques at different abstraction levels.

10 Marks

95

Describe intellectual property cores.

10 Marks