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25Q16
FEATURES
Program/Erase
Speed
-2048K-byte
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64/128K-byte
Low
Power Consumption
Software/Hardware
Write Protection
-16-Bit Customer ID
-Security Architecture
GENERAL DESCRIPTION
The 25Q16 (16M-bit) SPI flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS#
SO
VCC
HOLD#
Top View
WP#
SCLK
VSS
SI
8LEAD SOP/DIP
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
PIN DESCRIPTION
Pin Name
I/O
Description
CS#
SO (IO1)
I/O
WP# (IO2)
I/O
VSS
SI (IO0)
I/O
SCLK
HOLD# (IO3)
I/O
VCC
BLOCK DIAGRAM
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
DI(IO0)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Page Address
Latch/Counter
Flash
Memory
DO(IO1)
Byte Address
Latch/Counter
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
MEMORY ORGANIZATION
Each device has
2M
128/64/32K
4K
256
bytes
8K
512/256/128
16
pages
512
32/16/8
sectors
16/32/64
blocks
31
30
Sector
Address range
511
1FF000H
1FFFFFH
496
1F0000H
1F0FFFH
495
1EF000H
1EFFFFH
480
1E0000H
1E0FFFH
47
02F000H
02FFFFH
32
020000H
020FFFH
31
01F000H
01FFFFH
16
010000H
010FFFH
15
00F000H
00FFFFH
000000H
000FFFH
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
DEVICE OPERATION
SPI Mode
Standard SPI
The 25Q16 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The 25Q16 supports Dual SPI operation when using the Dual Output Fast Read and Dual I/O Fast Read (3BH and
BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard
SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The 25Q16 supports Quad SPI operation when using the Quad Output Fast Read, Quad I/O Fast Read, Quad I/O
Word Fast Read (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at four
times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins:
IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable
bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesnt stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK dont care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
Data Protection
The 25Q16 provide the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE)
-Block Erase (BE)
-Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1. 25Q16 Protected area size
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
NONE
NONE
NONE
NONE
31
1F0000H-1FFFFFH
64KB
Upper 1/32
30 to 31
1E0000H-1FFFFFH
128KB
Upper 1/16
28 to 31
1C0000H-1FFFFFH
256KB
Upper 1/8
24 to 31
180000H-1FFFFFH
512KB
Upper 1/4
16 to 31
100000H-1FFFFFH
1M
Upper 1/2
000000H-00FFFFH
64KB
Lower 1/32
0 to 1
000000H-01FFFFH
128KB
Lower 1/16
0 to 3
000000H-03FFFFH
256KB
Lower 1/8
0 to 7
000000H-07FFFFH
512KB
Lower 1/4
0 to 15
000000H-0FFFFFH
1M
Lower 1/2
0 to 31
000000H-1FFFFFH
2M
ALL
31
1FF000H-1FFFFFH
4KB
Top Block
31
1FE000H-1FFFFFH
8KB
Top Block
31
1FC000H-1FFFFFH
16KB
Top Block
31
1F8000H-1FFFFFH
32KB
Top Block
000000H-000FFFH
4KB
Bottom Block
000000H-001FFFH
8KB
Bottom Block
000000H-003FFFH
16KB
Bottom Block
000000H-007FFFH
32KB
Bottom Block
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
Status Register
S15-S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Reserved
QE
SRP1
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, BP0) bits are 0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1
SRP0
#WP
Status Register
Software Protected
Hardware Protected
Hardware Unprotected
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
WP#=0, the Status Register locked and can not be written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can
be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Table2. Commands
Byte 3
Byte 4
Command Name
Byte 1
Byte 2
Write Enable
Write Disable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
Fast Read(7)
Continuous Read Reset
Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Block Erase(128K)
Chip Erase
Program/Erase
Suspend
Program/Erase Resume
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
06H
04H
05H
35H
01H
03H
0BH
3BH
(S7-S0)
(S15-S8)
(S7-S0)
A23-A16
A23-A16
A23-A16
BBH
A23-A8(2)
6BH
A23-A16
EBH
A23-A0
M7-M0(4)
A23-A0
M7-M0(4)
dummy
E7H
FFH
02 H
20H
52H
D8H
D2H
C7/60 H
75H
7AH
B9H
ABH
Byte 5
Byte 6
n-Bytes
(continuous)
(continuous)
(S15-S8)
A15-A8
A15-A8
A15-A8
A7-A0
M7-M0(2)
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
(D7-D0)
dummy
dummy
(Next byte)
(D7-D0)
(D7-D0)(1)
(1)
A7-A0
(continuous)
(continuous)
(continuous)
(continuous)
dummy
(D7-D0)(3)
(continuous)
(5)
(D7-D0)(3)
(continuous)
dummy
(6)
(D7-D0)(3)
(continuous)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
dummy
dummy
dummy
(ID7-ID0)
ABH
Next byte
(continuous)
Uniform Sector
16Mbit Dual and Quad SPI Flash
Manufacturer/
Device ID
High Performance Mode
Read Identification
NOTE:
1. Dual Output data
25Q16
90H
dummy
dummy
00H
(M7-M0)
A3H
9FH
dummy
(M7-M0)
dummy
(ID15-ID8)
dummy
(ID7-ID0)
(ID7-ID0)
(continuous)
(continuous)
Table of ID Definitions:
Operation Code
M7-M0
ID15-ID8
ID7-ID0
9FH
C8
40
15
90H
C8
14
ABH
14
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
SCLK
Command
SI
06H
High-Z
SO
CS#
0
SCLK
Command
SI
04H
High-Z
SO
CS#
SCLK
SI
SO
9 10 11 12 13 14 15
Command
05H or 35H
High-Z
MSB
MSB
9
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
SCLK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
SI
Status Register in
01
MSB
SO
0 15 14 13 12 11 10 9
High-Z
CS#
0
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
SO
03
High-Z
24-bit address
23 22 21
MSB
MSB
10
Data Out1
4 3 2 1
Data Out2
0
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
23 22 21
0B
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO
Data Out1
5 4 3 2
7 6
MSB
Data Out2
7 6 5
MSB
CS#
0
9 10
28 29 30 31
SCLK
Command
SI
SO
24-bit address
23 22 21
3B
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI
SO
Data Out2
Data Out1
7 5 3 1 7 5 3 1
MSB
MSB
11
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
9 10
28 29 30 31
SCLK
Command
SI(IO0)
24-bit address
23 22 21
6B
SO(IO1)
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
12
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
Figure10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
1
SCLK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
SI(IO0)
BB
SO(IO1)
A23-16
A15-8
A7-0
CS#
SCLK
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
SO(IO1)
Byte1
Byte2
Byte3
Byte4
CS#
SCLK
9 10 11 12 13 14 15
A23-16
A15-8
A7-0
M7-0
CS#
SCLK
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI(IO0)
SO(IO1)
Byte1
Byte2
Byte3
13
Byte4
M7-0
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SO(IO1)
WP#(IO2)
HOLD#(IO3)
SCLK
Command
SI(IO0)
EB
Dummy
Byte1 Byte2
CS#
0
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
SCLK
14
9 10 11 12 13 14 15
Dummy
Byte1 Byte2
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SO(IO1)
WP#(IO2)
HOLD#(IO3)
SCLK
Command
SI(IO0)
E7
Figure15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)
CS#
0
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
SCLK
9 10 11 12 13 14 15
15
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
24-bit address
23 22 21
Data Byte 1
1
0 7
MSB
2078
2079
2077
2076
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
MSB
CS#
2075
02
2074
SI
SCLK
Data Byte 3
Data Byte 2
SI
7
MSB
0 7
MSB
MSB
16
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
SCLK
Command
SI
29 30 31
24 Bits Address
20
23 22
MSB
CS#
SCLK
SI
Command
52
29 30 31
24 Bits Address
23 22
MSB
17
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
SCLK
Command
SI
29 30 31
24 Bits Address
D8
23 22
MSB
CS#
SCLK
SI
Command
D2
29 30 31
24 Bits Address
23 22
MSB
18
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
SCLK
SI
Command
60 or C7
19
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
SCLK
tDP
Command
SI
B9
Stand-by mode
Release From Deep Power-Down Or High Performance Mode And Read Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be
used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic
identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the
CS# pin low, shifting the instruction code ABH and driving CS# high as shown in Figure23. Release from Power-Down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code ABH followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the GD25Q16
is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is
completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure23. Release Power-Down Or High Performance Mode Sequence Diagram
CS#
SCLK
SI
t RES1
Command
AB
Deep Power-down mode
High Performance Mode
20
Stand-by mode
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
SO
t RES2
3 Dummy Bytes
23 22
AB
MSB
High-Z
Device ID
5 4 3 2
MSB
CS#
0
9 10
28 29 30 31
SCLK
Command
SI
23 22 21
90
High-Z
SO
CS#
24-bit address
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO
7
MSB
Manufacturer ID
5 4 3 2 1
Device ID
0
MSB
21
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
9 10 11 12 13 14 15
Manufacturer ID
6 5 4 3 2 1
SCLK
SI
9F
SO
CS#
MSB
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
Capacity ID7-ID0
6 5 4 3 2 1
MSB
22
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
CS#
0
29 30 31
SCLK
Command
SI
A3
t RES2
3 Dummy Bytes
23 22
MSB
SO
High Performance Mode
CS#
0
SCLK
SI(IO0)
FF
SO(IO1)
Don`t Care
WP#(IO2)
Don`t Care
HOLD#(IO3)
Don`t Care
23
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
While the Erase/Program suspend cycle is in progress, the Read Status Register command may still be accessed
for checking the status of the WIP bit. The WIP bit is a 1 during the Erase/Program suspend cycle and becomes a 0
when the cycle is finished and the device is ready to accept read command. A power-off during the suspend period will
reset the device and release the suspend state. The command sequence is show in Figure29.
Figure29. Program/Erase Suspend Sequence Diagram
CS#
SCLK
tSUS
Command
SI
75H
High-Z
SO
CS#
SCLK
SI
Command
7AH
SO
Resume Erase/Program
24
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
POWER-ON TIMING
Vcc(max)
Program, Erase and Write command are ignored
Chip Selection is not allowed
Vcc(min)
tVSL
Reset
State
Read command
is allowed
Device is fully
accessible
VWI
tPUW
Time
Parameter
Min
Max
Unit
tVSL
10
us
tPUW
10
ms
VWI
2.5
Test Condition
Min
Units
150
10
Years
125
20
Years
-40 to 85
100K
Cycles
LATCH UP CHARACTERISTICS
Parameter
Min
Max
-1.0V
VCC+1.0V
-100mA
100mA
Value
Unit
-40 to 85
Storage Temperature
-55 to 125
200
mA
-0.5 to 4.0
-0.5 to 4.0
VCC
25
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
0.7VCC
0.2VCC
0.3VCC
0.5VCC
Parameter
Min
Tpy
Max
Unit
Conditions
CIN
Input Capacitance
pF
VIN=0V
COUT
Output Capacitance
pF
VOUT=0V
CL
Load Capacitance
30
pF
ns
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.5VCC
0V
4.0V
20ns
3.6V
-0.5V
26
20ns
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
DC CHARACTERISTIC
(T= -40~85, VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ
Max.
Unit.
ILI
ILO
ICC1
Standby Current
15
20
mA
13
18
mA
CS#=VCC,
VIN=VCC or VSS
ICC2
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 90MHz,
ICC3
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(*1,*2,*4 I/O)
ICC4
CS#=VCC
10
mA
ICC5
Operating Current(WRSR)
CS#=VCC
10
mA
ICC6
CS#=VCC
10
mA
ICC7
CS#=VCC
10
mA
I CC8
800
uA
VIL
-0.5
0.2VCC
VIH
0.7VCC
VCC+0.4
VOL
IOL =1.6mA
0.4
VOH
IOH =-100A
600
VCC-0.2
27
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
AC CHARACTERISTICS
(T= -40~85, VCC=2.7~3.6V, CL=30pf)
Symbol
Max.
Unit.
DC.
120
MHz
DC.
90
MHz
DC.
50
MHz
DC.
90
MHz
tCLH
3.5
ns
tCLL
3.5
ns
tCLCH
0.2
V/ns
tCHCL
0.2
V/ns
tSLCH
ns
tCHSH
ns
tSHCH
ns
tCHSL
ns
tSHSL
20
ns
tSHQZ
tCLQX
ns
tDVCH
ns
tCHDX
ns
tHLCH
ns
tHHCH
ns
tCHHL
ns
tCHHH
ns
tHLQZ
ns
tHHQX
ns
tCLQV
ns
tWHSL
20
ns
tSHWL
100
ns
tDP
fC
Parameter
Min.
Typ.
fC2
fR
tRES1
tRES2
tHPM
16
28
ns
0.1
0.1
0.1
0.2
us
Uniform Sector
16Mbit Dual and Quad SPI Flash
tSUS
25Q16
us
15
ms
tW
tPP
0.7
2.4
ms
tSE
150
750
ms
tBE
0.5/1.0/1.5
1.5/2.0/5s
tCE
20
50
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
SI
MSB
SO
High-Z
tCHCL
tCLCH
tCHDX
LSB
CS#
tCH
SCLK
tCLQV
tCLQX
tCLQV
tCL
tQLQH
tCLQX
SO
LSB
tQHQL
SI
Least significant address bit (LIB) in
Figure33. Hold Timing
CS#
SCLK
SO
tCHHL
tHLCH
tCHHH
tHLQZ
HOLD#
SI do not care during HOLD operation.
29
tHHCH
tHHQX
tSHQZ
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
PACKAGE INFORMATION
Package SOP8L 200MIL
E1
L
1
L1
4
C
D
A2
A1
Dimensions
Symbol
A1
A2
E1
Min
0.05
1.70
0.36
0.19
5.13
7.70
5.18
Nom
0.15
1.80
0.41
0.20
5.23
7.90
5.28
0.25
1.91
0.51
0.25
5.33
8.10
Min
0.002
0.067
0.014
0.007
0.202
Nom
0.006
0.071
0.016
0.008
0.010
0.075
0.020
0.010
Unit
mm
Max
Inch
Max
2.16
0.085
L1
0.50
1.21
0.62
0.65
1.31
0.74
5.38
0.80
1.41
0.88
0.303
0.204
0.020
0.048
0.024
0.206
0.311
0.208
0.026
0.052
0.029
0.210
0.319
0.212
0.031
0.056
0.035
30
1.27
0.050
Uniform Sector
16Mbit Dual and Quad SPI Flash
25Q16
REVISION HISTORY
Version No
Description
Date
1.0
Initial Release
Aug.17,2010
1.1
Update AC Characteristic
Aug.17,2010
31