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Enter Password.
Now screen looks like this
Now access the particular folder by using cd , ls and incase if you want to
create new file use mkdir.
After accessing the particular folder , type load_module cadenceold
And then type icfb &
Now screen looks as follows:
Introduction
1) What is ESD?
Electrostatic discharge (ESD) is the sudden discharge of static charge when two
differently charged surfaces come into contact. When these charged surfaces come
into contact with CMOS devices, a very large current flows in a short span of time.
These electrostatic charges can even create a potential difference of 8kv and
current over 13 A. This damages the CMOS devices.
3) ESD Testing.
To check the reliability and effectiveness of ESD protection circuits ESD
testing is conducted. Out of the few available models Human Body
Model(HBM) is widely used.
The HBM test consists of a charged capacitance of 100 pF that is
discharged through a 1.5k resistor, connected to the device under test
(DUT), resulting in a 150-ns double-exponential pulse. The standard level of
ESD protection is 2 kV and refers to the ability of the on-chip ESD protection
to conduct 1.34 A during an ESD event.
LNA Design:
Let us consider a simple cascade amplifier:
i x1
jw C gs
2 V x =i x jw L1 +
i x1
+ ( i + g V )jw Ls
jw C gs x m gs
Substitute eq 1 in eq 2.
We get,
V x =i xjw L1+
i x1
g mi x1
+ ix +
jw L s
jw C gs
jw C gs
Vx
g L
1
= jw L1+
+ jw Ls + m s
ix
jw C gs
C gs
Z =
g mL s
1
+ jw( L1 + Ls )+
C gs
jw C gs
And ,
g mLs
C gs = 50.
wR=
1
(L1 + Ls )C gs
Effective Circuit:
Effective Resistance =
LESD S
||
1
+ ( L 1+ LG ) S+WtL
+
C ESDS
C GSS
On solving we get,
Real part = 0.
Imaginary part = j*LESD*w
Under Assumption,
L1+LG > LESD
Reason for not choosing this is, real part becomes zero. Hence, we can never
achieve input matching by using the above ESD circuit.
Working:
As ESD event occurs, in case of +ve spike, peak spike voltage is much
greater than supply voltage. Hence, upper diode gets forward biased and all
the current is discharged through the upper diode.
In case of ve spike, lower diode gets forward biased and current discharges
through lower diode.
Type 2: In this, we place diodes at the gate of the MOSFET and away from
the RF input.
The schematic diagram of above ESD simulated in cadence is as follows:
The capacitor placed in front of the ESD circuit is MIM capacitor which can
withstand a potential difference of 75V and is a part of matching circuit.
This ESD also works in the same way mention for the above ESD.
Advantages:
Very easy to tune.
Provides efficient ESD isolation protection.