CHAPTER-2

Embedded Microcontrollers
Structure of a basic computer system:
Basics: Types of architectures
1) Princeton Architecture (Von Neumann)
No separate memory for program
code and data.

2) Harward Architecture
Two separate memory units for
both program code and data.
Both data and a program
instruction can be read at the same
time

2) Structure of CPU, Memory, I/O devices on a bus:

A computer consisting of five functionally independent main parts
1) Input 2) Output 3) Memory 4) ALU 5) Control Unit
Input Unit: Computer accepts encoded information through input unit. The standard input device is a keyboard.
Whenever a key is pressed, keyboard controller sends the code to CPU/Memory. Examples include Mouse,
Joystick, Tracker ball, Light pen, Digitizer, Scanner etc.
Output Unit: Computer after computation returns the computed results, error messages, etc. via output unit.
The standard output device is a video monitor, LCD/TFT monitor. Other output devices are printers, plotters etc.

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Memory unit: Its function is to store programs and data. It is basically two types
1. Primary memory
2. Secondary memory
1. Primary memory: - Is the one exclusively associated with the processor and operates at the electronics
speeds programs must be stored in this memory while they are being executed. The memory contains a large
number of semiconductors storage cells. Each cell is capable of storing one bit of information. These are
processed in a group of fixed site called word.
To provide easy access to a word in memory, a distinct address is associated with each word location.
Addresses are numbers that identify memory location.
Number of bits in each word is called word length of the computer. Programs must reside in the memory
during execution. Instructions and data can be written into the memory or read out under the control of
processor.
Memory in which any location can be reached in a short and fixed amount of time after
specifying its address is called random-access memory (RAM).
The time required to access one word in called memory access time. Memory which is only readable by
the user and contents of which cant be altered is called read only memory (ROM) it contains operating system.
Caches are the small fast RAM units, which are coupled with the processor and are aften contained on
the same IC chip to achieve high performance. Although primary storage is essential it tends to be expensive.
2 Secondary Memory: - Is used where large amounts of data & programs have to be stored, particularly
information that is accessed infrequently.
Examples: - Magnetic disks & tapes, optical disks (ie CD-ROMs), floppies etc.,
Arithmetic logic unit (ALU):Most of the computer operators are executed in ALU of the processor like addition, subtraction, division,
multiplication, etc. the operands are brought into the ALU from memory and stored in high speed storage
elements called register. Then according to the instructions the operation is performed in the required sequence.
The control and the ALU are may times faster than other devices connected to a computer system. This
enables a single processor to control a number of external devices such as key boards, displays, magnetic and
optical disks, sensors and other mechanical controllers.

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Control Unit: Control unit co-ordinates activities of all units by issuing control signals. Control signals issued
by control unit govern the data transfers and then appropriate operations take place. Control unit interprets or
decides the operation/action to be performed.
The operations of a computer can be summarized as follows:
1. A set of instructions called a program reside in the main memory of computer.
2. The CPU fetches those instructions sequentially one-by-one from the main memory, decodes them and
performs the specified operation on associated data operands in ALU.
3. Processed data and results will be displayed on an output unit.
4. All activities pertaining to processing and data movement inside the computer machine are governed by
control unit.
CPU Families Used in Microcontrollers:
8051 microcontroller:

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Basic I/O Devices:

Timers and Counters:
The 8051 has two counters/timers which can be used either as timer to generate a time delay or as counter to
count events happening outside the microcontroller. The 8051 has two timers: timer0 and timer1. They can be
used either as timers or as counters. Both timers are 16 bits wide. Since the 8051 has an 8-bit architecture, each
16-bit is accessed as two separate registers of low byte and high byte. First we shall discuss about Timer0
registers.
Timer0 registers is a 16 bits register and accessed as low byte and high byte. The low byte is referred as a TL0
and the high byte is referred as TH0. These registers can be accessed like any other registers.

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Timer1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and TH1.

TMOD (timer mode) Register: This is an 8-bit register which is used by both timers 0 and 1 to set the various
timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the upper 4 bits are set aside for
timer1. In each case, the lower 2 bits are used to set the timer mode and upper 2 bits to specify the operation.

In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting and stopping. Some timers
do this by software, some by hardware, and some have both software and hardware controls. The hardware way
of starting and stopping the timer by an external source is achieved by making GATE=1 in the TMOD register.
And if we change to GATE=0 then we do no need external hardware to start and stop the timers.
The second bit is C/T bit and is used to decide whether a timer is used as a time delay generator or an event
counter. If this bit is 0 then it is used as a timer and if it is 1 then it is used as a counter.
In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0 respectively. These are used to
select the timer mode.
M0
0
to

M1
0

Mode
0

Operating Mode
13-bit timer mode, 8-bit timer/counter THx and TLx as 5-bit
prescalar. A prescalar is an electronic counting circuit used
reduce a high frequency electrical signal to a lower

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frequency
timer clock
or may be
some value

by integer division. The prescalar takes the basic

frequency (which may be the CPU clock frequency
some higher or lower frequency) and divides it by
before feeding it to the timer

16-bit timer mode, 16-bit timer/counters THx and TLx are

cascaded; there are no prescalar.

M0
1

M1
0

Mode
2

Operating Mode
8-bit auto reload mode, 8-bit auto reload timer/counter; THx holds
a value which is to be reloaded into TLx each time it

Spilt timer mode.

overflows.
1

Mode 1- It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to be loaded into the timers
registers TL and TH. After TH and TL are loaded with a 16-bit initial value, the timer must be started. We can
do it by SETB TR0 for timer 0 and SETB TR1 for timer 1. After the timer is started. It starts count up until
it reaches its limit of FFFFH. When it rolls over from FFFF to 0000H, it sets high a flag bit called TF (timer
flag). This timer flag can be monitored. When this timer flag is raised, one option would be stop the timer with
the instructions CLR TR0 or CLR TR1 for timer 0 and timer 1 respectively. Again, it must be noted that each
timer flag TF0 for timer 0 and TF1 for timer1. After the timer reaches its limit and rolls over, in order to repeat
the process the registers TH and TL must be reloaded with the original value and TF must be reset to 0.
Mode0- Mode 0 is exactly same like mode 1 except that it is a 13-bit timer instead of 16-bit. The 13-bit counter
can hold values between 0000 to 1FFFH in TH-TL. Therefore, when the timer reaches its maximum of 1FFH, it
rolls over to 0000, and TF is raised.
Mode 2- It is an 8 bit timer that allows only values of 00 to FFH to be loaded into the timers register TH.
After TH is loaded with 8 bit value, the 8051 gives a copy of it to TL. Then the timer must be started. It is done
by the instruction SETB TR0 for timer 0 and SETB TR1 for timer1. This is like mode 1. After timer is
started, it starts to count up by incrementing the TL register. It counts up until it reaches its limit of FFH. When
it rolls over from FFH to 00. It sets high the TF (timer flag). If we are using timer 0, TF0 goes high; if using
TF1 then TF1 is raised. When Tl register rolls from FFH to 00 and TF is set to 1, TL is reloaded automatically
with the original value kept by the TH register. To repeat the process, we must simply clear TF and let it go
without any need by the programmer to reload the original value. This makes mode 2 auto reload, in contrast in
mode 1 in which programmer has to reload TH and TL.
Mode3- Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed to be in mode 0, 1 and
2 independently of similar mode for other timer. This is not true for mode 3; timers do not operate

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independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3 causes it to stop counting; the control
bit TR1 and the timer 1 flag TF1 are then used by timer0.
1) A/D and D/A Converters
Analog/digital (A/D) and digital/analog (D/A) converters (typically known as ADCs and DACs,
respectively) are often used to interface non digital devices to embedded systems. The design of A/D and D/A
converters themselves is beyond the scope of this book; we concentrate instead on the interface to the
microprocessor bus. Because A/D conversion requires more complex circuitry, it requires a somewhat more
complex interface. Analog/digital conversion requires sampling the analog input before converting it to digital
form. A control signal causes the A/D converter to take a sample and digitize it. There are several different types
of A/D converter circuits, some of which take a constant amount of time, while the conversion time of

others depends on the sampled value. Variable-time converters provide a done signal so that the microprocessor
knows when the value is ready. A typical A/D interface has, in addition to its analog inputs, two major digital
inputs. A data port allows A/D registers to be read and written, and a clock input tells when to start the next
conversion. D/A conversion is relatively simple, so the D/A converter interface generally includes only the data
value. The input value is continuously converted to analog form.
2) GPIO
A General Purpose Input/output (GPIO) is an interface available on most modern microcontrollers
(MCU) to provide an ease of access to the devices internal properties. Generally there are multiple GPIO pins
on a single MCU for the use of multiple interaction so simultaneous application. The pins can be programmed
as input, where data from some external source is being fed into the system to be manipulated at a desired time
and location. Output can also be performed on GPIOs, where formatted date can be transmitted efficiently to
outside devices, this provides a simple mechanism to program and retransmit data depending on user desires
through a single port interface. The pins are usually arranged into groups of 8 pins where signals can be sent or
received to and from other devices. In many applications, the GPIOs can be configured as interrupt lines for a
CPU to signal immediate processing of input lines. In many newer designs, they also have the ability to control
and use Direct Memory Access (DMA) to transfer blocks of data in a more efficient manner. Essentially all
ports can be tailored to fit specific design goals and provide reusability within applications.
POLLED I/O vs. INTERRUPT DRIVEN I/O:
Polled I/O: The process of periodically checking the status of an I/O device to determine the need to serve the
device.
In program controlled I/O, the data transfer is completely under the control of the microprocessor
program. This means that the data transfer takes place only when an I/O transfer instruction executed. In most
of the cases, it is necessary to check whether the device is ready for transfer of data or not. To check this,
microprocessor polls the status bit associated with I/O devices.
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Dis Adv: it can waste a lot of processor time because processors are so much faster than I/O devices.
Interrupt Driven I/O: An I/O scheme that employs interrupts to indicate to the processor that an I/O device
needs attention.
In interrupt driven I/O approach, when a peripheral is ready to transfer of data, it sends an interrupt
signal to the microprocessor. This indicates that the I/O data transfer is initiated by external I/O device. When
interrupted, the microprocessor stops the execution of the program and transfers the program control to an
interrupt service routine. This interrupt routine performs data transfer. After the data transfer , it returns control
to the main program at the point it was interrupted.
Vectored and Prioritized Interrupts:
Providing a practical interrupt system requires having more than a simple interrupt request line. Most
systems have more than one I/O device, so there must be some mechanism for allowing multiple devices to
interrupt. We also want to have flexibility in the locations of the interrupt handling routines, the addresses for
devices, and so on. There are two ways in which interrupts can be generalized to handle multiple devices and to
provide more flexible definitions for the associated hardware and software:
interrupt priorities allow the CPU to recognize some interrupts as more important than others, and
interrupt vectors allow the interrupting device to specify its handler.
Prioritized interrupts not only allow multiple devices to be connected to the interrupt line but also allow the
CPU to ignore less important interrupt requests while it handles more important requests. As shown in Figure
3.3, the CPU provides several different interrupt request signals, shown here as L1, L2, up to Ln.
Typically, the lower-numbered interrupt lines are given higher priority, so in this case, if devices 1, 2,and
n all requested interrupts simultaneously, 1s request would be acknowledged because it is connected to the
highest-priority interrupt line. Rather than provide a separate interrupt acknowledge line for each device, most
CPUs use a set of signals that provide the priority number of the winning interrupt in binary form (so that
interrupt level 7 requires 3 bits rather than 7). A device knows that its interrupt request was accepted by seeing
its own priority number on the interrupt acknowledge lines.

Vectored Interrupts:
Vectors provide flexibility in a different dimension, namely, the ability to define the interrupt handler that
should service a request from a device. Figure 3.5 shows the hardware structure required to support interrupt
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vectors. In addition to the interrupt request and acknowledge lines, additional interrupt vector lines run from the
devices to the CPU. After a devices request is acknowledged, it sends its interrupt vector over those lines to the
CPU. The CPU then uses the vector number as an index in a table stored in memory as shown in Figure 3.5.

The location referenced in the interrupt vector table by the vector number gives the address of the handler.
There are two important things to notice about the interrupt vector mechanism. First, the device, not the CPU,
stores its vector number.
In this way, a device can be given a new handler simply by changing the vector number it sends, without
modifying the system software. For example, vector numbers can be changed by programmable switches. The
second thing to notice is that there is no fixed relationship between vector numbers and interrupt handlers. The
interrupt vector table allows arbitrary relationships between devices and handlers. The vector mechanism
provides great flexibility in the coupling of hardware devices and the software routines that service them. Most
modern CPUs implement both prioritized and vectored interrupts. Priorities determine which device is serviced
first, and vectors determine what routine is used to service the interrupt.
DMA Transfer:
Standard bus transactions require the CPU to be in the middle of every read and write transaction.
However, there are certain types of data transfers in which the CPU does not need to be involved. For example,
a high-speed I/O device may want to transfer a block of data into memory. While it is possible to write a
program that alternately reads the device and writes to memory, it would be faster to eliminate the CPUs
involvement and let the device and memory communicate directly. This capability requires that some unit other
than the CPU be able to control operations on the bus.
Direct memory access (DMA) is a bus operation that allows reads and writes not controlled by the CPU. A
DMA transfer is controlled by a DMA controller, which requests control of the bus from the CPU. After gaining
control, the DMA controller performs read and write operations directly between devices and memory.

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Figure 4.9 shows the configuration of a bus with a DMA controller. The DMA requires the CPU to provide two
additional bus signals:
The bus request is an input to the CPU through which DMA controllers ask for ownership of the bus.
The bus grant signals that the bus has been granted to the DMA controller
A device that can initiate its own bus transfer is known as a bus master. Devices that do not have the
capability to be bus masters do not need to connect to a bus request and bus grant. The DMA controller uses
these two signals to gain control of the bus using a classic four-cycle handshake. The bus request is asserted by
the DMA controller when it wants to control the bus, and the bus grant is asserted by the CPU when the bus is
ready.
The CPU will finish all pending bus transactions before granting control of the bus to the DMA
controller. When it does grant control, it stops driving the other bus signals: R/W, address, and so on. Upon
becoming bus master, the DMA controller has control of all bus signals (except, of course, for bus request and
bus grant).
Once the DMA controller is bus master, it can perform reads and writes using the same bus protocol as
with any CPU-driven bus transaction. Memory and devices do not know whether a read or write is performed
by the CPU or by a DMA controller. After the transaction is finished, the DMA controller returns the bus to the
CPU by de-asserting the bus request, causing the CPU to de-assert the bus grant.
Memory Hierarchy and Cashes:

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(OR)
Caches
Caches are widely used to speed up memory system performance. Many microprocessor architectures include
caches as part of their definition. The cache speeds up average memory access time when properly used. It
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increases the variability of memory access timesaccesses in the cache will be fast, while access to locations
not cached will be slow. This variability in performance makes it especially important to understand how caches
work so that we can better understand how to predict cache performance and factor variabilitys into system
design.
A cache is a small, fast memory that holds copies of some of the contents of main memory. Because the
cache is fast, it provides higher-speed access for the CPU; but since it is small, not all requests can be satisfied
by the cache, forcing the system to wait for the slower main memory. Caching makes sense when the CPU is
using only a relatively small set of memory locations at any one time; the set of active locations is often called
the working set.
Figure 3.6 shows how the cache support reads in the memory system. A cache controller mediates
between the CPU and the memory system comprised of the main memory. The cache controller sends a memory
request to the cache and main memory. If the requested location is in the cache, the cache controller forwards
the locations contents to the CPU and aborts the main memory request; this condition is known as a cache hit.
If the location is not in the cache, the controller waits for the value from main memory and forwards it to the
CPU; this situation is known as a cache miss.

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