IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO.

6, JUNE 2009

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Dead-Time Elimination of PWM-Controlled

Inverter/Converter Without Separate Power Sources
for Current Polarity Detection Circuit
Yong-Kai Lin, Student Member, IEEE, and Yen-Shin Lai, Senior Member, IEEE

TABLE I
COMPARISON OF DIFFERENT METHODS

AbstractThis paper will present a dead-time elimination

scheme for a pulsewidth-modulation (PWM)-controlled inverter/
converter. The presented dead-time elimination scheme does not
require separated power supplies for freewheeling-current detection of high- and low-side power devices. The presented scheme includes the freewheeling-current polarity detection circuit and the
PWM control generator without dead time. It will be shown that
the presented scheme eliminates the dead time of PWM control
for inverter/converter and therefore dramatically improves output
voltage loss and current distortion. Experimental results derived
from a field-programmable-gate-array-based PWM-controlled inverter are shown to demonstrate the effectiveness.
Index TermsDead-time elimination, pulsewidth modulation
(PWM).

I. I NTRODUCTION

EAD time is used for pulsewidth-modulation (PWM)controlled inverter/converter control to avoid short
through of high-side and low-side power devices. The dead
time mainly depends upon characteristics of power devices
and gate drive circuit. The effects of dead time include output
voltage loss and current distortion [1]. These effects become
relevant as voltage is low and switching frequency is high.
Moreover, addition of dead time to a PWM-controlled inverter
also affects the common-mode voltage [2].
Several methods have been presented to deal with the
dead-time issue. These methods include dead-time compensation [3][11], dead-time elimination [12][15] and dead-time
minimization [16][19]. Most of the dead-time compensation
methods are developed based upon the knowledge of current
polarities. In order to determine the direction of current, an
accurate current sensor is required. However, the result is highly
affected by the harmonics around the zero-crossing points,
particularly when the current is small. Moreover, some of the
dead-time compensation methods [10], [11] highly rely upon
plant parameters.
For the dead-time minimization method, dead time is still
required when the current is around zero-crossing points in
which current polarity detection is difficult and not accurate.
Therefore, the dead-time effect cannot be completely removed
under this circumstance.
Manuscript received April 17, 2008; revised January 12, 2009. First published February 6, 2009; current version published June 3, 2009.
The authors are with National Taipei University of Technology, Taipei
10608, Taiwan (e-mail: t9319006@ntut.edu.tw; yslai@ntut.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2014305

In [12][15], current polarity is determined by detecting

the terminal voltages of the antiparallel diode of a power device. Therefore, the dead-time elimination method is developed
based upon the detection method. However, two power sources
are required for each inverter leg or half-bridge of converter. For
a three-phase inverter, four power sources for such detection
circuits are required.
Moreover, the conduction states of power antiparallel diode
are detected only at the instants of rising edge of chop on,
as shown in [15]. It may result in detection error due to
switching noise and current ripple in practice and therefore
cause commutation error.
More details of the comparisons are summarized in Table I.
There are three categories: 1) dead-time compensation [3][11];
2) dead-time elimination [13][15]; and 3) dead-time minimization [16][19]. For the dead-time minimization method,
dead time is required as current is smaller than a certain
value. Moreover, this current level depends upon the resolution
of the current sensor. This paper will present a dead-time
elimination scheme for PWM-controlled inverter/converter.
The presented dead-time elimination scheme does not require
separate power supplies for freewheeling-current detection of
high- and low-side power devices. Therefore, only one power
source is required for freewheeling-current polarity detection of
three-phase inverter/converter.
The presented scheme includes the freewheeling-current polarity detection circui and the PWM control generator without
dead time. Current polarity is detected regularly with a sampling frequency which is higher than the switching frequency
to reduce the detection error. Experimental results derived
from a field-programmable-gate-array (FPGA)-based PWMcontrolled inverter are shown to demonstrate the effectiveness.

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Fig. 1. Voltage distortion caused by dead time. (a) Inverter/converter leg.

(b) Voltage distortion caused by dead time.

Fig. 3. P-cell and N-cell of inverter/converter leg. (a) Inverter leg/half-bridge

of converter. (b) P cell. (c) N cell.

III. P ROPOSED D EAD -T IME E LIMINATION S CHEME

Fig. 2. Current distortion caused by dead time.

II. E FFECT OF D EAD T IME

Fig. 1(a) shows the circuit of an inverter leg or half-bridge
of converter. For the conventional PWM control method, the
chop signals (or PWM signals) for high- and low-side power
devices are with 180 phase shift. Due to the delay of drive
circuit and turn-off delay of power devices, these control signals
are modified by adding a dead time in each rising pulse, td ,
to give the control signals indicated by Chop A+ and Chop
A , as shown in Fig. 1(b). This additional dead time results
in output voltage distortion which is defined as the difference
between va,ideal and va,real , as shown in Fig. 1(b).
Therefore, the real output voltage is greater (smaller) than
its command as current is negative (positive). Fig. 2 shows the
phase voltage and current of the inverter output. As shown in
Fig. 2, the output voltage vo (t) is with distortion as compared
to that without dead time (see waveforms A and B). However,
waveforms A and B cross each other at points P1 and P2. The
output current io (t) is also distorted at these two zero-crossing
points, as shown in Fig. 2.

A. PWM Generator Without Dead Time

Fig. 3(a) shows the circuit of an inverter leg or half-bridge
of converter. As shown in Fig. 3(a), an antiparallel diode is
connected with a power device. As the power device is off
while the current conduction continues, the antiparallel diode of
its opposite power device provides the current path. Therefore,
there is no need to turn on the opposite power device during this
turn-off period. Once no switching occurs to its opposite power
device, dead time is no more needed.
For example, when power device A+ is turned off and the
current direction retains, D
a will provide the current path
when power device A+ is turned off. Similar facts occur to
power device A and diode D+
a . Therefore, power device

are
defined
as a P cell for positive
A+ and diode D
a
current control (current flowing into the load side), as shown
in Fig. 3(b). In addition, power device A and diode D+
a
are defined as N cell [as shown in Fig. 3(b)], which conducts
negative current.
Fig. 4 shows the PWM control without dead time. As shown
in Fig. 4(a), once current is positive, P-cell control is retained.
Meanwhile, there is no PWM control signal for N-cell control.

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Fig. 6. Previous detection circuit [15].

Fig. 4. PWM control based upon P cell and N cell. (a) P-cell control, iL > 0.
(b) N-cell control, iL < 0.

Fig. 7. Proposed detection circuit.

Fig. 5.

Furthermore, the modifications can be realized by a digital

controller. For inverter control, the chop signal is changed to a
PWM control signal. The PWM generator can be realized using
(1) and (2).

Signals for PWM generator.

Therefore, dead time is no longer required while guaranteeing

no short through between positive and negative dc links.
Similarly, when current is negative, a PWM control signal is
applied to N cell only. Since there is no switching in the power
device of P cell, dead time is no longer needed, and no short
through will occur.
Fig. 5 shows the relationship between the chop signals and
the control signals of converter without dead time. The control
signals can therefore be summarized as follows:
Chop A+ = chop sgn(iL )

Chop A = chop sgn(iL ).

(1)
(2)

As shown in (1) and (2), the required calculation is simple,

and only slight modifications to the PWM signal are required.

B. Freewheeling-Current Polarity Detection Circuit Without

Isolated Power
Fig. 6 shows the polarity detection of freewheeling current.
The detection circuit requires two separate power sources,
namely, Vcc1 and Vcc2 , as shown in Fig. 6. The required
number of separate power sources is increased up to four for a
three-phase inverter. These separate power sources increase the
difficulty for modularization of the detection circuit.
Fig. 7 shows the presented freewheeling-current polarity
detection circuit. As shown in Fig. 7, only one power source is
required for the detection circuit for both single- and multiphase
inverter/converter. This special feature provides the potential of
modularization of the detection circuit.
In Fig. 7, when iL > 0, the terminal voltage becomes negative during the switch-off period, as shown in Fig. 8(a).

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Fig. 10.

Experimental system.

current becomes negative, and the current polarity is changed.

The polarity change rule is therefore modified as follows. If
tk >

1
(1 D)ts
2

then iL,avg > 0, and there is no change of current polarity. If

Fig. 8. Terminal voltage and PWM control signals without dead time.
(a) iL > 0. (b) iL < 0.

Fig. 9. Load current with several crossing points around zero-current area.

Similarly, during the switch-off period, the terminal voltage

is positive and greater than the dc-link voltage when iL < 0,
as shown in Fig. 8(b). Therefore, the terminal voltage can
be used to reflect the polarity of freewheeling current. Once
the polarity of current is determined, the control signals of
converter/inverter can be generated by (1) and (2).

tk

1
(1 D)ts
2

then iL,avg 0, and the current polarity is changed, where tk =

time interval between chop off and zero-crossing point (k =
1, 2, 3, . . .).
The presented circuit for the dead-time elimination circuit and the method are indeed effective. More details about
the experimental results for confirmation will be shown in
Section IV.
ZVS can be achieved for the inverter with small inductance
load and proper dead time, as illustrated in [20], using class-D
amplifier as an example. In this case, the power device (e.g.,
high-side power device) is turned on as its antiparallel diode
(e.g., high-side power device) is conducting current.
In the presented paper, dead time is not required, and the
power device (e.g., high-side power device) is turned on only
when the antiparallel diode of its counterpart (low-side power
device) is conducting current. Therefore, the possibility for
ZVS seems dim.
IV. E XPERIMENTAL R ESULTS

C. Freewheeling-Current Polarity Detection for Current With

Multiple Zero-Crossing Points
Under some conditions, e.g., small inductor of load, the output current polarity changes very quickly in the zero-crossing
area. There may be a few zero-crossing points, as shown in
Fig. 9.
To deal with such ambiguous situation, the concept of average current is used as an assistance index for the judgment of
current polarity. Note that no real average value of load current
is calculated. Once the period between chop off and zerocrossing point is slightly greater than 0.5(1 D)ts , the average

Fig. 10 shows the experimental setup. As shown in Fig. 10, a

single-phase induction motor is used as the load. More details
of the specifications of induction motor are shown in the
Appendix. The proposed PWM generator without dead time is
realized using FPGA. The current polarity is detected by the
proposed detection circuit. As shown in Fig. 10, only one power
source is required for the proposed detection circuit.
Fig. 11 shows the flowchart of the PWM generator without
dead time. The P-cell control signal is generated as current is positive. Moreover, N cell is switched on and off
when current is negative. Fig. 12 shows the details of FPGA

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Fig. 11. Flowchart of the implementation.

Fig. 12.
scheme.

FPGA implementation of the proposed dead-time elimination

Fig. 13. Experimental results, Ch1 = iL , Ch2 = Chop A+ , Ch3 = Chop A ,

Ch4 = sgn(iL ).

Fig. 14. Measured current, modulation index = 0.3. (a) PWM control with
2-s dead time. (b) PWM control without dead time.

implementation of the proposed dead-time elimination method.

The polarity of freewheeling current is detected regularly with
a sampling frequency which is higher than the switching
frequency to reduce the detection error.
Fig. 13 shows the experimental results of current, PWM
signals, and the detected polarity. As shown in Fig. 13, the
proposed method can detect the polarity, and the PWM control
signals do not require any dead time. Since the dead time
for the presented method is eliminated, the current distortion
associated with dead time can be removed, as shown in Figs. 14
and 15, as modulation index = 0.3 and 0.9, respectively.
Comparing Fig. 14(a) with 14(b) for modulation index =
0.3, the proposed method indeed provides significant improvement to the current distortion caused by dead time. Similar
results can be derived as modulation index increases, as shown
in Fig. 15, for modulation index = 0.9.
Fig. 16 shows the measured load current with several crossing points around zero-current area. As shown in Fig. 16,

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Fig. 17.

Measured current THD.

the output current polarity changes very quickly in the zerocrossing area. There are a few zero-crossing points, as shown
in Fig. 16. Based upon the concept of average current, once the
period between chop off and zero-crossing point is slightly
greater than 0.5(1 D)ts , the average current becomes negative, and the current polarity is changed, as shown in Fig. 16.
Therefore, the presented circuit for the dead-time elimination
circuit and the method are indeed effective.
Fig. 17 shows the measured current total harmonic distortion
(THD) results of the proposed dead-time elimination PWM
method. The related current THD for the conventional PWM
method with dead time = 2 s is also included in Fig. 17 for
comparison. As shown in Fig. 17, the current THD for the proposed method is indeed significantly reduced, thus confirming
the advantages of the method.
V. C ONCLUSION

Fig. 15. Measured current, modulation index = 0.9. (a) PWM control with
2 s dead time. (b) PWM control without dead time.

The contributions of this paper include the following.

1) Propose a current polarity detection circuit which requires
one power source only for inverter/converter.
2) Present the PWM control method without dead time
based upon the proposed current polarity detection
circuit.
3) Confirm the effectiveness of the proposed detection circuit and PWM control without dead time.
The current distortion caused by dead time can be removed
by using the proposed method. The proposed detection circuit
can be easily incorporated into the inverter/converter hardware.
A PPENDIX
Specifications of induction motor: single phase, 60 Hz, four
poles, 110 V, 5 A, and 0.25 hp.
R EFERENCES

Fig. 16. Measured load current with several crossing points around zerocurrent area, Ch1: iL , Ch2: chop, Ch3: Dan , and Ch4: sgn(iL,avg ).

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Yong-Kai Lin (S09) received the B.S. and M.S. degrees in electrical engineering from National Taipei
University of Technology, Taipei, Taiwan, where he
is currently working toward the Ph.D. degree.
His research interests include FPGA design and
inverter control.

Yen-Shin Lai (M96SM02) received the M.S. degree in electronic engineering from National Taiwan
University of Science and Technology, Taipei,
Taiwan, and the Ph.D. degree in electronic engineering from the University of Bristol, Bristol, U.K.
In 1987, he joined the Department of Electrical
Engineering, National Taipei University of Technology, Taipei, as a Lecturer, where he became a Full
Professor in 1999 and was the Chairperson during
20032006 and is currently a Chair Professor. His research interests include design of control ICs, circuit
design of dc/dc converters, and inverter control.
Dr. Lai has been a recipient of several national and international awards,
including the John Hopkinson Premium for the session 19951996 from the
Institution of Electrical Engineers (IEE), the Technical Committee Prize Paper
Award from the Industrial Drives Committee of the IEEE Industry Applications
Society (IAS) for 2002, and the Best Presentation Award at IEEE IECON 2004.
He is a Committee Member of the IEEE IAS Industrial Drives, Industrial Power
Converter, and Appliance Industry Committees and an Associate Editor for the
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS.