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Computer Architecture
Lecture 12: Designing a Pipeline Processor
pipeline.1
PCWrCond
Zero
MemWr
IRWr
RegDst
ALUSelA
RegWr
32
PC
WrAdr
32
Din Dout
32
32
32
Rt 0
Rd
Mux
Ideal
Memory
Rb
busA
Reg File
Rw
busW busB 32
1 Mux 0
Imm 16
1
32
Extend
ExtOp
<< 2
0
1
32
32
2
3
32
MemtoReg
Zero
32
ALU
32
Rt
Ra
Target
32
Rs
Mux
RAdr
Mux
32
Instruction Reg
32
0
BrWr
Mux
IorD
PCSrc
ALU
Control
ALUOp
ALUSelB
pipeline.3
pipeline.4
Pipelining is Natural!
Laundry Example
Sequential Laundry
6 PM
T
a
s
k
10
11
12
2 AM
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
Time
O
r
d
e
r
C
D
pipeline.6
10
30 30 30 30 30 30 30
T
a
s
k
11
12
2 AM
Time
A
B
C
O
r
d
e
r
pipeline.7
Pipelining Lessons
6 PM
T
a
s
k
O
r
d
e
r
9
Time
30 30 30 30 30 30 30
C
D
pipeline.8
Why Pipeline?
Suppose we execute 100 instructions
Single Cycle Machine
45 ns/cycle x 1 CPI x 100 inst = 4500 ns
Multicycle Machine
10 ns/cycle x 4.6 CPI (due to inst mix) x 100 inst = 4600 ns
Ideal pipelined machine
10 ns/cycle x (1 CPI x 100 inst + 4 cycle drain) = 1040 ns
pipeline.9
Address
Data Memory
Reg Wr
Reg. Fetch
Clk
PC
Instr Decode /
Old Value
Clk-to-Q
New Value
Instruction Memory Access Time
New Value
Old Value
ALUctr
Old Value
ExtOp
Old Value
New Value
ALUSrc
Old Value
New Value
RegWr
Old Value
New Value
busB
Old Value
Delay through Extender & Mux
Old Value
New Value
ALU Delay
Address
Old Value
New Value
Data Memory Access Time
busW
Old Value
busA
New
pipeline.10
Load Ifetch
Cycle 3 Cycle 4
Reg/Dec
Exec
Cycle 5
Mem
Wr
pipeline.11
Cycle 3 Cycle 4
Cycle 5
Cycle 6
Cycle 7
Clock
1st lw Ifetch
Reg/Dec
2nd lw Ifetch
3rd lw
Exec
Mem
Wr
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
Wr
Exec
IFetch Dcd
Mem
WB
Exec
Mem
WB
Exec
Mem
WB
Exec
Mem
WB
Exec
Mem
WB
Exec
Mem
IFetch Dcd
IFetch Dcd
IFetch Dcd
Program Flow
IFetch Dcd
WB
pipeline.13
Cycle 2
Clk
Single Cycle Implementation:
Load
Store
Waste
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10
Clk
Multiple Cycle Implementation:
Load
Ifetch
Store
Reg
Exec
Mem
Wr
Ifetch
R-type
Reg
Exec
Mem
Ifetch
Pipeline Implementation:
Load Ifetch
Reg
Store Ifetch
Exec
Mem
Wr
Reg
Exec
Mem
R-type Ifetch
Reg
Exec
Wr
Mem
Wr
pipeline.14
Inst 3
Reg
Im
Reg
Dm
Reg
Dm
Im
Reg
Im
Reg
Reg
Reg
Dm
ALU
Inst 4
Im
Dm
ALU
Inst 2
Reg
ALU
Inst 1
Im
ALU
O
r
d
e
r
Inst 0
ALU
I
n
s
t
r.
Reg
Dm
Reg
pipeline.15
pipeline.16
Instr 2
Reg
Reg
Mem
Reg
Mem
Reg
Mem
Reg
Mem
Reg
Mem
Reg
Mem
Reg
ALU
Mem
Mem
ALU
Reg
ALU
Instr 1
Mem
ALU
O
r
d
e
r
Load
ALU
I
n
s
t
r.
Mem
Instr 3
Instr 4
Reg
Detection is easy in this case! (right half highlight means read, left half write)
pipeline.17
pipeline.18
Cycle 3 Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Clock
R-type Ifetch
R-type
Reg/Dec
Exec
Ifetch
Reg/Dec
Exec
Ifetch
Reg/Dec
Load
Wr
R-type Ifetch
Wr
Exec
Mem
Wr
Reg/Dec
Exec
Wr
R-type Ifetch
Reg/Dec
Exec
Wr
We have a problem:
Two instructions try to write to the register file at the same time!
pipeline.19
R-type Ifetch
Reg/Dec
Cycle 3 Cycle 4
Exec
Wr
pipeline.20
10
Important Observation
Each functional unit can only be used once per instruction
Each functional unit must be used at the same stage for all instructions:
Load uses Register Files Write Port during its 5th stage
Load
Ifetch
Reg/Dec
3
Exec
Mem
Wr
R-type uses Register Files Write Port during its 4th stage
1
R-type Ifetch
2
Reg/Dec
3
Exec
4
Wr
pipeline.21
Cycle 3 Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Clock
Ifetch
Load
Reg/Dec
Exec
Ifetch
Reg/Dec
R-type Ifetch
Wr
Exec
Mem
Reg/Dec
Exec
R-type Ifetch
Wr
Wr
Reg/Dec Pipeline
R-type Ifetch
Exec
Bubble Reg/Dec
Ifetch
Wr
Exec
Reg/Dec
Wr
Exec
Insert a bubble into the pipeline to prevent 2 writes at the same cycle
The control logic can be complex
No instruction is completed during Cycle 5:
The Effective CPI for load is >1
pipeline.22
11
R-type Ifetch
Cycle 1 Cycle 2
Reg/Dec
Exec
Mem
Wr
Cycle 3 Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Clock
R-type Ifetch
Reg/Dec
Mem
Ifetch
R-type
Load
Exec
Wr
Reg/Dec
Mem
Exec
Wr
Ifetch
Reg/Dec
Exec
Mem
Wr
Reg/Dec
Mem
Exec
Wr
Reg/Dec
Mem
Exec
R-type Ifetch
R-type Ifetch
Wr
pipeline.23
Store
Ifetch
Reg/Dec
Cycle 3 Cycle 4
Exec
Mem
Wr
pipeline.24
12
Beq
Ifetch
Reg/Dec
Cycle 3 Cycle 4
Exec
Mem
Wr
pipeline.25
A Pipelined Datapath
Clk
Ifetch
Reg/Dec
Exec
ExtOp
RegWr
Mem
ALUOp
Wr
Branch
1
0
PC
Ra
Rt
Rb
RFile
Rw Di
Rd
Exec
Unit
Zero
Data
Mem
RA Do
WA
Di
Mux
Rt
Imm16
busA
busB
Mem/Wr Register
Rs
ID/Ex Register
IUnit
IF/ID Register
PC+4
Imm16
Ex/Mem Register
PC+4
PC+4
RegDst
ALUSrc
MemWr
MemtoReg
pipeline.26
13
Reg/Dec
Exec
ExtOp
RegWr
Mem
ALUOp
Branch
1
0
Ra
Rb
RFile
Rw Di
Rt
Rd
Exec
Unit
Zero
Data
Mem
RA Do
WA
Di
Mux
Rt
Imm16
busA
busB
Mem/Wr Register
Rs
Ex/Mem Register
IUnit
I
PC+4
Imm16
ID/Ex Register
PC = 14
PC+4
PC+4
ALUSrc
RegDst
MemWr
MemtoReg
pipeline.27
Reg/Dec
1
0
Address
Instruction
Memory
Instruction
Adder
PC = 14
10
pipeline.28
14
Clk
Ifetch
Reg/Dec
Exec
ExtOp
RegWr
Mem
ALUOp
Branch
1
0
Imm16
Rt
Rb
RFile
Rw Di
Rd
Exec
Unit
Zero
Data
Mem
RA Do
WA
Di
Mux
IUnit
Rt
Imm16
busA
busB
Mem/Wr Register
Ra
Ex/Mem Register
Rs
PC+4
IF/ID:
PC+4
PC
PC+4
ALUSrc
RegDst
MemWr
MemtoReg
pipeline.29
Clk
Ifetch
Reg/Dec
RegWr
Exec
Mem
ALUOp=Add
ExtOp=1
Branch
1
0
Ra
Rt
Rd
Rb
RFile
Rw Di
Exec
Unit
0
1
RegDst=0
Zero
Data
Mem
RA Do
WA
Di
ALUSrc=1 MemWr
Mux
IUnit
I
Rt
Imm16
busA
busB
Mem/Wr Register
Rs
PC+4
Imm16
ID/Ex Register
IF/ID:
PC+4
PC
PC+4
MemtoReg
pipeline.30
15
Mem
Adder
32
32
busA
Zero
32
busB
0
Extender
16
Mux
32
imm16
ALU
ID/Ex Register
PC+4
Target
32
32
ALUctr
ALU
Control
ALUSrc=1
ExtOp=1
ALUout
<< 2
ALUOp=Add
pipeline.31
Clk
Ifetch
Reg/Dec
Exec
ExtOp
RegWr
Mem
ALUOp
Branch=0
1
0
Ra
Rt
Rb
RFile
Rw Di
Rd
Exec
Unit
Zero
Data
Mem
RA Do
WA
Di
RegDst
ALUSrc
MemWr=0
Mux
IUnit
I
Rt
Imm16
busA
busB
Ex/Mem Register
Rs
PC+4
Imm16
ID/Ex Register
IF/ID:
PC+4
PC
PC+4
MemtoReg
pipeline.32
16
Clk
Ifetch
Reg/Dec
Exec
ExtOp
RegWr=1
Mem
ALUOp
Wr
Branch
1
0
PC+4
Imm16
Rt
Rb
RFile
Rw Di
Rd
Exec
Unit
Zero
Data
Mem
RA Do
WA
Di
Mux
IUnit
Rt
Imm16
busA
busB
Mem/Wr Register
Ra
Ex/Mem Register
Rs
ID/Ex Register
IF/ID:
PC+4
PC
PC+4
ALUSrc
RegDst
MemWr
MemtoReg=1
pipeline.33
Reg/Dec
RegWr
Wr
Exec
Mem
ALUOp=Add
ExtOp=1
Branch
1
0
Ra
Rt
Rd
Rb
RFile
Rw Di
Exec
Unit
0
1
RegDst=0
Zero
Data
Mem
RA Do
WA
Di
ALUSrc=1 MemWr
Mux
IUnit
I
Rt
Imm16
busA
busB
Mem/Wr Register
Rs
PC+4
Imm16
ID/Ex Register
IF/ID:
PC+4
PC
PC+4
MemtoReg
pipeline.34
17
Pipeline Control
The Main Control generates the control signals during Reg/Dec
Control signals for Exec (ExtOp, ALUSrc, ...) are used 1 cycle later
Control signals for Mem (MemWr Branch) are used 2 cycles later
Control signals for Wr (MemtoReg MemWr) are used 3 cycles later
Reg/Dec
Exec
ExtOp
ALUSrc
ALUSrc
RegDst
MemWr
Branch
ALUOp
RegDst
MemtoReg
RegWr
MemWr
Branch
MemtoReg
Wr
Mem/Wr Register
Main
Control
ID/Ex Register
IF/ID Register
ALUOp
Ex/Mem Register
ExtOp
Mem
MemWr
Branch
MemtoReg
RegWr
RegWr
MemtoReg
RegWr
pipeline.35
Clk
RegAdr
WrAdr
RegWr
MemWr
RegWrs Clk-to-Q
MemWrs Clk-to-Q
RegAdrs Clk-to-Q
RegAdr
Data
Reg
File
WrAdrs Clk-to-Q
Ex/Mem
Mem/Wr
RegWr
MemWr
WrAdr
Data
Data
Memory
pipeline.36
18
Clock
Store Ifetch
Reg/Dec
Store Ifetch
Exec
Mem
Wr
Reg/Dec
Exec
Mem
Wr
Reg/Dec
Exec
Mem
Wr
Reg/Dec
Exec
Mem
R-type Ifetch
R-type Ifetch
Wr
pipeline.37
Clk
I_Addr
I_WrEn
C_WrEn
WrEn
WrEn
C_WrEn
I_WrEn
Address
I_Addr
Data
I_Data
Address
Reg File
or
Memory
Data
Clk
Reg File
or
Memory
pipeline.38
19
Cycle 3 Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Clock
0: Load Ifetch
Reg/Dec
Exec
Ifetch
Reg/Dec
4: R-type
8: Store Ifetch
Mem
Wr
Exec
Mem
Wr
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
End of
Cycle 4
End of
Cycle 5
End of
Cycle 6
Wr
End of
Cycle 7
End of Cycle 4: Loads Mem, R-types Exec, Stores Reg, Beqs Ifetch
End of Cycle 5: Loads Wr, R-types Mem, Stores Exec, Beqs Reg
End of Cycle 6: R-types Wr, Stores Mem, Beqs Exec
End of Cycle 7: Stores Wr, Beqs Mem
pipeline.39
4: R-types Exec
8: Stores Reg
8: Stores Reg
4: R-types Exec
ALUOp=R-type
ExtOp=x
0: Loads Mem
Branch=0
Clk
1
0
Ra
Rt
Rd
Rb
RFile
Rw Di
Exec
Unit
0
1
RegDst=1 ALUSrc=0
Zero
Clk
MemWr=0
Data
Mem
RA Do
WA
Di
Mux
Rt
Imm16
busA
busB
Rs
PC+4
Imm16
IUnit
PC = 16
PC+4
PC+4
pipeline.40
MemtoReg=x
20
8: Stores Exec
0: Loads Wr
16: Rs Ifet
4: R-types Mem
ALUOp=Add
ExtOp=1
RegWr=1
Branch=0
Clk
1
0
Ra
Rb
RFile
Rw Di
Rt
Rd
Exec
Unit
0
1
RegDst=x ALUSrc=1
pipeline.41
Zero
Data
Mem
RA Do
WA
Di
Clk
MemWr=0
Mux
Rt
Imm16
busA
busB
Rs
PC+4
IUnit
I
Imm16
IF/ID: Instruction @ 16
PC = 20
PC+4
PC+4
MemtoReg=1
4: R-types Wr
RegWr=1
8: Stores Mem
ALUOp=Sub
ExtOp=1
Branch=0
Clk
1
0
Ra
Rt
Rd
Rb
RFile
Rw Di
Exec
Unit
0
1
RegDst=x ALUSrc=0
Zero
Clk
MemWr=1
Data
Mem
RA Do
WA
Di
Mux
Rt
Imm16
busA
busB
Rs
PC+4
IUnit
I
Imm16
IF/ID: Instruction @ 20
PC = 24
PC+4
PC+4
MemtoReg=0
pipeline.42
21
8: Stores Wr
ALUOp=R-type
ExtOp=x
RegWr=0
Branch=1
Clk
1
0
Ra
Rt
Rb
RFile
Rw Di
Rd
Exec
Unit
0
1
RegDst=1 ALUSrc=0
Zero
Data
Mem
RA Do
WA
Di
Clk
MemWr=0
Mux
Rt
Imm16
busA
busB
Rs
PC+4
IUnit
I
Imm16
IF/ID: Instruction @ 24
PC = 1000
PC+4
PC+4
MemtoReg=x
pipeline.43
Cycle 6 Cycle 7
Cycle 8
Cycle 9
Cycle 10 Cycle 11
Clk
12: Beq Ifetch Reg/Dec Exec
(target is 1000)
16: R-type Ifetch Reg/Dec
20: R-type
Ifetch
24: R-type
Mem
Wr
Exec
Mem
Wr
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
1000: Target of Br
Wr
22
Cycle 3 Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Clock
I0: Load Ifetch
Plus 1
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
Wr
Ifetch
Reg/Dec
Exec
Mem
Plus 2
Plus 3
Plus 4
Wr
Summary
Disadvantages of the Single Cycle Processor
Long cycle time
Cycle time is too long for all instructions except the Load
Multiple Clock Cycle Processor:
Divide the instructions into smaller steps
Execute each step (instead of the entire instruction) in one cycle
Pipeline Processor:
Natural enhancement of the multiple clock cycle processor
Each functional unit can only be used once per instruction
If a instruction is going to use a functional unit:
- it must use it at the same stage as all other instructions
Pipeline Control:
- Each stages control signal depends ONLY on the instruction
that is currently in that stage
pipeline.46
23