University at SUNY Buffalo

Student of Engineering
Department of Electrical Engineering

Design and Simulation of Two-stage Op-Amp

Self Study

Instructor: Dr. Praveen Meduri

Buffalo, NY, USA

Prepared by
Jianfeng Sun
ID: 37068562
Electrical Engineering
12/08/2015

Contributions
This is a self-study report that based on knowledge from course EE 491.
The main goal of this experiment is to design and simulate the circuit of two-stage op-amp in
order to meet the requirements that the instructor has offered.
My task is to first design the circuit from the parameters of the TSMC025 model of the transistors
and the specifications by hand calculation then using the software of Cadence to simulate the
circuit in order to meet the requirements.
The relationship between this report and my knowledge from the course EE 491 is that in the EE
491 class, by using the information that I have learned of the circuits of the MOSFET such as the
single stage amplifier, current mirror, differential amplifier, current source and deep triode
resistors stand by MOSFET, etc. Then combined all of these parts to construct a two-stage opamp in order to satisfy the specifications. In other words, the knowledge that I have learned from
the EE 491 class is the fundamental towards to the analysis of the IC design.

Summary
The main purpose of the report to verification of the results either from the hand calculation or
from the simulation of the software Cadence to meet the specifications that given by the
instructor.
The major points covered in this reports are the graphs of voltage gain, GBW, phase margin, slew
rate, ICMR, and OVSR and using these result to check whether the specifications are meet or not.
The major conclusions in this report is that almost all of the value of the requirements are meet,
but for the ICMR and OVSR, the actual values are kind of with a little deviation, but they are still
correct.
The major recommendations in this report are the reference given by the instructors, textbooks
and online source.

Table of Contents
Contributions ................................................................................................................................... 2
Summary ......................................................................................................................................... 3
List of Figures ................................................................................................................................. 5
List of Tables ................................................................................................................................... 6
1
Introduction............................................................................................................................. 7
2
Results .................................................................................................................................... 8
2.1
Hand Calculation ............................................................................................................. 8
2.2
Circuit Schematic ............................................................................................................ 9
2.3
AC Analysis .................................................................................................................... 9
2.4
ICMR ............................................................................................................................. 10
2.5
OVSR ( Range of Vout ) ................................................................................................. 11
2.6
Slew Rate ....................................................................................................................... 12
2.7
Pdiss ................................................................................................................................. 13
2.8
MOSEK ......................................................................................................................... 13
Engineering Analysis .................................................................................................................... 16
Conclusion ..................................................................................................................................... 16
References ..................................................................................................................................... 16

List of Figures
Figure 1.1 - 1 Design specifications ................................................................................................ 7
Figure 2.2 - 1 Two stage amplifier circuit lay out ........................................................................... 9
Figure 2.3 - 1 Ac analysis of AV, margin phase and GB ................................................................ 9
Figure 2.4 - 1 Circuit used to calculate ICMR .............................................................................. 10
Figure 2.4 - 2 DC response of ICMR ............................................................................................ 10
Figure 2.5 - 1 Circuit used to calculate the range of output voltage .............................................. 11
Figure 2.5 - 2 DC response of range of output voltage ................................................................. 11
Figure 2.6 - 1 Circuit used to calculate slew rate .......................................................................... 12
Figure 2.6 - 2 Slew rate of two stage amplifier ............................................................................. 12
Figure 2.7 - 1 Pdiss of the two stage amplifier .............................................................................. 13

List of Tables
Table 1.1 - 1 Design specifications ................................................................................................. 7
Table 2.3 - 1 AC analysis of the circuit ........................................................................................... 9
Table 2.4 - 1 DC response of ICMR.............................................................................................. 10
Table 2.5 - 1 Value of OVSR ........................................................................................................ 11
Table 2.6 - 1 Value of Slew Rate .................................................................................................. 12
Table 2.7 - 1 Value of Pdiss............................................................................................................. 13
Table 3 - 1 Summary of simulation ............................................................................................... 16

Introduction

In this project, we used the TSMC025 model for transistors of NMOS and PMOS to build a two
stage op amp in order to meet the special design specifications as following:

Table 1.1 - 1 Design specifications

60o
>7500V/V
3.3V
0V
10MHz
>10V/us
0.4V to 2.9V
1V to 2V
<5mW
10pF

Phase margin
AV
VDD
VSS
GB
SR
OVSR
ICMR
Pdiss
CL

Figure 1.1 - 1 Design specifications

The circuit that I used is the classic and standard two stage amplifier that is widely known, there
are three current mirrors in figure 1, such as, Mb1 and Mb2, Mb1 and Mb3, M3 and M4. The
current flow through M1 and M2 equal to half of the drain current of Mb2, and if M3 and M4 has
the same aspect ratio, so that the same structure will make the voltages at VD3 and VD4 constant
under the condition of ICMR. Then, it offers the constant current and voltage to the second stage
amplifier, CM is the miller compensated capacitor. What we first to do is using the parameters of
the TSMC025 model to do the hand calculation and try the best to satisfies the specifications.
Secondly, entering those results into the devices of the circuit to simulate, if the specifications are
not met, then we have to change some of the parameters of the devices.

Results

2.1

Hand Calculation

2.2

Circuit Schematic

Figure 2.2 - 1 Two stage amplifier circuit lay out

2.3

AC Analysis

Figure 2.3 - 1 Ac analysis of AV, margin phase and GB

Table 2.3 - 1 AC analysis of the circuit

Specifications

Parameters
Simulation results
>7500 V/V (77.5 dB)
78.83 dB
AV
60o
60.28o
Margin phase
10MHz
10.01MHz
GB
It is obvious that all three values of parameters from simulation are very close to the expected
values. So that the results from simulation are matched with the specification values.

2.4

ICMR

Figure 2.4 - 1 Circuit used to calculate ICMR

Figure 2.4 - 2 DC response of ICMR

Parameter
ICMR

Table 2.4 - 1 DC response of ICMR

Specification
1V to 2V

Result from simulation

28.82mV to 2.6V

The highest value is very close to the requirement, I had try my best to increase the lowest value
of ICMR to approach 1V, but the most possible number that I can got is 28.8186 mV.

10

2.5

OVSR ( Range of Vout )

Figure 2.5 - 1 Circuit used to calculate the range of output voltage

Figure 2.5 - 2 DC response of range of output voltage

Parameter
OVSR

Table 2.5 - 1 Value of OVSR

Specification
0.4V to 2.9V

Result from simulation

3.65mV to 2.99V

Same as ICMR, the highest value of OVSR is satisfied, but the lower boundary is so hard to be
completed.
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2.6

Slew Rate

Figure 2.6 - 1 Circuit used to calculate slew rate

Figure 2.6 - 2 Slew rate of two stage amplifier

The slew rate is the average value of the two slopes (positive and negative) of the two lines.
Slope1: (2.2366-0.99665) V/ (1.1001-1.1802) us=-15.48 V/s
Slope2: (1.9798-0.69547) V/ (1.8648-1.7649) us= 12.86 V/s
Average slew rate: 14.17 V/s
Parameter
SR

Table 2.6 - 1 Value of Slew Rate

Specification
>10 V/s

Result from simulation

14.17 V/s

So that the result from simulation matches with the specification value for SR.
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2.7

Pdiss

Figure 2.7 - 1 Pdiss of the two stage amplifier

Table 2.7 - 1 Value of Pdiss

Parameters
Pdiss

Specification
<5 mW

Result from simulation

2.87 mW

So that the result from simulation matches with the specification value for Pdiss.

2.8

MOSEK
Extra: MOSEK (undergraduate)

For the two stage op amp, there are 19 parameters of devices totally.
1. All of the aspect ratio Wi, Li, where I is from 1 to 8 (16)
2. The resistor R, and compensated capacitor Cc (2)
3. Bias current (1)
(The following equations for optimization of two-stage op-amp by MOSEK tool are from my
researches, not developed by myself.)
Goal of minimization:

13

AV:

GB:

Slew rate:

Pdiss:

14

ICMR:

OVSR:

Size of transistors:

Phase margin:

15

Engineering Analysis
Table 3 - 1 Summary of simulation
Parameters
Phase margin
AV
GB
SR
OVSR
ICMR
Pdiss

Specifications
60o
>77.5 dB
10MHz
>10V/us
0.4V to 2.9V
1V to 2V
<5mW

Results
60.28o
78.83dB
10.01MHz
14.17 V/s

3.65mV to 2.99V
28.82mV to 2.6V
2.87 mW

We could see the comparison between the values of specifications and the results from simulation
are very close to each other, although for the OVSR and ICMR, there is a little deviation. Because
it is quite hard to control them after setting up values for satisfying the required values of Av, GB,
SR, phase margin, and Pdiss. However, as a whole, I am pretty sure that this project met the
requirements completely and achieved the goal of the learning from the class of EE 491.

Conclusion
From the project, by using the basic knowledge that we learned from the EE 491 class to analysis
the circuit of the two-state op-amp, the specifications are almost satisfied. By the reference
materials such as the examples and method of simulations from the book written by ALLEN, we
could design the amplifier with the simple design procedures. The goal of this project is to help us
increase the ability to use the simulation software such as Cadence and also improve the ability of
analysis of the circuit. For the compensating of the circuit, we use the miller effect, which is add
the capacitor of Cc. By observing the curves of its phase margin simulation, it is obvious that the
BW of the 3dB is quite small, around 836Hz. By using the compensated capacitor, the point of
the pole is very close to the original one. And in order to increase the BW of the -3dB point, one
should use the zero calibration to do the compensated. However, for the MOSEK which is used
for circuit optimization has not been completed properly.

References

[1]

[2]

K. N. Abhilash, S. Bose, and A. Gupta, "A high gain, high CMRR two-stage fully
differential amplifier using g<inf>m</inf>/I<inf>d</inf> technique for bio-medical
applications," in Microelectronics and Electronics (PrimeAsia), 2013 IEEE Asia Pacific
Conference on Postgraduate Research in, 2013, pp. 40-45.
H. Chengming, C. Degang, and R. Geiger, "A low-voltage compatible two-stage
amplifier with &ge;120 dB gain in standard digital CMOS," in Circuits and Systems,
2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, pp. I-353I-356 vol.1.
16

[3]

[4]

[5]

[6]
[7]

[8]

[9]

[10]

[11]

[12]

B. H. Kassiri and M. J. Deen, "Slew-rate enhancement for a single-ended low-power twostage amplifier," in Circuits and Systems (ISCAS), 2013 IEEE International Symposium
on, 2013, pp. 1829-1832.
A. Mesri, M. M. Pirbazari, K. Hadidi, and A. Khoei, "High gain two-stage amplifier with
positive capacitive feedback compensation," Circuits, Devices & Systems, IET, vol. 9, pp.
181-190, 2015.
T. Min and Z. Qianneng, "A two-stage amplifier with active miller compensation," in
Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International
Conference on, 2011, pp. 201-204.
N. A. Olsson and R. M. Jopson, "Two-stage high-gain optical amplifier," Lightwave
Technology, Journal of, vol. 7, pp. 791-793, 1989.
P. Osmann, J. Fuhrmann, K. Dufrene, J. Fritzin, J. Moreira, H. Pretl, et al., "Design of a
Fully Integrated Two-Stage Watt-Level Power Amplifier Using 28-nm CMOS
Technology," Microwave Theory and Techniques, IEEE Transactions on, vol. PP, pp. 112, 2015.
K. Po-Yu, K. Ting-Hao, and H. Kuo-Yen, "The standard design flow for two-stage
amplifier design," in Consumer Electronics - Taiwan (ICCE-TW), 2015 IEEE
International Conference on, 2015, pp. 458-459.
M. S. M. Taufik, A. N. Nordin, S. Khan, and A. A. Zainuddin, "Design of Two-Stage
CMOS amplifier for quartz crystal resonator," in Smart Instrumentation, Measurement
and Applications (ICSIMA), 2013 IEEE International Conference on, 2013, pp. 1-4.
P. Wang, C. Golkowski, Y. Hayashi, J. D. Ivers, J. A. Nation, and L. Schachter, "Study
of high power, two-stage, TWT X-band amplifier," in Plasma Science, 1999. ICOPS '99.
IEEE Conference Record - Abstracts. 1999 IEEE International Conference on, 1999, p.
245.
Q. Zhou, H. Li, X. Duan, and C. Yang, "A two-stage amplifier with the recycling folded
cascode input-stage and feedforward stage," in Cross Strait Quad-Regional Radio
Science and Wireless Technology Conference (CSQRWC), 2011, 2011, pp. 1557-1560.
Y. Zuschu, M. Pui-In, and R. P. Martins, "Two Stage Operational Amplifiers: Power and
Area Efficient Frequency Compensation for Driving a Wide Range of Capacitive Load,"
Circuits and Systems Magazine, IEEE, vol. 11, pp. 26-42, 2011.

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