1. Reset DA = 0 via KEY and investigate output of U7D.

Acknowledge BPSK output OCO

x DA x CA exhibits a phase change at every change in OCO logic value. Try other
values of DA, such as selecting the 10 Hz square wave at TEST_DATA SELECT switch.

5.4.1 Simulation Results

The following oscilloscope plots show early test results from several stages of the
DSSS TX Subsystem. All of these pictures have an input function signal of 4 MHz, just as was
depicted in the original design by Kasteloot. Notice that at this input, CA is 2 MHz and that each
stage does its job satisfactorily. With this data, the stages show that they can produce useable
signals at this higher frequency. This again proves that dropping to a slower frequency of CA
resulting 10 kHz should prove well within the operational limits of the circuit elements.

Simulation Results Figures:

Fig. 5.4.2: U1A + U2A – Divide-by-two stage
Fig. 5.4.3: I/O of Divide-by-1000 stage
Fig. 5.4.4: PN generated sequence OCO clocked by CA = 2 MHz
Fig. 5.4.5: Modulo-2 addition spreading stage – see that OCO is inverse of OCO x DA,
when DA = 1
Fig. 5.4.6: BPSK output signal at U7D pin 11, when DA = 0

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Fig. 5.4.2: U1A + U2A – Divide-by-two stage

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Fig. 5.4.3: I/O of Divide-by-1000 stage

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Fig. 5.4.4: PN generated sequence OCO clocked by CA = 2 MHz

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Fig. 5.4.5: Modulo-2 addition spreading stage – see that OCO is inverse of OCO x DA,

when DA = 1

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Fig. 5.4.6: BPSK output signal at U7D pin 11, when DA = 0

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 5.4.2 Observed and Measured Results
Refer to Fig. 3.3.5 for an oscilloscope printout comparison of BPSK signal OCO
x DA x CA to PN sequence OCO when DA =0. Notice that the phase changes correspond
directly to the OCO chip value.

5.1 DSSS Shift Registers Subsystem and DSSS Synchronization

Subsystem
Team member who designed this subsystem: Matt Elder
Team member who wrote this subsection: Matt Elder

The key element behind a direct-sequence spread spectrum system is the

synchronization of PN generator sequences at both the transmitter and the receiver. This
correlation between the transmitter and receiver PN shift-registers is the only means through
which to demodulate the data at the receiver. There are several methods known in literature to
accomplish PN generator synchronization, the final DSSS System uses the method of SR Latch
and logic triggering.

5.5.1 Theoretical Considerations

The key theoretical concepts needed to grasp these two subsystems’ operation are the
logic behind XOR, NOR, NAND, and inverter gates.

Fig. 5.5.1: XOR and NOR logic truth tables.

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 Fig. 5.5.2: NAND logic truth table.

Of particular importance is the NAND gate orientation seen as arrangement U16A

and U16B in DSSS Synchronization Subsystem. This orientation is known as an SR Latch and
its theoretical logic table is presented in Fig. 5.5.3.

Fig. 5.5.3: SR NAND latch truth table.

By placing S2 RESET PUSHBUTTON between Q’ and VCC, we can reset the SR

Latch to run the receiver PN generator U10 at 2 x CA to synchronize with U9 Shift-register fed
by the PN sequence OCO from DSSS TX Subsystem. When Q’ is high, the receiver PN
generator U10 is clocked at 2xCA while U9 receives OCO at a clock rate of CA. When the
cascaded logic gates U11 through U15 output a logic low at U8D pin 11, the LED D1 is
activated and the SR Latch output Q’ is locked into a value of logic low. When Q’ is logic low,
U10 PN generator is clocked at CA and U10 outputs synchronized PRBS, called Local
Controlled Oscillation (LCO), identical to U9’s PRBS output, called OCO or Original Controlled
Oscillation. At this point, LCO = OCO and DSSS Demodulation Subsystem can accurately
demodulate BPSK OCO x DA x CA to recover DA at the receiver.

If at any time synchronization between OCO and LCO is lost, the SR Latch can be
reset and U10 is double-speed clocked again with the simple press of S2 RESET
PUSHBUTTON.

5.5.2 Design Procedure

The DSSS Shift Registers Subsystem sees input from the DSSS TX Subsystem
into Shift-register U9. By comparing each of the seven flip-flop states within U9 and
U10, the phase correlation of the PN sequence at the U10 can be determined in relation to
the transmitted PN sequence. Both U9 and U10 have the same feedback logic and taps,
so each will produce the same code. However, if these codes do not match up in phase,
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 they cannot be used constructively to send accurate data. Below outlines the test
procedure used for both DSSS Shift Registers Subsystem and DSSS Synchronization
Subsystem to ensure accurate performance.

Procedure for initial DSSS Shift Registers Subsystem test

1. Build circuit in Fig. 3.2.6.

2. GND or VCC each of the seven output pins on U9 and U10 in the same order.
And acknowledge that a low logic level is received at U8D pin 11. If not, there is
an issue with the cascading logic circuit and it must be addressed before moving
on.

3. Acknowledge that the SR NAND latch is performing logically and test that after
reset Q’ stays logic high until LED illuminates, and U8D pin 11 go logic low.

4. Remove GNDs and VCC connections placed for testing in step 2, and check that
U9 and U10 are producing a similar frequency PRBS.

5. Acknowledge that the multiply-by-two stage U12 D and its cooresponding

Schmitt Trigger waveform shaper are taking in the 10 kHz CA and producing a
useable 20 kHz square wave of equal phase and voltage.

6. Test that bilateral switches U17A and U17B are not closed simultaneously and
that when U17A is closed, U16D’s inputs are (2 x CA). When U17A is open,
U17B must be closed, and U16D will see CA at its input.

7. Acknowledge that the SR NAND latch sets U17A and U17B open and closed
depending on the value of Q’.

8. Acknowledge that the two subsystems, in combination with DSSS TX Subsystem,

produce VAR_CLOCK as (2 x CA) when PN generators U9 and U10 are seeking
phase synchronization, and when it is achieved VAR_CLOCK is switched to CA
immediately. This process occurs when both PN generators U6, U9, and U10 are
all running and S2 RESET PUSHBUTTON SWITCH is pressed quickly. Once
VAR_CLOCK is CA in value, check the output of both U9 and U10 on an
oscilloscope to check that they are indeed synchronized.

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 5.5.3 Simulation Results
Testing to ensure each stage of the two subsystems was operational was at both CA =
2 MHz and CA = 10 kHz. Data from these tests shows the great difference a change in
frequency has on several parts of the circuit. In particular the multiply-by-two stage of U12D
and U18A,B,C saw great fluctuations in operation between the two CA frequencies. The
original design had provided suggested R and C values for U12D inputs but experimental results
showed differently. In Fig. 5.5.4 the I/O of U12D given suggested R = 3 kΩ and C = 50 pF.
After several attempts, a better combination of capacitance C= 22pF || 10 pF = 33 pF provided a
more satisfactory output at CA = 2 MHz in Fig. 5.5.6.

Similar tests were run for this U15D stage with the final 10 kHz CA. The results
shown in Fig. 5.5.7 proved the best (2 x CA) output at 10 kHz. The R value remained 3 kΩ but
the C value varied considerably to 0.033 uF.

The finished multiply-by-two stage, however, requires some more waveform shaping
to the signal produced by U12D. This wave shaping process is completed through the Schmitt
Trigger created through U18A,B,C. Consult Fig. 5.5.8 to see the final design I/O of the Schmitt
Trigger U18A,B,C. The values of R used within the Schmitt Trigger have been modified as well
to compensate for the slower frequency CA. The new values are 56 kΩ and 100 kΩ as shown in
the schematic of Fig. 3.2.7.

5.5.4 Observed and Measured Results

Finally, the end result of CA and (2 x CA) signals are produced. These signals are shown for
comparison in Figs. 5.5.9 and 5.5.10.

Observed Results Figures:

Fig. 5.5.4: U12D Multiply-by-two Stage w/ R = 3 kΩ, C = 50 pF, and CA = 2 MHz.

Fig. 5.5.5: U12D Multiply-by-two Stage w/ R = 3 kΩ, C = 33 pF, and CA = 2 MHz.

Fig. 5.5.6: U12D Multiply-by-two Stage w/ R = 3 kΩ, C = 0.033 uF, and CA = 10 kHz.

Fig. 5.5.7: Schmitt Trigger shaping 20 kHz (2 x CA).

Fig. 5.5.8: CA = 10 kHz produced at U10 pin 8 while “S2 RESET” Open.

Fig. 5.5.9: (2 x CA) = 20 kHz produced at U10 pin 8 while “S2 RESET” Closed.

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Fig. 5.5.4: U12D Multiply-by-two Stage w/ R = 3 kΩ, C = 50 pF, and CA = 2 MHz.

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Fig. 5.5.5: U12D Multiply-by-two Stage w/ R = 3 kΩ, C = 33 pF, and CA = 2 MHz.

84
Fig. 5.5.6: U12D Multiply-by-two Stage w/ R = 3 kΩ, C = 0.033 uF, and CA = 10 kHz.

85
Fig. 5.5.7: Schmitt Trigger shaping 20 kHz (2 x CA).

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Fig. 5.5.8: CA = 10 kHz produced at U10 pin 8 while “S2 RESET” Open.

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Fig. 5.5.9: (2 x CA) = 20 kHz produced at U10 pin 8 while “S2 RESET” Closed.

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 5.2DSSS Demodulation Subsystem
Team member who designed this subsystem: Matt Elder
Team member who wrote this subsection: Matt Elder

The true DSSS communication system challenge is synchronous demodulation of PN spread

data OCO x DA. All of the DSSS Subsystems up to the DSSS Demodulation Subsystem have
provided the means to acquire synchronization between OCO and LCO. Given an input BPSK
OCO x DA x CA and a receiver produced LCO x CA into a Balanced Modulator, recovery of
DA is the main priority.

5.6.1 Theoretical Considerations

The process behind recovery of DA from the modulated BPSK input signal OCO x DA x
CA is through the circuit construction of a Balanced Modulator. The theory behind the balanced
modulator/demodulator is simple. The inputs are taken into a doubly-balanced modulator
configuration, shown in Fig. 5.6.1, and the output is a translated version of the inputs. In the
DSSS Demodulation Subsystem case, OCO x DA x CA and LCO x CA are taken in as inputs.
When LCO and OCO are synchronized, the translated output would be [(2xOCO) x DA x
(2xCA)] and DA. With a simple LPF at the output, DA can be recovered easily.

Fig. 5.6.1 The Doubly-Balanced Mixer

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 5.6.2 Design Procedure
The design procedure for this subsystem is fairly simple as the main part
involved is biasing the Balanced Modulator U10 correctly for accurate
demodulation and recovery of DA.

Procedure for initial DSSS Demodulation Subsystem test

1. Build circuit in Fig. 3.2.8.

2. Ensure synchronization between LCO and OCO is established from previous

DSSS subsystems.

3. Ensure proper filtering at the collector output of Q1. Take several pictures of
waveforms as they traverse the low-pass filters and inverter ICs.

4. Match the recovered DA output with that of the input DA from DSSS TX
Subsystem.

5.6.3 Simulation Results

There was no real simulation test to be run separately for the DSSS Demodulation
Subsystem. The signal was output and then passed through several LPF and inverter stages to be
wave-shaped into a square wave 5 Vpk-pk with offset so Vlow = 0 V. See Observed and Measured
Results below for output figures from this stage.

5.6.4 Observed and Measured Results

DSSS Demodulation Subsystem takes the BPSK input OCO x DA x CA and
spread carrier LCO x CA into Balanced Modulator. Balanced Modulator demodulates
and recovers DA after an amplifier & LPF stage.

Consult Figs. 3.3.5, 3.3.6, and 3.3.7 for oscilloscope and spectrum plots of the
resultant BPSK signal. The demodulated DA from DSSS Demodulation subsystem is compared
with input DA from DSSS TX Subsystem for effect in Fig. 3.3.8.

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 5.3Hamming Channel Code Subsystem
Team member who designed this subsystem: Ryan Ginter
Team member who wrote this subsection: Ryan Ginter

The Hamming (7, 4) Subsystem was decided upon to be responsible for the system’s
error detection and correction. This system is composed of two parts. One part is the Hamming
Parity Generator Subsystem, which is used in the Baseband Transmit Data Subsystem. The other
is the Hamming Error Detection and Correction Subsystem that is used in the Baseband Receive
Data Subsystem. Together these systems work to prevent any bit errors to cause false alarms or
resets in the overall system.

5.7.1 Theoretical Considerations

The first part of the Hamming Subsystem is the parity bit generator. The key component
to Hamming codes is the Hamming distance that is between any set of data. This distance is
determined by the number of bits that would need to have an error in order for the data to
become the alternative set of data. The Hamming generator maximizes this distance by ensuring
that the only set of data that shares the same parity bits is far from the desired set of data. To do
this theoretically linear algebra techniques are used to do matrix manipulations. The first matrix
of concern is the Hamming generator matrix, which essentially takes 4 bits, 16 possible
combinations, and maps them to 3 parity bits, 8 possible combinations. The theoretical mapping
is as follows using the generator matrix:

|1000011|
G=|0100101|
|0010110|
|0001111|

Take the data vector D times G, where D = [D1 D2 D3 D4]. The result of this multiplication will
be a 1x7 vector made up of the original data vector plus 3 additional parity bits, D’= [D1 D2 D3
D4 P1 P2 P3]. The parity bits are formed via the following equations:

P1 = D2 + D3 + D4 (5.7.1)
P2 = D1 + D3 + D4 (5.7.2)
P3 = D1 + D2 + D4 (5.7.3)

Note these additions are done modulo 2. Based on these formulas the following theoretical
mapping is determined to relate each possible set of data to its correspond parity bits.

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 Table 5.7.1: Theoretical Hamming Parity Bit Generation.

Theoretical
D1 D2 D3 D4
P1 P2 P3
0000 000
0001 111
0010 110
0011 001
0100 101
0101 010
0110 011
0111 100
1000 011
1001 100
1010 101
1011 010
1100 110
1101 001
1110 000
1111 111

One characteristic of the parity generator that should be noted is how each 3 bit parity
combination is repeated no more than two times. This characteristic is what allows the parity bits
to map the 16 possible outcomes of data to only 8 possible outcomes. Along with this realization
it should be noted that in order for the 3 bit parity combination to accidentally be correct, there
would need to be a bit error at D1, D2, and D3. In other words the minimum Hamming distance
is three. To display these characteristic clearer the data from Table 5.7.1 has been rearranged and
placed in Table 5.7 2.

Table 5.7.2: Data/Parity comparison highlighting important characteristics.

D1 D2 D3 D4 P1 P2 P3
0000 000
1110 000
0011 001
1101 001
0101 010
1011 010
0110 011
1000 011
0111 100
1001 100
0100 101
1010 101
0010 110
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 D1 D2 D3 D4 P1 P2 P3
1100 110
0001 111
1111 111

The detecting and correcting component takes advantage of the mapping that the parity
generator provides. When decoding the 7 bit combination of parity bits and data bits, a parity
check matrix must be designed appropriately, known as H. When this matrix is multiplied by the
7 bit vector, containing the 4 data bits and 3 parity bits, a 3 bit vector known as the syndrome is
created. When each bit of this syndrome is zero then there was no error detected. If it is not a
vector of zeros then the column of H that it matches indicates an error occurred at that respective
bit.
In the generator matrix each parity bit was determined by a specific linear combination of
data bits, now to do the parity check those equations are verified one by one to determine the
syndrome. Thus the Hamming parity check matrix will be:

|0111100|
H=|1011010|
|1101001|

Notice now that when computing D’T times H the resulting syndrome will be:

| D2 + D3 + D4 + P1 |
SYN = | D1 + D3 + D4 + P2 |
| D1 + D2 + D4 + P3 |

Note that the first three addends of each row are what generated the parity bit that is the fourth
addend. The reason why the syndrome will be zero when there is no error is because each parity
bit is essentially an even parity bit of the three data bits that determined it. To clarify if there is
an odd number of logic “1s” in the 3 data bits of the generating parity bit equations then the
respective parity bit will be logic “1”. This makes the four combined bits, 3 data 1 parity, have
an even number of logic “1s” in total. If there is and even number of logic “1s” in the initial 3
data bits then the respective parity bit is set to logic “0”. Again an even number of logic “1s” will
be represented within the combination of the 3 data bits and 1 parity bit. The syndrome simply
checks that this even parity is maintained and if so the sum modulo 2 will be zero.
The reason that the syndrome is able to indicate where the error occurred is because of
the way the parity bits overlap. Notice how each data bit other then D4 is use in exactly two
parity generating equations. This means if there is an error in any two equations then it must
have been the data bit that is used in both of those equations. If there is an error in all 3 equations
then it must have been an error in D4 because it is the only bit used in all 3. And if there is an
error in just one equation then it must have been the parity bit used in that equation.

5.7.2 Design Procedure

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