VLSI VSAT Program

CoreEL University Program Team

Contents

Introduction to Physical Design- Layout

ASIC Construction : Floorplanning, Placement &
Routing ;

Physical verification: DRC, LVS

Basics of Digital CMOS Design

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Design flow in VLSI / FPGA

Specifications
Graphical

Design Entry

Simulation

Functional Verification

Synthesizer

Synthesis

Post-syn simulation Post-Synthesis Verification

ASIC Specific
Flow

DFT
Verification Formal Verification
Layout

Layout Editor

PAR
Physical VerificationPhysical Verification

Post-PAR Verification

Simulation

Fabrication
Bit-Format

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Introduction to Physical Design

Basics of Layout Designing : Design Kits,
Standard Cells.

ASIC Backend Flow

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Basics of Chip Designing

Designer
Design Kit
GDS II

Foundry
(Fabricator)
TSMC,
UMC,
Faraday, etc

Chip
GDS = Graphic Database System
Its the de facto industry standard for data exchange of IC layout artwork.
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Transistors
Drain

Gate Drain
Source
Width

Gate
Source
Length

a) Circuit Symbol

Minimum Length=2

b) Physical Realization

Drain
Ron

Gate
Source

Bulk

Gate

Drain Width=4

Cgate

Cdrain
Csource

Source
d) Simple RC Model

c) Layout View
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Files in Design Kit

Library Database: Layout, schematic, symbol, abstract, and
other logical or simulation views.

Timing Abstract - provides functional definitions, timing,
power, and noise information for each cell

DRC, LVS, PEX rule files.

Technology files: Layer specifications

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Cell List in Digital Design Kit

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Comparison

General definition
module mux1( select, d, q );
input[1:0] select;
input[3:0] d;
output q;

module mux1 ( select, d, q ) ;

input [1:0]select ;
input [3:0]d ;
output q ;
wire nx59, nx61;
mux21 ix23 (.Y (q), .A0 (nx59),
.A1 (nx61), .S0 (select[1])) ;
mux21 ix60 (.Y (nx59), .A0 (d[0]),
.A1 (d[1]), .S0 (select[0])) ;
mux21 ix62 (.Y (nx61), .A0 (d[2]),
.A1 (d[3]), .S0 (select[0])) ;
endmodule

wire
q;
wire[1:0] select;
wire[3:0] d;
assign q = d[select];
endmodule

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 Synthesized Code
// Verilog description for cell mux1,
// LeonardoSpectrum Level 3,
2010a.7

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Design Kit

Digital Design Kit

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Standard Cells

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ASIC Backend Flow

System Partitioning: Divide Large system into

ASIC-sized Pieces
Floorplan: Arrange the blocks of the netlist on
the chip
Placement : Decide the location of cells in a
block

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Floorplan

The input to a floorplanning tool is a hierarchical netlist that
describes the interconnection of the blocks
The goals of floorplanning are to:
 arrange the blocks on a chip,
 decide the location of the I/O pads,
 decide the location and number of the power pads,
 decide the type of power distribution, and
 decide the location and type of clock distribution

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Placement
The goal of a placement tool is to arrange all the logic cells
within the flexible blocks on a chip
Goals:

Guarantee the router can complete the routing step

Minimize all the critical net delays

Make the chip as dense as possible

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Placement Algorithms
Two Types of Algorithms used:

Min-cut algorithm

Eigenvalue method

Pairwise-interchange algorithm

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Algorithms

Min-Cut Algorithm

Cut the placement area into two pieces.

Swap the logic cells to minimize the cut cost.

Repeat the process from step 1, cutting smaller pieces
until all the logic cells are placed.

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Routing

Process of placing and connecting signal and power
paths between the standard cells or blocks

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General Routing
Two phases:

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Global & Detailed Routing

Global Routing

A global router does not make any connections, it just
plans them.
The objectives of global routing are

Minimize the total interconnect length.

Maximize the probability that the detailed router can
complete the routing.

Minimize the critical path delay.

Detailed Routing

The detailed router decides the exact location and
layers for each interconnect.
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Special Routing

Clock Routing :
Uses Higher metal Layer (has less resistance & capacitance )

Power Routing:

Each of the power buses has to be sized according to the

current it will carry.

The required power-bus widths can be estimated

automatically from library information.

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Design flow in VLSI / FPGA

Specifications
Graphical

Design Entry

Simulation

Functional Verification

Synthesizer

Synthesis

Post-syn simulation Post-Synthesis Verification

ASIC Specific
Flow

DFT
Verification Formal Verification
Layout

Layout Editor

PAR
Physical VerificationPhysical Verification

Post-PAR Verification

Simulation

Fabrication
Bit-Format

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References

Application Specific Integrated Circuits-- By Smith Pearson Publication

http://iroi.seu.edu.cn/books/asics/asics.htm#anchor11320

Physical design essentials: an ASIC design implementation perspective- By Khosrow Golshan Springer Publication

Algorithms for VLSI Design Automation-- By Gerez Wiley India Edition

VLSI physical design automation: theory and practice By Sadiq M. Sait,
Habib Youssef World Scientific.

Introduction to Place and Route Design in Vlsis-- By Patrick Lee

CMOS: Circuit Design, Layout, and Simulation-- By R. Jacob Baker

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Physical Verification & PEX

Physical Verification

DRC

LVS

Parasitic Extraction (PEX)

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Physical Verification : DRC & LVS

DRC : Design Rule Checking
Inputs: Layout -- GDSII, OASIS, etc.
Rule File
Outputs
DRC Results
Report

LVS : Layout Versus Schematic

Inputs
Layout -- GDSII, OASIS, etc.
Logic (for LVS) i.e SPICE / Verilog
Rule File
Outputs
LVS Results
Report
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DRC Errors
oxide

Internal

Width:
INT oxide <=3

Overlap:
INT Oxide poly <=3

poly

Internal: Width

External

EXT oxide <=2

EXT oxide poly <= 2

External

Internal: Overlap

Enclosure
ENC poly oxide < 2

Enclosure

Extension
ENC oxide poly < 2
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LVS (Layout Vs Schematic)

RESET

Design View
RESET

Design Architect

Composer
Layout View

G
S

DESIGNrev

Connectivity
Extraction

Virtuoso
StreamView

Device
Extraction

Schematic
Compilation

HDL
Compilation

COMPARISON
PHASE

LAYOUT NETLIST

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RESULTS

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SOURCE NETLIST

LVS Rule File

Device Statements

E.g. device r(pl) rpoly ipoly ipoly [20000]

Gate Recognition Statements

LVS GROUND NAME VSS VSS1

LVS POWER NAME VDD VCC

LVS RECOGNIZE GATES ALL

Connectivity Statements

CONNECT metal1 metal2 BY via12

VIRTUAL CONNECT NAME vdd

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Shorts and Opens

Short circuits

Occur when nets that should be isolated are connected

Can lead to a difference between the number of nets:
# layout nets < # source nets

Open circuits

Occur when connectivity is not maintained over the
entire length of a layout net

Can lead to a difference between the number of nets:
# layout nets > # source nets

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Device
// Device Statement
DEVICE MN NGATE POLY NSD NSD PWELL [0]
ELEMENT = MN

1. LVS defines the MN

element template
based upon the
Device statement.

NET Y
M2

G
S

LAYER PWELL
LAYER OXIDE
LAYER POLY
LAYER NPLUS
PAREA
NGATE
NOX
NSD

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1
2
4
5

= OXIDE AND PWELL

= POLY AND PAREA
= OXIDE AND NPLUS
= NOX NOT NGATE

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Parasitic Extraction

Extracts the parasitic values of each interconnect, via, and
contact that will be on the silicon wafer

Parasitic Formats: SPF, RPF and DSPF

The standard parasitic format ( SPF ) describes interconnect
delay and loading due to parasitic resistance and
capacitance.
RSPF Reduced SPF.
DSPF--- Detailed SPF , describes the actual parasitic
resistance and capacitance components of a net.
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Physical Verification Flow using Calibre

Rule file

Layout
GDSII

Source
netlist

Hcell list
(optional)

Netlist extraction
Calibre LVS-H

Comparison

Extraction
report

Extracted
netlist

Fix layout
errors

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LVS
report

svdb

Locate errors using

Calibre RVE & Layout tool

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References

Physical design essentials: an ASIC design implementation
perspective-- By Khosrow Golshan Springer Publication

http://www.mentor.com/products/ic_nanometer_design/verifi
cation-signoff/physical-verification/

IC mask design: essential layout techniques-- by
Christopher Saint, Judy Saint

CMOS: Circuit Design, Layout, and Simulation-- By R.
Jacob Baker

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Basics of Digital CMOS Design

Basic Working of CMOS logic

Models of Digital Design

Pass Gate

Transmission Gate

Inverter

DC Characteristics

Switching Characteristics

Sizing

Logic Effort

Types of Logic Circuits

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Complementary CMOS

Complementary CMOS logic gates

nMOS pull-down network

pMOS pull-up network

a.k.a. static CMOS

pMOS
pull-up
network

inputs
output

Pull-up OFF

Pull-up ON

Pull-down OFF Z (float)

Pull-down ON

X (crowbar)

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nMOS
pull-down
network

Series and Parallel

nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON

a
g1
g2

1
b

OFF

ON

(b)

a
g2

(c)

a
g1

g2
b

(d)

ON

OFF

OFF

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b
OFF

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b
OFF

g1

(a)

g2

g1

OFF

ON

ON

ON

ON

ON

ON

OFF

Conduction Complement

Complementary CMOS gates always produce 0 or 1

Ex: NAND gate

Series nMOS: Y=0 when both inputs are 1

Thus Y=1 when either input is 0
Y

Requires parallel pMOS
A

Rule of Conduction Complements

Pull-up network is complement of pull-down

Parallel -> series, series -> parallel

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Compound Gates

Compound gates can do any inverting function

Ex:

Y = A B + C D (AND-AND-OR-INVERT, AOI22)
A

(a)

(b)

B C

(c)

(d)

A
B
C
D

Y
A

(f)

(e)

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Signal Strength

Strength of signal

How close it approximates ideal voltage source

VDD and GND rails are strongest 1 and 0

nMOS pass strong 0

But degraded or weak 1

pMOS pass strong 1

But degraded or weak 0

Thus nMOS are best for pull-down network

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Why NMOS is week 1?

The nMOS transistor will stop conducting if VGS < VT.
Let VT = 0.7V,

As source goes from 0V 5V, VGS goes from 5V 0V.
When VS > 4.3V, then VGS < VT, so switch stops
conducting.
VD left at 5V - VT = 5V - 0.7V = 4.3V or Vdd - VT.
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Pass Transistors

Transistors can be used as switches

g=0

g
s

Input g = 1 Output
0
strong 0

g=1
s

d
g=0

g
s

g=1

Input
d

g=1
s

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degraded 1
g=0

Output
degraded 0

g=0

strong 1

Transmission Gates

Pass transistors produce degraded outputs

Transmission gates pass both 0 and 1 well

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Transmission Gates

Pass transistors produce degraded outputs

Transmission gates pass both 0 and 1 well

Input
g
a

b
gb

b
gb

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g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
a

g
b

gb

Output

b
gb

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CMOS Inverter
N Well

VDD

VDD

PMOS

Contacts

PMOS
In

Out
In

Out
Metal 1

Polysilicon

NMOS
NMOS
GND

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V-I Characteristic Curve

I Dn

PMOS

Vin = 0

Vin = 2.5

Vin = 0.5

Vin = 2

Vin = 1

NMOS

Vin = 1.5

Vin = 1.5

Vin = 1
Vin = 1.5

Vin = 1

Vin = 2

Vin = 0.5

Vin = 2.5

Vin = 0
Vout

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CMOS Inverter VTC Curve

NMOS off
PMOS res

2.5

Vout

NMOS s at
PMOS res

1.5

NMOS sat
PMOS sat

0.5

NMOS res
PMOS sat

0.5

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NMOS res
PMOS off
2.5

Vin

Switching Characteristics

Define:

Rise time tr = time required for a node to charge from the 10% point to 90% point

Fall time tf = time required for a node to discharge from 90% to 10% point

Delay time td = delay from the 50% point on the input to the 50% point on the
output

Falling delay tdf = delay time with output falling

Rising delay tdr = delay time with output rising

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Noise Margin

Noise margin = voltage difference between output of one
gate and input of next. Noise must exceed noise margin to
make second gate produce wrong output.

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Inverter Sizing

In each case, the rise or fall time depends on the channel

resistance, which in-turn, depends on the device
dimensions.
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Gate Delay Components

Cin
Cout

Logic Gate

Split delay of logic gate into three components

Delay = Logical Effort x Electrical Effort + Parasitic Delay

Logical Effort

Complexity of logic function (Invert, NAND, NOR, etc)

Define inverter has logical effort = 1

Depends only on topology not transistor sizing

Electrical Effort

Ratio of output capacitance to input capacitance Cout/Cin

Parasitic Delay

Intrinsic self-loading of gate

Independent of transistor sizes and output load
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Method of Logical Effort

Easy way to estimate delays in CMOS process

Indicates correct number of logic stages to use and
transistor sizes

Characterize process speed with single delay parameter:
, delay of inverter driving same-sized inverter (no parasitic)

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Logical Effort for Simple Gates

Define Logical Effort of Inverter = 1

For other gates, size to give same current drive as inverter

Logical Effort is ratio of logic gates input cap. to inverters input cap.

Relative
Transistor
Widths

1
Inverter
Input Cap = 3 units
L.E.=1 (definition)
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4
(2n+1)/3

(n+2)/3

2
NAND
Input Cap = 4 units
L.E.=4/3
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4
1

NOR
Input Cap = 5 units
L.E.=5/3

Logic Blocks

F = AB(C+D)

N-block implementation of a Boolean function

A series of N connection P(A,B)= AB;
A parallel of N Connection P(A,B)= A+B;
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CMOS Tristate & Buffer

Tristate

CMOS Buffer

output

High Z

High Z

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When long lines or chip outputs

must be driven buffer circuits,
which have the advantage that
the output driving transistors are
directly connected to the output
and ground or respectively
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Types of Logic Circuits

Static CMOS

Dynamic CMOS

Pseudo NMOS

Pass Transistor Logic

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Static CMOS

Characteristics
At every point in time, each gate output is connected to either Vdd or Vss via a
low-resistance path
It have rail-to-rail swing , no static power dissipation
Speed depends on the transistor sizing and parasitic that are involved with it.
Disadvantage
The problem with this type of implementation is that for N fan-in gate 2N
number of transistors are required, ie, more area required to implement logic.
This has an impact on the capacitance and thus the speed of the gate.
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Dynamic CMOS

Buffered dynamic CMOS (domino) logic

Characteristics
Dynamic CMOS circuits rely on the temporary storage of signal values on the
capacitance of high-impedance circuit nodes.
no static power dissipation.
Disadvantage
the need for repeated charging and discharging even when the inputs do not
change their state.

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Pseudo NMOS

Characteristics
The advantage of pseudo-NMOS logic are its high speed and low transistor
count.
Disadvantage
Static power consumption of the pull-up transistor as well as the reduced
output voltage swing and gain, which makes the gate more susceptible to
noise.

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Pass Transistor Logic

Characteristics
The advantages of pass-transistor logic are
the simple design, the reuse of already
available signals.
Low contribution to static power.
Disadvantage
Output levels can be no higher than the input
level
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Four-to-one multiplexer in pass-transistor logic

References

CMOS: Circuit Design, Layout, and Simulation-- By R. Jacob Baker

CMOS Digital Integrated Circuits-- By Sung-Mo Kang, Yusuf Leblebici

CMOS logic circuit design-- By John Paul Uyemura

Cmos Vlsi Design: A Circuits And Systems Perspective, 3/E-- By Weste,
Weste Neil H.E.

Douglas A. Pucknell and Kamran Eshraghian, Basic VLSI Design, Third
Edition

http://www.iue.tuwien.ac.at/phd/schrom/node93.html

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Thank You
upt@coreel.com

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