HD74LS273

Octal D-type Positive-edge-triggered Flip-Flops (with Clear)

REJ03D04730300
Rev.3.00
Jul.15.2005
The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a
direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse.
When the clock input is at either the high or low level, the D input signal has no effect at the output.

Features
Ordering Information
Part Name

Package Type

Package Code
(Previous Code)

Package
Abbreviation

Taping Abbreviation
(Quantity)

HD74LS273P

DILP-20 pin

PRDP0020AC-B
(DP-20NEV)

HD74LS273FPEL

SOP-20 pin (JEITA)

PRSP0020DD-B
(FP-20DAV)

FP

EL (2,000 pcs/reel)

PRSP0020DC-A
RP
(FP-20DBV)
Note: Please consult the sales office for the above package availability.
HD74LS273RPEL

SOP-20 pin (JEDEC)

EL (1,000 pcs/reel)

Pin Arrangement

Clear

1Q

1D

Clear
D CK

2D

2Q

3Q

3D

Clear
D CK

4D

4Q

GND

10

CK
Clear

CK
Clear

20

VCC

Q
Clear
CK D

19

8Q

18

8D

CK D
Clear
Q

17

7D

16

7Q

Q
Clear
CK D

15

6Q

14

6D

CK D
Clear
Q

13

5D

12

5Q

11

Clock

(Top view)

Rev.3.00, Jul.15.2005, page 1 of 6

HD74LS273

Function Table
Inputs
Clock
X

Clear
L
H
H
H

Output
Q
L
H
L
Q0

D
X
H
L
X

Notes: H; high level, L; low level, X; irrelevant

; transition from low to high level
Q0; level of Q before the indicated steady-state input conditions were established.

Block Diagram
1D

2D

3D

4D

5D

6D

7D

8D

Clock (1)
D Q
CK
Clear

D Q
CK
Clear

D Q
CK
Clear

D Q
CK
Clear

D Q
CK
Clear

D Q
CK
Clear

D Q
CK
Clear

D Q
CK
Clear

Clear (2)

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

Absolute Maximum Ratings

Item

Symbol

Ratings

Unit

Supply voltage

VCC

Input voltage

VIN

PT

400

mW

Tstg

65 to +150

Power dissipation
Storage temperature

Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.

Recommended Operating Conditions

Item
Supply voltage
Output current

Symbol

Min

Typ

Max

Unit

VCC

4.75

5.00

5.25

IOH

400

A
mA

IOL

Operating temperature

Topr

20

25

75

Clock frequency

clock

30

MHz

tw (clock)

20

ns

Clock pulse width

Clear pulse width

tw (clear)

20

ns

Data setup time

tsu (data)

20

ns

Clear (inactive-state) setup time

tsu (clear)

25

ns

Data hold time

th (data)

ns

Rev.3.00, Jul.15.2005, page 2 of 6

HD74LS273

Electrical Characteristics
(Ta = 20 to +75 C)
Item
Input voltage

Symbol
VIH
VIL

min.
2.0

typ.*

max.

0.8

Unit
V
V

VOH

2.7

20

0.5
0.4
20
0.4
0.1
100
27
1.5

Output voltage
VOL
IIH
IIL

Input current

V
A
mA
mA
mA
mA
V

Condition

VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,

IOH = 400 A
IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
IOL = 4 mA VIL = 0.8 V
VCC = 5.25 V, VI = 2.7 V
VCC = 5.25 V, VI = 0.4 V
VCC = 5.25 V, VI = 7 V
VCC = 5.25 V
VCC = 5.25 V
VCC = 4.75 V, IIN = 18 mA

II
Short-circuit output current
IOS

Supply current
ICC**
17
Input clamp voltage
VIK

Notes: * VCC = 5 V, Ta = 25C

** With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary
ground, then 4.5 V is applied to clock.

Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item
Maximum clock frequency
Propagation delay time

Symbol
max
tPHL
tPLH
tPHL

Inputs
Clock
Clear

min.
30

Clock

typ.
40
18
17
18

max.

27
27
27

Testing Method
Test Circuit
VCC
Input 4.5V
P.G.
Zout = 50

Output
Input

P.G.
Zout = 50

1. CL includes probe and jig capacitance.

2. All diodes are 1S2074(H).

Rev.3.00, Jul.15.2005, page 3 of 6

Clock
Clear

Notes:

RL

CL

Unit
MHz
ns

Condition

CL = 15 pF, RL = 2 k

HD74LS273
Waveforms 1
tTLH

Data

tTHL

90%
1.3 V

3V

90%
1.3 V

1.3 V

10%

10%

tsu

0V

tsu

th

tTLH

th

tTHL
3V

90% 90%
1.3 V
1.3 V
10%

Clock

1.3 V
10%

tw

0V
tw
tPHL

tPLH

VOH

Q
1.3 V

1.3 V

VOL

Notes: Input pulse; tTLH 15 ns, tTHL 6 ns,

Clock input; PRR = 1 MHz, duty cycle 50%
Data input; PRR = 500 kHz, duty cycle 50%

Waveforms 2
tTLH

tTHL

Clear

90%
1.3V

3V

90%
1.3V
10%

10%
tw

0V
tw

Clock

tTHL

tTLH

90%
1.3V

90%
1.3V
10%

10%

3V
0V

tPHL
tw
Q

1.3V

tPLH

VOH
1.3V
VOL

Note:

Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz.

Rev.3.00, Jul.15.2005, page 4 of 6

HD74LS273

Package Dimensions
JEITA Package Code
P-DIP20-6.3x24.5-2.54

RENESAS Code
PRDP0020AC-B

Previous Code
DP-20NEV

MASS[Typ.]
1.26g

11

20

10
b3

0.89

Dimension in Millimeters
Min

Nom

Max

Reference
Symbol

A1

e
D

24.50

6.30

c
e1

A1

0.51

0.40

JEITA Package Code

P-SOP20-5.5x12.6-1.27

RENESAS Code
PRSP0020DD-B

*1

Previous Code
FP-20DAV

0.48

0.56

0.19

2.29

0.25

0.31

2.54

2.79

15

1.27

2.54

MASS[Typ.]
0.31g

NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.

20

7.00

1.30

Z
( Ni/Pd/Au plating )

25.40

5.08

bp

7.62

11

HE

*2

bp

Index mark
Reference
Symbol

Terminal cross section

( Ni/Pd/Au plating )
Z

*3

bp

Nom

Max

12.60

13.0

5.50

A2

10

A1
x

Dimension in Millimeters
Min

0.00

0.10

0.20

0.34

0.40

0.46

0.15

0.20

0.25

7.80

8.00

2.20

A
L1

bp
b1
c

HE

A1

Detail F

1.27

0.12

0.15
0.80

Z
0.50

L
L

Rev.3.00, Jul.15.2005, page 5 of 6

7.50

0.70
1.15

0.90

HD74LS273
JEITA Package Code
P-SOP20-7.5x12.8-1.27

RENESAS Code
PRSP0020DC-A

*1

Previous Code
FP-20DBV

MASS[Typ.]
0.52g

20

NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
@ DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
@ INCLUDE TRIM OFFSET.

11

HE

*2

bp

Index mark
Reference
Symbol

Terminal cross section

( Ni/Pd/Au plating )

Dimension in Millimeters
Min

Nom

Max

12.80

13.2

7.50

A2
10

1
Z

*3

bp

A1
M

0.10

0.20

0.30

0.34

0.40

0.46

0.20

0.25

0.30

10.40

10.65

L1

2.65

bp
b1
c

A1

HE

10.00

1.27

e
x

0.12

0.15
0.935

Detail F

L
L

Rev.3.00, Jul.15.2005, page 6 of 6

0.40
1

0.70
1.45

1.27

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