THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2009/2010
1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

4
Design and Implementation of a LCD Hardware Driver

Lab Weighting:

35%

Delivery mode:

Lecture

Online
 Lab

Other

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use of Xilinx ISE and Modelsim in the implementation of digital
system
2. VHDL programming

Recommended
prior knowledge
and skills3:

Course Staff

Position/Role

Estimated total
study hours1:

Cathy Radix

Lecturer

E-mail

Cathy.Radix@sta.uwi.tt

Azim Abdool

Instructor

azim.abdool@sta.uwi.tt

10

Phone
Office
Office

Hours
x3157 Rm 321, Mon/Tue
Blk 1
11am 2pm
x2636 Rm 341/ Mon/
RTSG,
Thu
Blk 1
11am12pm

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Understand the operation of the HITACHI HD44780 LCD controller chip
and its involvement in the JHD204A LCD display.
2. Implement a FSM plementation of a LCD Hardware driver for the
JHD204A LCD display
3. Use the FSM-D method in the design of a finite state machine

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:

Cognitive
Level
C
Ap
Ap, Sy

N/A (To be completed in advance of in-lab session)

N/A
2 hours

3.1. Required Reading Resources

1. Datasheet for the JHD204A LCD display labelled as jhd204a.pdf on MyeLearning.
2. Datasheet for the HITACHI HD44780U (LCD-II)(Dot Matrix Liquid Crystal Display
Controller/Driver) ADE-207-272(Z) '99.9 Rev. 0.0 labelled as hd44780.pdf on
MyeLearning.

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

3.4 Pre-Lab Exercise [5 marks]

3.4.1

Characteristics of the JHD204A LCD Display [13 marks]

1. List all control pins of the JHD204A LCD display. [3 marks]

2. Using the datasheet for the JHD204A LCD display, determine the following: [1 mark]
a. Typical supply voltage required by the JHD204A LCD display
b. Input High Voltage (VIH)
c. Minimum cycle time for control signal E, in write mode (for VDD in the range 2.7V
- 4.5V)
d. Minimum pulse width for control signal E, in write mode (for VDD in the range
2.7V - 4.5V)
3. Using table 4 (on page 17) of the datasheet of the HD44780, determine the ASCII
representation of the following characters: i, I, c, C, g, G, d, D, 1, 2. [1 mark]

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

Reading Exercise - System Requirements

 This laboratory exercise comprises the design and implementation of a FSM-based LCD
Hardware driver for the JHD204A LCD display using the FSM-D method.
 The JHD204A has 16 pins: GND, VCC, VEE, RS, WR, E, Data pin (D0-D7), LED+,LED-. The
following Table 1 below gives the pin configurations for the JHD204A LCD.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Name of Pin
GND
VDD
VEE
RS
W/R
E
D0
D1
D2
D3
D4
D5
D6
D7
LED+
LED-

Connection
FPGA GND
FPGA VCC (+5V)
FPGA GND
FPGA Pin
FPGA GND
FPGA Pin
FPGA Pin
FPGA Pin
FPGA Pin
FPGA Pin
FPGA Pin
FPGA Pin
FPGA Pin
FPGA Pin
Unconnected
Unconnected

Table 1: Pin Configuration for the JHD204A LCD

 In this lab we will not be reading data from the LCD, hence the W/R pin will be fixed to ground
(GND).
 Students will be required to perform the following functions using the JHD204A LCD:

Display a pre-defined character on the display at the current cursor position

Clear display

Set the cursor position to a pre-defined DDRAM address

 It is to be noted that when a command is sent to the LCD, the state of the RS and E pins must be
altered in order to achieve the desired functionality. Pin E must be set HIGH for at least 500s
for each command. Pin RS must only be set HIGH when data is to be displayed on the LCD.
Table 2 below gives a summary of the nature of both the RS and E pins for the required
functions of the system.

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

System Functionality
Display data on LCD
Clear display
Set cursor position

Nature of RS and E pins

RS = 1, E = 1
RS = 0, E = 1
RS = 0, E = 1

Table 2: Nature of RS and E pins for various LCD commands

 The FSM-type LCD Hardware driver for the JHD204A LCD display will consist of a central
control unit we call the Instruction Controller. We can model the Instruction Controller using a
flow chart as shown in Figure 1 below. This flowchart will be of significant importance in the
in-lab section of the lab. Since we will be utilizing the FSM-D method for creating this unit, it is
important as a first step that you understand the strategy that it implements.

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

Figure 1: Flow chart of the operation of the LCD Instruction Controller

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

4.

IN-LAB

Allotted Completion 6 hours

Time:
1 Computer
Required lab
1 Spartan 3 Toolkit
Equipment:
1 JHD204A LCD Display
1 breadboard
Copper Wire
Pliers/Wire Clippers

4.1. In-Lab Procedure

4.1.2 FSM-type LCD Hardware driver [39 marks]

Ensure that you first understand the algorithm that describes the system behaviour as given
by the flowchart in Figure 1. Also note well the inputs and outputs of the instruction controller as
given by the diagram of Figure 2. As you would note, these are the first two steps of the FSM-D
design method. (Assume that the frequency divider output clock frequency that feeds the system
is 10 kHz). Follow the FSM-D procedure as given below in the deployment of this LCD hardware
driver.
1. Design and draw a data-path block diagram which would implement the data functions of the
illustrated algorithm. You should relate each entity in your data-path to the set algorithm. It is
advised that you develop this incrementally so as to show that you have implemented each
section of the given algorithm. [3 marks]
2. Tabularize your inputs and outputs (interface definition) for:
a. the created data-path (illustrate which exist on the system boundary and which go to
the controller FSM) [1 mark]
b. the controller FSM [1 mark]
3. Define the states of the controller FSM [1 mark]
4. Create a state diagram for the FSM module to illustrate its behaviour [2 marks]
5. Create a block diagram to show the FSM design [1 mark]

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

6. Open Xilinx ISE and create a new project called FSM_LCD_Hardware_Driver. Write the
VHDL code for the LCD hardware driver data-path and FSM controller . Perform simulations
at the behavioural and PAR levels using the ISim simulator for:
a. the data-path elements [3 marks]
b. the FSM controller [3 marks]
c. the final instruction controller entity [3 marks]
7. Implement the frequency divider required to produce a 10 kHz clock signal for both the 3-bit
debounce module and the instruction controller in VHDL. Implement the 3-bit debounce
module for the system in VHDL. You can utilize the language template example to assist in its
creation. Perform simulations at the behavioural and PAR levels using the ISim simulator. [3
marks]
8. Interface system modules together in a VHDL module named LCD_FSM_Driver_Main.vhd.
Use the block diagram of Figure 2 as your guide. Create an implementation constraints file for
the system and connect the Spartan 3 development board to the LCD. Download the bitstream
to the Spartan 3 FPGA development board and perform on-board testing on the system. [2
marks]
9. Another module, called message_printer, will interface with instruction_controller and print to
the LCD screen a message on the first line Adv Dig and on the second line Done.
Message_printer should take the message from a 16x16 bit ROM that should store each
DDRam address alongside the character to be printed. Be sure to follow the first two steps of
the FSM-D procedure to design message_printer by creating the algorithm and the system
interface. [3 marks]
10. For the message_printer module proposed above, use the steps of the FSM-D procedure to
implement and test on the Spartan 3 development board. [13 marks]

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

Figure 2: Datapath block diagram of the FSM-type LCD Hardware Driver

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

Proceed to post-lab exercise.

Mini-Project 2: Design and Implementation of a LCD Hardware Driver

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:

Deliverables:

Friday 2nd April, 2009

Students must submit soft-copies of their report (in *.pdf format) to the
myelearning course support website. A copy of the project folder for the
DTMF Generator must also be submitted. The project folder may be
compressed (either *.rar or *.zip) and named as L01_YourUwiId. The
document of your report should be in a *.pdf format and named similarly.
Students are expected to produce an informal report on the entire lab
exercise.
Please organize your report in sections so that it is easy to read and
assess.
1. Pre-lab Exercise [5 marks]
2. In-lab Exercise: FSM-type LCD Hardware Driver [39 marks]

Demonstration of Working Systems [10 marks]

Students must demonstrate the working system to the course staff
during the week of 8th of March. Groups should contact the staff and
arrange for a mutually convenient time/venue. Demonstration marks
will not be awarded unless students demonstrate their work
during this week.
Students are urged to submit responses to questions asked in this
laboratory exercise in the order of appearance in order to ease
marking and ensure thorough marking of reports.

End of Mini-Project 2: Design and Implementation of a LCD Hardware

Driver