More Moore Roadmap ITRS 2.

0 White Paper
PIDS, Lithography, FEP, Metrology, Interconnect

1. ITRS 2.0 AND MORE MOORE MISSION

CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to
Moore's law. System scaling is getting more difficult with the limitations in interconnect and bandwidth per power as well as the
difficulties and cost of monolithic integration. This requires a holistic approach for an optimal balance of performance and power
under the limits of technology. This paper covers a portfolio of More Moore technologies for power-aware device enabling value
proposition for system scaling where requirements and gaps will be addressed in the ITRS2.0 roadmap.
Due to a changing environment with applications becoming more important in determining future technology requirements, the
ITRS now has 7 Focus teams that will analyze trends in the application areas and identify new technology requirements. Those focus
teams will streamline system requirements across technology work groups (TWGs). This will necessitate the definition of a new
roadmap, which is steered by application requirements [1][2]. This application guided technology targeting will transform into a
reframed roadmap, which is the so-called ITRS 2.0. These 7 focus teams are:

Systems Integration: studies and recommends system architectures to meet the needs of the industry. It prescribes ways of
assembling heterogeneous building blocks into coherent systems.

More Moore: refers to the continued shrinking of horizontal and vertical physical feature sizes to reduce cost and improve
performance.

Beyond CMOS: devices, focused on new physical states, which provide functional scaling substantially beyond CMOS,
such as spin-based devices, ferromagnetic logic, and atomic switch.

Heterogeneous Components: describes devices that do not necessarily scale according to Moore's Law, and provide
additional functionalities, such as power generation and management, or sensing and actuating.

Heterogeneous Integration (More than Moore): refers to the integration of separately manufactured technologies that in the
aggregate provide enhanced functionality

Outside System Connectivity: refers to physical and wireless technologies that connect different parts of systems.

Factory Integration: consists of tools and processes necessary to produce items at affordable cost in high volume.

More Moore focus team mission is to identify options and gaps in an effort to provide guidance for physical, electrical and
reliability requirements for logic devices to sustain More Moore (PPAC: power, performance, area, cost) scaling for big data,
mobility, and cloud applications. In this regard it is aiming to forecast device technologies (15 years) in main-stream manufacturing
for digital/logic and memory technologies. Good guidance on system drivers are addressed in [2].
In this paper we will discuss the impact of system requirements on power-aware device technology roadmap targeting [1].

2. APPLICATION REQUIREMENTS
System scaling enabled by Moores scaling is more and more challenged with the scarcity of resources such as power and
interconnect bandwidth. These challenges were traditionally solved (or delayed) by reducing the dimensions, increasing drive,
reducing voltage and also employing parallelism at architecture level. However, parallelism is challenged by increasing portion of
active leakage in total power consumption and silicon area.
Following applications drive requirements of More Moore technologies.

High-performance computing targeting more performance (operating frequency) at constant power density (constrained
by thermal).

Mobile computing targeting more performance (operating frequency) and functionality at constant energy (constrained by
battery) and cost

Autonomous sensing & computing (Internet-of-Things: IoT) targeting reduced leakage & variability

Particularly due to the emergence of cloud, seamless interaction of big-data and instant data have become a necessity (Figure 1).
Instant data generation require ultra-low-power device with always-on feature at the same time with high-performance device that
can generate the data instantly. Big data require abundant computing and memory resources to generate the service and information
that clients need.

Figure 1: Big data and Instant Data.

These applications dictated the need for More Moore platform to bring the PPAC value for node-to-node scaling (every 2-3
years):

(P)erformance: >40% more maximum operating frequency at constant energy

(P)ower: >65% less energy per switching at a given performance

(A)rea: >50% area reduction

(C)ost: <15% wafer cost 35-40% less die cost for scaled die

Battery limits keep the power consumption budget for the application processor at 450 mW (Figure 2). Unfortunately, this power
budget does not improve from node-to-node while on the other hand the amount of logic gates placed in a System-on-Chip (SoC)
increases by a factor 2 from node-to-node [2]. Increasing amount of components under constant power budget puts a limit to the
usage percentage (utilization) of gates in SoC [3]. Currently the reduction of supply voltage does not suffice to meet the system
requirements for the battery and thermal power envelope of the high-performance application [4]. Therefore, it is necessary to
aggressively reduce the supply voltage for maximal amount of functions at iso power.

150mW 450mW
LCD
Backlight

Max = 3W
(plastic package limitation)

Application
Processor
+
DRAM

DRAM

FLASH

RF

170mW
WLAN+BT+
GPS+FM

Audio
Codec

Power

PA

10h video playback - average power budget allocation

Figure 2: Power budget allocation in a mobile device.

In the next chapters we will discuss challenges, roadblocks, and potential solutions in order to potentially address the following
through interaction with different technology working groups (TWGs) and Focus Teams:

Process integration and device scaling (Process Integration and Devices & Structures)

Manufacturing challenges of devices (Front-end processes TWG)

Process control requirements (Metrology TWG)

Interconnect scaling (Interconnect TWG)

Area scaling (Lithography TWG)

3. PROCESS INTEGRATION AND DEVICE SCALING (PIDS TWG)

KEY CHALLENGES
Table summarizes summarizes difficult challenges to continue scaling of devices and memory. These challenges are divided into
near-term 2014-2020 and long-term 2021-2028.
Table 1: Process integration difficult challenges.

Near-Term 2014-2020

1. Scaling Si CMOS

2. Implementation of
high-mobility CMOS
channel materials

3. Scaling of DRAM and

SRAM

4. Scaling high-density
non-volatile memory

5. Reliability due to
material, process, and
structural changes, and
novel applications.

Long-Term 2021-2028
1. Implementation of
advanced multi-gate
structures

Summary of Issues
Scaling of fully depleted SOI and multi-gate (MG) structures
Implementation of gate-all-around (nanowire) structures
Controlling source/drain series resistance within tolerable limits
Further scaling of EOT with higher K materials (K > 30)
Threshold voltage tuning and control with metal gate and high- stack
Inducing adequate strain in advanced structures
Basic issues same as Si devices listed above
High-K gate dielectrics and interface state (Dit) control
CMOS (n- and p-channel) solution with monolithic material integration
Epitaxy of lattice-mismatched materials on Si substrate
Process complexity and compatibility with significant thermal budget limitations
DRAM
Adequate storage capacitance with reduced feature size; implementing high- dielectrics
Low leakage in access transistor and storage capacitor; implementing buried gate type/saddle fin type
FET
Low resistance for bit- and word-lines to ensure desired speed
Improve bit density and lower production cost in driving toward 4F2 cell size
SRAM
Maintain adequate noise margin and control key instabilities and soft-error rate
Difficult lithography and etch issues
Endurance, noise margin, and reliability requirements
Multi-level at < 20 nm nodes and 4-bit/cell MLC
Non-scalability of tunnel dielectric and interpoly dielectric in flash memory difficulty of
maintaining high gate coupling ratio for floating-gate flash
Few electron storage and word line breakdown voltage limitations
Cost of multi-patterning lithography
Implement 3-D NAND flash cost effectively
Solve memory latency gap in systems
TDDB, NBTI, PBTI, HCI, RTN in scaled and non-planar devices
Gate to contact breakdown
Increasing statistical variation of intrinsic failure mechanisms in scaled and non-planar devices
3D interconnect reliability challenges
Reduced reliability margins drive need for improved understanding of reliability at circuit level
Reliability of embedded electronics in extreme or critical environments (medical, automotive,
grid...)
Summary of Issues
Fabrication of advanced non-planar multi-gate and nanowire MOSFETs to below 10 nm gate length
Control of short-channel effects
Source/drain engineering to control parasitic resistance
Strain enhanced thermal velocity and quasi-ballistic transport
Scaling storage capacitor for DRAM
DRAM and SRAM replacement solutions

2. Identification and
implementation of new
memory structures
3. Reliability of novel
devices, structures, and
materials.

4. Power scaling
5. Integration for
functional diversification

Cost effective installation of high density 3-D NAND (512 Gb 4 Tb) with high layer numbers or
tight cell pitch
Implementing non-charge-storage type of NVM cost effectively
Low-cost, high-density, low-power, fast-latency memory for large systems
Understand and control the failure mechanisms associated with new materials and structures for both
transistor and interconnect
Shift to system level reliability perspective with unreliable devices
Muon-induced soft error rate
Vdd scaling while supplying sufficient current drive
Controlling subthreshold current or/and subthreshold slope
Margin issues for low Vdd
Integration of multiple functions onto Si CMOS platform
3-D integration

In the early years before 130nm node, transistors enjoyed Dennard scaling where oxide thickness (EOT), transistor length (Lg)
and transistor width (W) were scaled by a constant factor in order to provide a delay improvement at constant power density.
Nowadays there are numerous input parameters that can be varied, and the output parameters are complicated functions of these input
parameters, other sets of projected parameter values (i.e., different scaling scenarios) may be found to achieve the same target. In
order to maintain the scaling at low voltages, scaling in recent years focused on additional knobs to boost the performance such as
the use of introducing strain to channel, stress boosters, high-k metal gate, lowering contact resistance, and improving electrostatics.
This was all done in order to compensate the gate drive loss while supply voltage needs to be scaled down for high-performance
mobile applications [5].
For the 2013 edition of the ITRS, we used the support from the NanoHub Team of Purdue University using the Nanohub TCAD
tools [8]. This allowed us to understand the fundamental limits of standard scaling scenario where Vdd, Lg, EOT, and channel doping
(for planar only) are varied. NanoHub is well-known for its variety of tools and lectures. It was shown that the n-channel MOSFET
saturation drive current, Id,sat, is found to increase only for a few years and then starts to drop (Figure 3). One of the reasons for the
drop of current is mainly due to Vdd scaling despite the fact that it was kept moderately scaling to maintain enough inversion charge
in the channel. There is also significant source-drain tunneling which comes to the picture for channel lengths below 10 nm. This
source-drain tunneling makes the device harder to turn off and increases the subthreshold swing (SS). The tunneling current requires
the threshold voltage to be higher to maintain the fixed Ioff, and consequently leads to a reduction in the inversion charge. This then
resulted in drop of performance (I/CV) trend (4%/year), particularly after 2018 (Figure 3).

4.00

Bulk planar

Field-effect limited device

4%/year - I/CV

2.00

1.00
2013

2018

2023

Figure 3: Idsat and I/CV scaling trend for bulk planar and field-effect limited devices (e.g. finFET) [8].

POTENTIAL SOLUTIONS
Following knobs are used to scale down Vdd while improving performance [9]:

Enhance drive

Reduce parasitics

Increase drive per footprint by 3D structures

2028

Improve electrostatics and device isolation

Reduce process & material variations

Transition to new device architectures

Enhancing drive: High-mobility materials (Ge, IIIV) bring promise in increasing drive current by means of an order of
magnitude increase in intrinsic mobility (Figure 4). With the scaling in gate length, the impact of mobility of drain current becomes
limited because of the velocity saturation. On the other hand whenever gate length further scales down, the carrier transport becomes
ballistic. This allows velocity of carriers, which is the so-called injection velocity, scale with the mobility increase. Having drain
current mostly ballistic increases the injection velocity because of lower effective mass, therefore results in increase of the drain
current. However, low effective mass for the high mobility device can actually bring high tunneling current at higher supply voltage.
This may degrade performance of III-V devices at short channel after work function tuning (e.g. threshold voltage increase) to lower
Ioff to compensate the tunneling current. Another consideration for high mobility channel is the lower density of states. The current
is proportional to the multiplication of drift velocity and carrier concentration in the channel [10]. This requires correct selection of
Lg, Vdd, and device architecture in order to maximize this multiplication, where the selection of those parameters will be different
for the type of channel material used. This all needs to be holistically tackled [11]. A shift in the centroid of charge away from the
gate potential adds to the equivalent oxide thickness (EOT), reducing the inversion capacitance, particularly in IIIV high-mobility
channels. Despite the fact that drive current of IIIV might not be that high, the overall delay merit (CV/I) can result better than the
ones of Si and other high-mobility channels (e.g. Ge). Strain engineering is an additional knob to boost mobility on top of highmobility channels. In fact this knob has been used as one of the most effective knobs in the last decade (Figure 5) [12]. With the
scaling down of contacted poly pitch, SiGe on the S/D EPI contact and strain relaxation buffer (SRB) remain as effective boosters to
scale mobility more than double on top of high-mobility channel material [13].

Figure 4: Intrinsic mobility of different materials.

Figure 5: Impact of strain engineering on device performance [12].

Reducing parasitics: Controlling source/drain series resistance within tolerable limits will become much more difficult. Due to
the increase of current density, the demand for lower resistance with smaller dimensions at the same time poses a great challenge. It
is estimated that in current technologies, series resistance degrades the saturation current by 40% and more from that of ideal case.

This proportion will likely become harder to maintain or worse with the poly pitch scaling and also increasing interconnect resistance
by scaling, will all leaving less headroom for the device contact itself. In order to maximize the benefits of high-mobility channels in
the drain current, it gets much more important to reduce the contact resistance. Silicide contacts are getting off-stream in maintaining
the required reduction of contact resistance with the poly pitch scaling and decreasing channel resistance with improved drive. One
promising reduction is achieved by MIS contacts, which utilize an ultra-thin dielectric between the metal and semiconductor interface.
This reduces the Fermi level pinning and therefore reduces the Schottky Barrier Height (SBH) [14]. This SBH reduction happens by
the exponential decay of the metal induced gap states (MIGS) induced charge density in the bandgap of the dielectric.Parasitic
capacitance between gate and source/drain terminal of the device is increasing with technology scaling and exceed the channel
capacitance as the poly pitch is scaled down. There is a need to focus on low-k spacer materials that still provide good reliability and
etch selectivity for S/D contact formation.
Increasing drive per footprint: FinFET and lateral nanowires enable a higher drive at unit footprint (by enabling drive in the
third dimension) if fin pitch can be aggressively scaled. This increased drive at unit footprint by scaling the fin pitch comes at a tradeoff between fringing capacitance between gate and contact and series resistance.
Improving electrostatics and device isolation: FinFET has better electrostatics integrity due to its tall narrow channel that is
controlled by a gate from three-sides where this allows relaxing the scaling requirements of fin thickness (i.e. body thickness)
compared to UTBB FDSOI. In UTBB FDSOI electrostatic control could be done by using silicon (i.e. body) thickness and BOX
thickness where convergent scaling of both silicon thickness and BOX thickness enables electrostatics scaling (DIBL < 100 mV/V)
down to Lg beyond 10 nm. Thick buried oxide (Tbox) and thin Si (Tsi) scalings are typically kept at compromise between
manufacturability and short-channel-effects control. Junction implantation engineering, EOT scaling, and density of interface traps
(Dit) reduction are potential solutions to maintain the electrostatics control in the channel [15]. Besides the channel leakage induced
by electrostatics, there are potentially other leakage sources such as sub-fin leakage. This leakage current flows through the bottom
part of the fin from source to drain (Figure 6). This gets more problematic in Ge channels because of low effective mass of Ge.
Ground plane doping and quantum well below the channel will potentially solve this leakage problem; therefore improving the
electrostatics [16].

Figure 6: Sub-fin leakage in Si and Ge channels [16].

Reducing process and material variations: Reducing variability would further allow Vdd scaling. Controlling channel length
and channel thickness are important to maintain the electrostatics in the channel. This would require for instance controlling the
profile of the fin and lithography processes to reduce the CD uniformity (CDU), line width roughness (LWR), line edge roughness
(LER). Dopant-free channel and low-variability work-function metals would variations in the threshold voltage. With the introduction
of high-mobility materials gate stack passivation is needed to reduce the interface related variations as well as maintaining the
electrostatics and mobility.
Transition to new device architectures: These extensions to the existing device architectures such as finFET will sustain the
same device architecture for 1 or 2 nodes until the end of 2019. Beyond 2019 a transition to gate-all-around (GAA) and potentially
to vertical nanowires devices will be needed when there will be no room left for the gate length scale down due to the limits of fin
width and contact width.

ROADMAP
PIDS roadmap focuses on effective knobs to sustain the performance scaling at scaled dimensions and scaled supply voltage.

Figure 7: Device roadmap enabling More Moore: 1) ground rules and device structure, 2) performance boosters.

4. AREA SCALING (LITHOGRAPHY TWG)

Area scaling is dependent on the solution of roadblocks seen in Lithography.
The Lithography Technology Working Groups mission is to identify lithographic options for future semiconductor nodes and to
describe the driving forces for their implementation and the challenges to their implementation. We also work with other TWGs so
that their roadmaps incorporate lithographic capabilities and constraints.

KEY CHALLENGES
Both double and quadruple patterning using immersion ArF lithography have now been demonstrated as manufacturing capable
patterning methods. Major semiconductor makers have said that they use can multiple patterning for near-in manufacturing nodes
without any additional patterning methods being used. However, as multiple patterning is extended to more complicated levels and
used for smaller dimensions, it requires many additional masks, especially for contact hole layers and for cut exposures. It also puts
constraints on design that force the use of more chip area for a given number of circuits. Both of these consequences increase chip
costs and mean that future devices may not be cheaper on a per device basis. This would be a change from the historical trends of
the semiconductor industry; where, in the past, reducing dimensions automatically improved costs. So the first challenge of any
future patterning technique is to reduce costs per device or to make device design simpler, which also ultimately reduces device costs.
Possible new patterning methods being worked on in industry are direct write e-beam lithography (known as maskless lithography),
directed self-assembly (DSA), nanoimprint and EUV lithography. Besides the challenges of cost, key challenges for any of these
methods to succeed are defectivity, masks, throughput and pattern placement or overlay. Defectivity can be an issue either for the
printed pattern itself or for making the masks or other parts or materials related to the new technique. Each of these methods has
their own particular challenges and roadblocks as discussed below.

POTENTIAL ROADBLOCKS
The strengths and weaknesses of the four leading next generation patterning methods are shown in the radar charts shown in
Figure 8. In the radar charts each radius leading to a vertex represents how well the attribute represented by that vertex is ready for
manufacturing. A point closer to the outside is more ready for manufacturing than one near the inside. A point on the edge of the red
are means that manufacturing solution are NOT known. A point on the outer edge of the yellow area means that manufacturable
solutions are known. A point on the outside of the green area means that manufacturable solutions exist, and are being optimized.
The charts enable a quick picture of how ready each technology is for volume manufacturing. Each method has very different
strengths and weaknesses and the key roadblocks for each one are different.
Maskless lithography requires a tool that writes with thousands of e-beams simultaneously. Massively parallel ebeam writing
systems are needed because single e-beam direct write is an intrinsically slow process. A multibeam approach has been demonstrated
for mask making, but requires on the order of half a day to write one state of the art mask pattern. Writing chip patterns has to be
orders of magnitude faster than this if maskless lithography is to be a usable production tool. If writing is faster, pattern placement
is much harder; so key roadblocks for maskless lithography are throughput and pattern placement. Actual tool design and
demonstration of reasonable throughput with good pattern properties is the key technical accomplishment needed for semiconductor
producers to commit to it for manufacturing use. Even though direct write e-beam can have very high resolution, the minimum pixel
size such a tool can write is fixed by the tools initial design. So if a tool misses availability for its intended node, the resolution will
not be sufficient for critical levels of the next node, making tool resolution a secondary issue for implementation. Inspection of
wafers written in maskless approach may require additional inspection, since each exposure field could have different defects. This
may also affect wafer throughput. But even with limited resolution capability, such tools could still find use for patterning non critical
levels if they miss the window for use on leading edge critical level patterning, especially for chip designs with limited production
runs, where maskless lithography might be cost effective to replace many patterning levels.
Directed self-assembly works by using special polymeric materials that phase separate into regions of different composition when
annealed. A guide pattern printed by some patterning method such as immersion lithography is used to make sure the different phases
will separate where they are needed. The different regions have different etch or chemical resistance properties, and one of the
phases can be selectively removed during etch or other post processing. Defects of particular concern in DSA are incomplete
annealing, where the phases dont separate into the required locations everywhere on the wafer, and three dimensional defects, where
some defect or defects in the guiding structures causes improper three dimensional phase separation structures. No one has yet
demonstrated full wafer defectivity sufficient for manufacturing. However, active work in this area has shown considerable progress.
Inspection of some defects is complicated by their three dimensional nature. Some possible defects look good from top down
inspection but will not result in good circuit patterns. So key roadblocks to implementation are defectivity and inspection. If these
roadblocks can be overcome, directed self-assembly has a good cost and throughput profile. But DSA friendly designs will be
mandatory and will take time to become part of chip design infrastructure. Like multiple patterning designs, these designs will
almost certainly increase the silicon area a circuit requires. This will add cost to the process.
Nanoimprint works by a physical process of stamping a pattern in a liquid and then curing the liquid before removing the mold.
The resolution and LWR are excellent and limited only by the quality of the mask. It is a contact printing method and so is susceptible
to defects. Unlike conventional lithography , the masks are the same dimensions (1X) as the printed pattern. This puts stress on
pattern placement in mask making. A complicated system of master and secondary masks is used to reduce accumulated defects and
significant progress has been made in lowering defects. But defects are not at manufacturing capable levels yet. Its easier to get
low defects if the process is done slowly, so throughput is also an issue. Overlay is accomplished by stretching the mask slightly
and has been reported to be as low as 8nm, but this is larger than needed for future critical levels. So defects, throughput and pattern
placement are the key roadblocks for this technology to succeed.

EUV lithography is like optical lithography in that a projection step and scan imaging process is used with a 4X reduction in
dimensions from mask to wafer. But the physics of EUV light requires vacuum exposure, multilayer reflective masks and make
constructing a bright enough source for reasonable throughput very difficult. Light source power and mask defectivity are the two
biggest roadblocks for EUV implementation. Substantial progress was reported in 2014 on these two roadblocks. For the first time
in 10 years of EUV development, EUV tools are capable of enough throughput to make pilot production possible. This is encouraging,
but throughput still has to be improved further to make EUV economical enough for mass production. Mask blank defects have also
improved, but there is still only a limited infrastructure for making EUV mask blanks. Other EUV needs are an improved EUV mask
infrastructure and resists that have an improved photospeed to LWR tradeoff. Low defect EUV mask blanks have been demonstrated
recently, but are not available in production volumes. Production tool throughput is specified by the manufacturer assuming 20mJ/cm2
photoresist. However, the typical actual resist in use now has a slower photospeed of about 50 or 60mJ/cm2 in order to get adequate
performance.

Figure 8: Strengths and weaknesses of patterning methods.

POTENTIAL SOLUTIONS ROADMAP

Potential solutions are shown in Table 2 together with their first possible application in manufacturing and date of use. The dates
in the last column are our estimates for when a semiconductor manufacturer needs to make an irreversible commitment to that
technology for it to be ready in time for planned manufacturing. We consider that a two year pilot stage with a fixed patterning
technology is normal for chip development. For nanoimprint, industry sources indicate that pilot scale use is already underway, so
the decision time frame shown indicates when a capital commitment needs to be made for volume use in 2016. EUV requires a
substantial investment in buildings and tools, so the time frame shown is a little longer than two years from decision to manufacturing.
Multiple patterning with ArF immersion is included in the table as the baseline process that other patterning methods have to
compete with. Since it is already demonstrated that quadruple patterning can be used in manufacturing, the key date for multiple
patterning progress relates to when octuple patterning will first be needed. This is expected to be in 2019 for patterning of 5nm logic
node fins.
The 10nm logic node design rules are already being finalized, so the first implementations of 10nm parts will be made with
multiple patterning, not EUV. However, EUV could still be used to lower costs, shrink or otherwise extend the capability of 10nm
logic node designs, if EUV throughput and defects prove sufficient. Otherwise, EUVs first manufacturing opportunity will be for
7nm node logic devices in 2018 or potentially for DRAMs in the same time frame.

Nanoimprint is being developed for semiconductor use by a private alliance of companies who have not publicized their progress.
It is hard to tell how far along it is in addressing roadblocks. However, participants in its development state that it is targeted for use
in 14nm planar flash memory production.
DSAs first application is likely to be contact holes or cuts for DRAM and Logic in 2017 or 2018. A decision to use it in
manufacturing would need to be made next year. Since pilot quantities of materials are already available and active defect reduction
work has already been reported, this seems doable. The key question is there enough benefit and performance for DSA that a
semiconductor manufacturer will be willing to modify their designs and possibly their pattern placement requirements to make DSA
use feasible.
For maskless lithography the schedule for availability of a beta tool is 2016. If that demonstrates enough feasibility, mask less
lithography could be in production in 2018 for contact holes or cut levels in 7nm node logic parts.

Table 2: Potential solutions.

INTERACTION WITH FOCUS TEAMS/iTWGS

IRC:
The lithography roadmap cannot be completed without knowing the device roadmap and requested CDs. Since lithography
can affect what CDs can be printed in what time frame, IRC needs to interact with lithography. This interaction is essential
for both groups.

More Moore:
Lithography is a component of More Moore and has to give input to the More Moore roadmap. This interaction is essential
for both groups.

Design, PIDS, Interconnect and Metrology:

Design, process and chip layout are strongly affected by what sorts of patterns lithography can print. In addition various
parameter requirements, such and LWR and overlay are driven by process and device needs. So interaction with these teams
is essential. This interaction is essential for both groups. Metrology has to know the future testing requirements for critical
dimension structures, so lithography has to communicate expected dimensions and requirements to them. Metrology also
needs to know of any process constraints that require potential new overlay measurement patterns or segmentation.

ERM/ERD:

Lithographic progress can be very dependent on new materials, particularly with DSA, but also with new types of resists.
ERM also needs input on lithographic needs to make sure that related materials are in the ERM roadmap.
New devices affect what sort of lithography is needed. For example, the introduction of finFETs to logic devices reduced the
minimum half pitch in a logic device by 25% and provided a new type of layer to pattern. Lithography needs to be aware of
new devices to make sure new lithographic requirements driven by them are included in the lithographic roadmap.

Other iTWGs:
Occasional interaction with factory integration, FEP, EHS and yield groups is useful.

5. MANUFACTURING CHALLENGES OF NEW DEVICE

ARCHITECTURES (FEP TWG)
KEY CHALLENGES
As pointed out in the previous section. A transition to new device architectures such as GAA is needed to continue the
scaling, particularly beyond 2019. Following tables list the associated challenges of manufacturing GAA devices.
Table 3: Difficult challenges of GAA manufacturing.
Difficult challenges
Transition from fin to
GAA
Strain engineering for
GAA devices

Junction engineering
High mobility material
integration

Starting substrates

Etch

Material deposition

Cleans
CMP

Opportunities and issues

Extension of fin processes
Need to deal with higher aspect ratio starting topography
Continued use of embedded epitaxy for channel mobility boost
GAA mobility enhancements
Integration of dual channel materials
Usage of sSOI substrates and stress conversion through condensation techniques
In vertical GAA architectures new techniques are needed to induce channel stress (eg reintroduction of
stressed liners)
reducing junction concentration and achieving dopant redistribution
Conformal doping solutions are needed, increased importance for GAA or NW architectures
different materials needed for NFET and PFET which leads to significant challenges to co integrate the
materials
process solutions need to be compatible with material requirements such as low temperatures needed for post
processing steps and new requirements on limiting the material losses in the subsequent processing steps
the materials used need to have low defectivity requirements (no killer defects in the channel)
GAA architectures can potentially be easier integrated and with less parasitics on SOI, sSOI, thin SOI
substrates
Substrates for high mobility solutions cost and defectivity are issues that will need to be addressed
high aspect ratio deep trenches, high pillars
high selectivity requirements compatible with the aggressive ground rules
GAA architectures and the need to eliminate parasitics drive the requirements for directional etching
Improved LER, etch bias and loading
Gate recess control and uniformity driven by the aggressive ground rules and yield requiremens
Very high conformality processes are needed to wrapa round gate materials around the wires
High aspect ratio fill capability is needed (taller and thinner structures)
Gate fill solutions for sub 20 nm gates with acceptable gate resistance
Contact metal deposition solutions for increased aspect ratio contacts (vertical devices)
TDDB requirements (smaller distances needed between gate and contacts drive the requirements for the
insulator materials used)
Good clean or removal without any residual defects or material removal

Control and uniformity for gate and contact

Higher starting topography
Both non selective and highly selective slurries

6. PROCESS CONTROL REQUIREMENTS (METROLOGY TWG)

Manufacturing process control of advanced device require metrology. The Metrology Technology Working Groups mission is
to identify emerging measurement challenges and describe research and development pathways for meeting them, primarily for
extending CMOS, accelerating Beyond CMOS technologies, materials characterization and structure function relationships.
Metrology also provides the measurement capability necessary for cost-effective manufacturing.

KEY CHALLENGES

Starting materials metrology and manufacturing metrology are impacted by the introduction of new substrates
based on SOI, III-V, GeOI, etc. Impurity detection (especially particles) at levels of interest for starting
materials and reduced edge exclusion for metrology tools are needed.

Measurement of complex material stacks and interfacial properties including physical and electrical properties.

Factory level and company-wide metrology integration for real-time in situ, integrated, and inline metrology
tools; continued development of robust sensors and process controllers; and data management that allows
integration of add-on sensors.

Metrology for Directed Self Assembly (DSA).

Control of new process technology such as Directed Self Assembly Lithography, complicated 3D structures
such as FinFET and MuGFET transistors, capacitors and contacts for memory, and 3D Interconnect are not
ready for their rapid introduction.

Measurement test structures and reference materials are needed.

Nondestructive, production worthy wafer and mask-level metrology for CD measurement for 3D structures,
overlay, defect detection, and analysis

Structural and elemental analysis at device dimensions and measurements for beyond CMOS, and emerging
materials and devices.

Determination of manufacturing metrology when device and interconnect technology remain undefined.

KEY CHALLENGES AND POTENTIAL SOLUTIONS

Table 4: Difficult challenges and potential solutions.

Difficult Challenges

Potential Solutions

Starting materials metrology and manufacturing

metrology are impacted by the introduction of new
substrates based on SOI, III-V, GeOI, etc.

Enhancement capability for SOI, III-V, GeOI wafers.

detection (especially particles) at levels of interest

Impurity

Measurement of complex material stacks and

interfacial properties including physical and electrical
properties.

Reference materials and standard measurement methodology for

complex material stacks and interfacial properties including physical
and electrical properties.

Control of new process technology such as Directed

Self Assembly Lithography, complicated 3D
structures such as FinFET & MuGFET transistors,
capacitors and contacts for memory, and 3D
Interconnect. Figure 9 shows a simplified model of a
finfet. To obtain a full 3D profile of the feature above,
measurements such as fin CD, height, sidewall angle
and roughness, and film thickness.

Introduction of inline 3D metrology for dimensional, compositional,

and doping measurements.

Factory level and companywide metrology

integration for real-time in situ, integrated, and inline
metrology tools;

Standards for process controllers and data management must be agreed

upon. Conversion of massive quantities of raw data to information
useful for enhancing the yield of a semiconductor manufacturing
process.

Nondestructive, production worthy wafer and masklevel metrology for CD measurement for 3D
structures, overlay, defect detection, and analysis

Imaging and scattering techniques available for any given process

control situation.

New strategy for in-die metrology must reflect across

chip and across wafer variation.

Sampling plan optimization and correlation of test structure variations

with in-die properties as devices shrink.

Statistical limits of sub-12 nm process control.

Controlling processes where the natural stochastic
variation limits metrology. Examples are low-dose
implant, thin-gate dielectrics, surface, sidewall and
edge roughness of very small structures.

Increased use of complementary and hybrid metrology combined with

state of the art statistical analyses would be required to reduce the
measurement uncertainty. Figure 10 shows a conceptual diagram of
hybrid metrology.

Structural and elemental analysis at device

dimensions and measurements for beyond CMOS,
and emerging materials and devices.

Materials characterization and metrology methods for control of

interfacial layers, dopant positions, defects, and atomic concentrations
relative to device dimensions.

Directed Self Assembly (DSA)

Clear definition of material and system dependent measurands.

Metrology to detect low densities of surface and buried defects.

Mask defects, especially for EUV.

Solution for non-visible defects, film thickness non-uniformity, phase

separation, and reflectivity.

POTENTIAL ROADBLOCKS
FEP

Measurement capability for SOI, III-V, GeOI wafers needs enhancement. Some of the challenges come from
the extra optical reflection in SOI and the surface quality. Critical dimensions, film thickness, and defect
detection are impacted by thin SOI optical properties and charging by electron and ion beams.

Carrier mobility characterization will be needed for stacks with strained silicon and SOI, III-V, GeOI, and other
substrates, or for measurement of barrier layers. Characterization techniques for metal gate work function are
also needed.

Lithography

The area available for test structures is being reduced, especially in the scribe lines. Measurements on test
structures located in scribe lines may not correlate with in-die performance.

Surface charging and contamination interfere with electron beam imaging. CD measurements m

ust account for overall feature profile. It is important to have both imaging and scattering techniques available
for any given process control situation. Focus, exposure, and etch bias control will require better precision and
3D capability than are currently available.

In directed self-assembly, key measurands such as size, location, and alignment are not well defined. Some of
the measurands are not only material and system dependent, but are similar enough that identifying a property
with the required contrast may be difficult.

Yield

Mask defects, especially for EUV will continue to be a challenge. These include non-visible defects, film
thickness non-uniformity, phase separation, and reflectivity.

Factory

Standards for process controllers and data management must be agreed upon. Conversion of massive quantities
of raw data to information useful for enhancing the yield of a semiconductor manufacturing process is a
potential problem.

Figure 9: Complex structures such as finFETs require 3D metrology. To obtain a full 3D profile of the feature above, measurements such as fin CD,
height, sidewall angle and roughness, and film thickness are needed. Figure courtesy of Benjamin Bunday, SEMATECH.

Figure 10: Conceptual diagram of hybrid metrology. Different instruments provide specific model parameters that are used in a generalized
model of the measurement. The arrows indicate specific information from different instruments. Figure courtesy of Richard Silver NIST.

INTERACTION WITH FOCUS TEAMS/ITWGS

Close interaction between metrology and other Focus Teams and iTWGs is necessary. Table 2 prioritizes the level of interaction
needed between the Metrology TWG and the focus Teams/ITWGS listed. This list or priority level is by no means static, the
metrology TWG will continue to seek out and engage with other Focus Teams/ITWGs on topics of mutual interest.

Table 5: Interaction with other Focus Teams/iTWGs.

7. INTERCONNECT SCALING
KEY CHALLENGES
Table 6 highlights and differentiates the top key challenges. The most difficult challenge for interconnects is the introduction of
new materials that meet the wire conductivity requirements and reduce dielectric permittivity. As for the conductivity, the impact of
size effects on interconnect structures must be mitigated. Future effective requirements preclude the use of a trench etch stop for
dual damascene structures. Dimensional control is a key challenge for present and future interconnect technology generations and
the resulting difficult challenge for etch is to form precise trench and via structures in low- dielectric material to reduce variability
in RC. The dominant architecture, damascene, requires tight control of pattern, etch and planarization. To extract maximum
performance, interconnect structures cannot tolerate variability in profiles without producing undesirable RC degradation. These
dimensional control requirements place new demands on high throughput imaging metrology for measurement of high aspect ratio
structures. New metrology techniques are also needed for in-line monitoring of adhesion and defects. Larger wafers and the need to
limit test wafers will drive the adoption of more in situ process control techniques.
Table 6: Interconnect difficult challenges.

Critical Challenges
Materials
Mitigate impact of size effects in interconnect
structures
Metrology
Three-dimensional control of interconnect features
(with its associated metrology) will be required
Process
Patterning, cleaning, and filling at nano dimensions
Complexity in Integration
Integration of new processes and structures,
including interconnects for emerging devices
Practical Approach for 3D
Identify solutions which address 3D interconnect
structures and other packaging issues

Summary of Issues
Line and via sidewall roughness, intersection of porous low- voids with
sidewall, barrier roughness, and copper surface roughness will all adversely
affect electron scattering in copper lines and cause increases in resistivity.
Line edge roughness, trench depth and profile, via shape, etch bias, thinning
due to cleaning, CMP effects. The multiplicity of levels, combined with new
materials, reduced feature size and pattern dependent processes, use of
alternative memories, optical and RF interconnect, continues to challenge.
As features shrink, etching, cleaning, and filling high aspect ratio structures
will be challenging, especially for low- dual damascene metal structures and
DRAM at nano-dimensions.
Combinations of materials and processes used to fabricate new structures
create integration complexity. The increased number of levels exacerbate
thermomechanical effects. Novel/active devices may be incorporated into the
interconnect.
Three-dimensional chip stacking circumvents the deficiencies of traditional
interconnect scaling by providing enhanced functional diversity. Engineering
manufacturable solutions that meet cost targets for this technology is a key
interconnect challenge.

ROADMAP AND POTENTIAL SOLUTIONS

Table 7: Interconnect roadmap for scaling.
2013-15

2016-18

2019-21

2022-24

2025-27

2028-30

Node

N14

N10

N7

N5

N3

N1.5

Ground rules (CPP, MP, FP, LG)

- [nm]

70, 52,
42,20

52, 42,
30, 16

36, 30,
21, 14

25, 21,
14, 12

18, 14,
10, 10

12, 10,
7, 8

Conductor

Cu

Cu

Cu

Cu,
Silicides,
Carbon,
Collective
Excitations

Cu,
Silicides,
Carbon,
Collective
Excitations

Cu,
Silicides,
Carbon,
Collective
Excitations

Barrier Metal

Ta(N)

Ta(N),
Mn(N)

Ta(N),
Mn(N)

Ta(N),
Mn(N),
SAM

Ta(N),
Mn(N),
SAM

Ta(N),
Mn(N),
SAM

IMD (Inter-metal dielectrics)

and k values

SiCOH (2.55)

SiCOH
(2.40-2.55),
Airgap (1.0)

SiCOH
(2.20-2.55),
Airgap (1.0)

SiCOH
(2.20-2.55),
Airgap, (1.0)
MOF, COF

SiCOH
(2.00-2.55),
Airgap, (1.0)
MOF, COF

SiCOH
(1.80-2.55),
Airgap, (1.0)
MOF, COF

Conductor: Cu will be the preferred solution for the M1 and Mx levels. Although a resistivity increase due to electron scattering
is already apparent, a hierarchical wiring approach such as scaling of line length along with the that of the width still can overcome
the problem. As the alternative materials, two directions are proposed. One is the usage of the metals with less size effect e.g. silicides
and the other is the introduction of materials that have different conductance mechanism e.g. carbon and collective excitations. The
latter materials are still in R&D phase to implement to the semiconductor.
Barrier Metal: Cu wiring barrier materials must prevent Cu diffusion into the adjacent dielectric but also must form a suitable,
high quality interface with Cu to limit vacancy diffusion and achieve acceptable electromigration lifetimes. Ta(N) is a well-known
industry solution. Although the scaling of Ta(N) deposited by PVD is limited, other nitrides such as Mn(N) which can be deposited
by CVD or ALD have recently attracted attention. As for the emerging materials, SAM (Self-Assembled Monolayers) are researched
as the candidates for future generation.
IMD (Inter-metal Dielectrics): Reduction of the ILD value is slowing down because of problems with manufacturability. The
poor mechanical strength and adhesion properties of lower- materials are obstructing their incorporation. Delamination and damage
during CMP are major problems at early stages of development, but for mass production, the hardness and adhesion properties needed
to sustain the stress imposed during assembly and packaging must also be achieved. The difficulties associated with the integration
of highly porous ultra-low- ( 2) materials are becoming clearer, and air-gap technologies is the alternative path to lower the interlayer capacitance. As the emerging materials, MOF (Metal Organic Framework) and COF (Carbon Organic Framework) are
advocated.
Reliability-EM (Electromigration): An effective scaling model has been established assuming that the void is located at the
cathode end of the interconnect wire containing a single via with a drift velocity dominated by interfacial diffusion as shown in Figure
11. The model predicts that scales with w*h/j, where w is the linewidth (or the via diameter), h the interconnect thickness, and j the
current density. Whereas the geometrical model predicts that the lifetime decreases by half for each new generation, it can also be
affected by small process variations of the interconnect dimensions. Jmax (The maximum equivalent dc current density) and JEM (The
maximum current density) limited by the interconnect geometry scaling is shown in Figure 14. Jmax increases with scaling due to
reduction in the interconnect cross-section and increase in the maximum operating frequency. The practical solutions to overcome
the lifetime decrease in the narrow linewidths are discussed actively over the past years. Recent studies show an increasingly
important role of grain structure in contributing to the drift velocity and thus the EM reliability beyond the 45nm node. Process
options with Cu alloys seed layer (e.g., Al or Mn) have shown to be an optimum approach to increase the lifetime. Other approaches
are the insertion of a thin metal layer (e.g CoWP or CVD-Co) between the Cu trench and the dielectric SiCN barrier and the usage
of the short length effect. The short length effect has effectively been used to extend the current carrying capability of conductor lines
and has dominated the current density design rule for interconnects.
Reliability - TDDB (Time Dependent Dielectric Breakdown): Basically, the dielectric reliability can be categorized according to
the failure paths and mechanisms as shown in Figure 3. While a large number of factors and mechanisms have already been identified,
the physical understanding is far from complete.

Figure 11: Experiment and model of lifetime scaling versus interconnect geometry

Figure 12: Evolution of Jmax (from device performance) and JEM (from targeted lifetime)

Figure 13: Degradation paths in low-k damascene structure.

8. MORE MOORE ROADMAP TOWARDS ITRS 2.0

As the applications strictly requiring all figure-of-merits (FoMs) concurrently met, it is necessary to come along effective list of
knobs for sustaining certain device architecture to its limits. This approach will also help in sustaining the cost while moving from
one logic generation to another. Particularly this gets more important whenever the cost of wafer processing is getting more expensive
with the increased number of steps as an outcome of the multiple patterning lithography steps (Figure 14). However, we need to
reduce the cost by 35-40% for the same of number of transistors, which can only be enabled by aggressive pitch scaling due to new
advancements in channel material, device architecture, contact engineering, and device isolation. However, increased process
complexity must also be taken into account for the overall die yield.

Figure 14: Number of transistors that can be bought by $1. Source: Linley Group.

Will all inputs from TWGs and interaction with other Focus Teams our aim is to consolidate all technology roadmaps into More
Moore roadmap.

9. REFERENCES
[1]

M.E. Mason et al., Design enablement: the challenge of being early, accurate, and complete, VLSI, pp. 145-146, June 2012,

[2]

J.-A. Carballo, W.-T. J. Chan, P. A. Gargini, A. B. Kahng and S. Nath, ITRS 2.0: towards a re-framing of the semiconductor technology roadmap, Proc. ICCD,
October 2014.

[3]

W. Huang et al, Scaling with design constraints: predicting the future of big chips, IEEE Micro, Vol. 31, No. 4, pp. 16-29, Jul-Aug 2011.

[4]

ITRS 2011 edition. Source: public.itrs.net.

[5]

A. Keshavarzi et al, Architecting advanced technologies for 14nm and beyond with 3D FinFET transistors for the future SoC applications, IEDM, pp. 4.1.14.1.4, December, 2011.

[6]

Nanohub website (http://nanohub.org) and ITRS tools on Nanohub (https://nanohub.org/tools/itrs/).

[7]

MASTAR tool (http://www.itrs.net/Links/2011ITRS/MASTAR2011/), and downloading and installation instructions at:

(http://www.itrs.net/Links/2011ITRS/MASTAR2011/MASTARDownload.htm).

[8]

ITRS 2013 edition. Source: public.itrs.net.

[9]

A. Thean, Z. Tokei, Challenges of 10nm and 7nm CMOS Technologies, IEDM, December 2013.

[10] T. P. Ma, Beyond Si: opportunities and challenges for CMOS technology based on high-mobility channel materials, Sematech Symposium Taiwan,
September 2012.
[11] T. Skotnicki, F. Boeuf, How can high mobility channel materials boost or degrade performance in advanced CMOS, VLSI, pp. 153-154, June 2010.
[12] K. Kuhn et al. Past, present and future: SiGe and CMOS transistor scaling, Electrochemical society trans., Vol. 33, No. 6, pp. 13-17, 2010.
[13] G. Eneman et al., Stress simulations for optimal mobility group IV p- and nMOS finFETs for the 14nm node and beyond, IEDM, pp. 6.5.1-6.5.4, December
2012.
[14] K.-W. Ang et al., Effective Schottky barrier height modulation using dielectric dipoles for source/drain specific contact resistivity improvement, IEDM, pp.
18.6.1-18.6.4, December 2012.
[15] J. Mitard et al., 15nm-wfin high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process, VLSI, pp. 1-2, June 2014.
[16] G. Eneman et al., Quantum barriers and ground-plane isolation: a path for scaling bulk-finFET technologies to the 7nm node and beyond, IEDM, pp. 12.3.112.3.4, December 2013.
[17] S. Kosonocky et al., Designing in Scaled Technologies: 32nm and Beyond, VLSI, pp. 147-148, June 2012.
[18] K. Arabi, Low power design techniques in mobile processes ISLPED, pp. 1-2, August 2014.

10.

MEMBERS

PIDS TWG Members

The PIDS TWG is composed of members from industry (device makers, materials producers and tool vendors),
academia, and research organizations. As key logic technology challenges evolve, the TWG will continue to
seek and recruit contributors to ensure the group has the expertise it needs to meet its mission. The list below
includes active members, contributors, and meeting participants within the 2014 and 2015.

Yasushi Akasaka (TEL)

Dimitri Antoniadis (MIT)
Mustafa Badaroglu (Qualcomm), PIDS TWG lead, EU
Gennadi Bersuker (SEMATECH)
Frederic Boeuf (ST)
Azeez Bhavnagarwala (IBM)
Joe Brewer (Univ. Florida)
Alex Burenkov (Fraunhofer IISB)
Jeff Butterbaugh (FSI Int.)
Chorng-Ping Chang (Applied Materials) logic US lead
Kin (Charles) Cheung (NIST) reliability US co-lead, logic
US co-lead
Kristin De Meyer (IMEC)
James Fonseca (Purdue Univ.)
Yuzo Fukuzaki (Sony Corp.), logic Japan lead,
Toshiro Futatsugi (Fujitsu Semiconductor)
William (Bill) J. Gallagher (IBM)
Yasushi Gohou (Panasonic)
Christopher Henderson (Semitracks)
Michel Haond (ST)
Yoshihiro Hayashi (Renesas)
Toshiro Hiramoto (Univ. of Tokyo)
Digh Hisamoto (Hitachi)
Jim Hutchby (SRC)
Jiro Ida (Kanazawa IT)
Hirofumi Inoue (Toshiba), NVM Japan co-lead, DRAM
Japan lead
Kunihiko Iwamoro (Rohm)
Herve Jaouen (ST)
Moon-Young Jeong (Samsung)
Malgorzata Jurczak (IMEC)
Naoki Kasai (Tohoku Univ.
SunGeun Kim (Intel)
Gerhard Klimieck (Purdue Univ.)
Fred Kuper (NXP)
Hajime Kurata (Fujitsu)
Chung Lam (IBM)
Robert Lander (NXP)
Laurent Le-Pailleur (ST)

Rich Liu (Macronix), NVM Taiwan co-lead

Witek Maszara (Global Foundries)
Jurgen Lorenz (Fraunhofer)
Saumitra Mehrotra (Purdue Univ.)
Tohru Mogami (NEC)
Kwok Ng (SRC), logic US co-lead
Tak Ning (IBM)
Masaaki Niwa (U. Tsukuba)
Tony Oates (TSMC)
Hidekazu Oda (Renesas), logic Japan co-lead
Sang Hyun Oh (SK Hynix)
Tatsuya Ohguro (Toshiba)
Jongwoo Park (Samsung)
Thierry Poiroux (CEA-LETI)
Siddharth Potbhare (NIST)
Kirk Prall (Micron)
Xiang Qi (Xilinx)
Mehdi Salmani Jelodar (Sandisk)
Pan Sam (TSMC)
Prasad Saranhapani (Purdue Univ.)
Thomas Schulz (Intel)
Saurabh Sinha (ARM)
Eric S. Snyder (MKS Inst.)
James Stathis (IBM)
Toshihiro Sugii (Fujitsu)
Shinichi Takagi (Univ. Tokyo)
Tetsu Tanaka (Tohoku Univ.)
Cheng-tzung Tsai (UMC)
Wilman Tsai (Intel)
Philip Wong (Stanford Univ.)
Yanzhong Xu (Altera)
Geoffrey Yeap (Qualcomm)
Hitoshi Wakabayashi (Tokyo Inst. Technology)
Makoto Yoshimi (Soitec)
Scott Yu (TI)
Peter Zeitzoff (Toshiba)

Lithography TWG Members

The lithography TWG is composed of members from industry (device makers, materials producers and tool
vendors), academia, and research organizations. As key lithography challenges evolve, the TWG will continue
to seek and recruit contributors to ensure the group has the expertise it needs to meet its mission. The list
below includes active members, contributors, and meeting participants within the 2013 and 2014.

Tsukasa Azuma
Chris Bencher
Tatsuo Chijimatsu

Brian Cha
Will Conley
Ralph Dammel

Greg Denbeaux
Anton deVilliers
Masayuki Endo
Nigel Farrar
Ted Fedynyshyn
Heiko Feldmann
Emily Gallagher
Mike Garner
Reiner Garreis
Cesar Garza
TS Gau
Bob Gleason
Frank Goodwin
Roel Gronheid
Naoya Hayashi
Long He
Yoshiaki Ikuta
Rik Jonckeere
Hyungsang Joo
Franklin Kalk
Kunihiko Kasama
Patrick Kearney
Insung Kim
Sachiko Kobayashi
Christof Krautschik
Y.C. Ku
Keishiro Kurihara
Jongwook Kye
David Kyser
Michael Lercel
ChangMoon Lim
Shy-Jay Lin
Lloyd Litt
Greg McIntyre
Dan Millward, Matt Malloy
Pawitter Mangat
Hiroaki Morimoto
Venkat Nagaswami

Hideo Nakashima
Patrick Naulleau
Mark Neisser
Katsumi Ohmori
Yasushi Okubo
Masahiko Okumura
Kazuya Ota
Laurent Pain
Eric Panning
Moshe Preil
Doug Resnick
Morty Rothschild
Yoshitake Shusuke
Mark Slezak
Osamu Suga
Kazuhiro Takahashi
Takao Tamura
Serge Tedesco
Raluca Tiron
Walt Trybula
Plamen Tzviatkov
Rick Uchida
Fumikatsu Uesawa
Mauro Vasconi
Keiji Wada
Phil Ware
John Wiesner
Jim Wiley
Grant Willson
Obert Wood
Stefan Wurm
Jiro Yamamoto
Tetsuo Yamaguchi
Pei-Yang Yan
Anthony Yen
JeongHo Yeo
John Zimmerman

Front-end processes (FEP) TWG Members

The FEP TWG is composed of members from industry (device makers, materials producers and tool vendors),
academia, and research organizations. As key FEP challenges evolve, the TWG will continue to seek and
recruit contributors to ensure the group has the expertise it needs to meet its mission. Please refer to the
member list from the FEP TWG chapter.

Metrology TWG Members

The metrology TWG is composed of members from industry (device makers and instrument vendor),
academia, and research organizations. As key metrology challenges evolve, the TWG will continue to seek
and recruit contributors to ensure the group has the expertise it needs to meet its mission. The list below
include active members, contributors, and meeting participants within the last three meting cycles.

Carlos Beitia (CEA LETI MINATEC)

Mark Berry (Metryx)
Benjamin Bunday (SEMATECH)
Hyun Mo Cho (KRISS)
Soo Bok Chin (Samsung)
Delphine Le Cunff (ST)

Alain Diebold (CNSE) Chair

Brendan Foran (Aerospace Corp.)
Christina Hacker (NIST)
Dick Hockett (Evans Analytical Group)
Karey Holland (FEI)
Adrian Kiermasz, (Metryx)

Stephen Knight (NIST Retired)

Masahiko Ikeno (Hitachi High-Tech)
Yun-Jung Jee (Samsung)
S. S. Kim (SK hynix)
Scott List (Intel)
Niwa Masaaki (Panasonic)
Philippe Maillot (ST)
Seong-Min Ma (SK hynix)
George Orji (NIST)

Yaw Obeng (NIST)

Brennan Peterson (Nanometrics)
Narender Rana (IBM)
David Seiler (NIST)
Yuichiro Yamazaki (Toshiba)
Wilfried Vandervorst (IMEC)
Victor Vartanian (SEMATECH)
Andras Vladar (NIST)

Interconnect TWG Members

The interconnect TWG is composed of members from industry (device makers, materials producers and tool
vendors), academia, and research organizations. As key interconnect challenges evolve, the TWG will
continue to seek and recruit contributors to ensure the group has the expertise it needs to meet its mission.
Please refer to the member list from the interconnect TWG chapter.