CONTENTS

S.No.

Topic

Page

1.

Acknowledgement

2.

Introduction

3.

180 nm Technology

4.

CMOS Fabrication Technology

5.

Proposed Circuit

13

6.

Simulation Results

25

7.

Conclusion

31

8.

Future Work

32

9.

Bibliography

33

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ACKNOWLEDGEMENT
It gives me immense pleasure to express my deepest sense of gratitude and sincere
thanks to my highly respected and esteemed guide Mrs. N Jayanthi, Dept. of
Electronics and Communication Engineering, Delhi Technological University, for her
valuable guidance, encouragement and help for completing this work. Without her
valuable support this project would not have been complete on time.
I also wish to express my gratitutes to Dr. S Indu, Dept. of Electronics and
Communication Engineering, Delhi Technological University for her kind hearted
support and guidance throught the project.

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INTRODUCTION
The pipelined analog-to-digital converter (ADC) has become the most popular ADC
architecture for sampling rates from a few megasamples per second (Msps) up to
100Msps+. Pipelined converters, like successive-approximation and algorithmic
converters, perform an iterative search for a digital code that accurately reflects the
analog input signal. However, rather than perform the iterations with a single analog
circuit, pipelined converters have a separate analog stage dedicated to performing each
iteration. All of the analog stages operate on every clock cycle, each operating on a
different input sample. Since iterations are performed simultaneously, the pipelined
converter operates -times faster than algorithmic converters and is capable of
outputting one conversion on every clock cycle. Therefore, pipelined converters are
generally applied when higher speed is desired than is achievable with algorithmic
converters. Although input samples are being processed in parallel, clock cycles are
required for each input sample to proceed through the entire pipeline. Hence, there is a
latency of clock cycles through pipelined converters, just as in algorithmic and
successive approximation converters.
Resolutions range from eight bits at the faster sample rates up to 16 bits at the lower
rates. These resolutions and sampling rates cover a wide range of applications,
including CCD imaging, ultrasonic medical imaging, digital receivers, base stations,
digital video (for example, HDTV), xDSL, cable modems, and fast Ethernet.
Applications with lower sampling rates are still the domain of the successive
approximation register (SAR) and integrating architectures, and more recently,
oversampling/sigma-delta ADCs. The highest sampling rates (a few hundred Msps or
higher) are still obtained using flash ADCs. Nonetheless, pipelined ADCs of various
forms have improved greatly in speed, resolution, dynamic performance, and low
power in recent years.

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4 | Page

180 nm TECHNOLOGY
The 180 nanometer (180 nm) process refers to the level of semiconductor process
technology that was reached in the 1999-2000 timeframe by most leading
semiconductor companies, like Intel, Texas Instruments, IBM, and TSMC.
The origin of the 180 nm value is historical, as it reflects a trend of 70% scaling every
23 years. The naming is formally determined by the International Technology
Roadmap for Semiconductors (ITRS).
Some
of
the
first CPUs manufactured
with
this
process
include Intel Coppermine family of Pentium III processors. This was the first
technology using a gate length shorter than that of light used for lithography (which
has a minimum of 193 nm).
Some more recent microprocessors and microcontrollers (e.g. PIC) are using this
technology because it is typically low cost and does not require upgrading of existing
equipment.

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CMOS FABRICATION PROCESS

In early 1960s the semiconductor manufacturing process was initiated from Texas and
in 1963 CMOS or complementary metal oxide semiconductor was patented by Frank
Wanlass. Integrated circuits are manufactured by utilizing the semiconductor device
fabrication process. These ICs are major components of every electrical and electronic
devices which we use in our daily life. Many complex and simple electronic
circuits are being designed on a wafer made of semiconductor compounds and mostly
silicon by using different fabrication steps.
The complementary of the Commodore Semiconductor Group (CSG) or Metal Oxide
Semiconductor (MOS) is called as CMOS technology. This technology is used in
developing the microprocessors, microcontrollers, digital logic circuits and many
other integrated circuits. It facilitates low- power dissipation and high-packing density
with very less noise margin. It is mostly used to build digital circuitry.
20 Steps of CMOS Fabrication Process
The CMOS can be fabricated using different processes such as:
N-well process for CMOS fabrication
P-well process
Twin tub-CMOS-fabrication process
The fabrication of CMOS can be done by following the below shown twenty steps, by
which CMOS can be obtained by integrating both the NMOS and PMOS transistors
on the same chip substrate. For integrating these NMOS and PMOS devices on the
same chip, special regions called as wells or tubs are required in which semiconductor
type and substrate type are opposite to each other.
A P-well has to be created on an N-substrate or N-well has to be created on a Psubstrate. In this article, the fabrication of CMOS is described using the P-substrate, in
which the NMOS transistor is fabricated on a P-type substrate and the PMOS
transistor is fabricated in N-well.
The fabrication process involves twenty steps, which are as follows:
Step1: Substrate
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Primarily, start the process with a P-substrate.

Step2: Oxidation
The oxidation process is done by using high-purity oxygen and hydrogen, which are
exposed in an oxidation furnace approximately at 1000 degree centigrade.

Step3: Photoresist
A light-sensitive polymer that softens whenever exposed to light is called as
Photoresist layer. It is formed.

Step4: Masking
The photoresist is exposed to UV rays through the N-well mask

Step5: Photoresist removal

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A part of the photoresist layer is removed by treating the wafer with the basic or acidic
solution.

Step6: Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through the open area made by the removal of
photoresist using hydrofluoric acid.

Step7: Removal of photoresist

The entire photoresist layer is stripped off, as shown in the below figure.

Step8: Formation of the N-well

By using ion implantation or diffusion process N-well is formed.

Step9: Removal of SiO2

Using the hydrofluoric acid, the remaining SiO2 is removed.

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Step10: Deposition of polysilicon

Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer of gate
oxide.

Step11: Removing the layer barring a small area for the Gates
Except the two small regions required for forming the Gates of NMOS and PMOS, the
remaining layer is stripped off.

Step12: Oxidation process

Next, an oxidation layer is formed on this layer with two small regions for the
formation of the gate terminals of NMOS and PMOS.

Step13: Masking and N-diffusion

By using the masking process small gaps are made for the purpose of N-diffusion.

9 | Page

The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for
the formation of the terminals of NMOS.

Step14: Oxide stripping

The remaining oxidation layer is stripped off.

Step15: P-diffusion
Similar to the above N-diffusion process, the P-diffusion regions are diffused to form
the terminals of the PMOS.

Step16: Thick field oxide

A thick-field oxide is formed in all regions except the terminals of the PMOS and
NMOS.

Step17: Metallization
Aluminum is sputtered on the whole wafer.

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Step18: Removal of excess metal

The excess metal is removed from the wafer layer.

Step19: Terminals
The terminals of the PMOS and NMOS are made from respective gaps.

Step20: Assigning the names of the terminals of the NMOS and PMOS

Fabrication of CMOS using P-well process:

Among all the fabrication processes of the CMOS, N-well process is mostly used for
the fabrication of the CMOS. P-well process is almost similar to the N-well. But the
only difference in p-well process is that it consists of a main N-substrate and, thus, Pwells itself acts as substrate for the N-devices.
Twin tub-CMOS Fabrication Process:

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In this process, separate optimization of the n-type and p-type transistors will be
provided. The independent optimization of Vt, body effect and gain of the P-devices,
N-devices can be made possible with this process.
Different steps of the fabrication of the CMOS using the twin-tub process are as
follows:
Lightly doped n+ or p+ substrate is taken and, to protect the latch up, epitaxial layer is
used.
The high-purity controlled thickness of the layers of silicon are grown with exact
dopant concentrations.
The dopant and its concentration in Silicon are used to determine electrical properties.

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THE PROPOSED CIRCUIT

DESIGN APPROACH
TOP DOWN APPROACH
A top-down approach (also known as stepwise design and in some cases used as a
synonym of decomposition) is used to analyse and design the pipelined ADC.
It essentially the breaking down of a system to gain insight into its compositional subsystems in a reverse engineering fashion. In a top-down approach an overview of the
system is formulated, specifying but not detailing any first-level subsystems. Each
subsystem is then refined in yet greater detail, sometimes in many additional
subsystem levels, until the entire specification is reduced to base elements. A topdown model is often specified with the assistance of "black boxes", these make it
easier to manipulate. However, black boxes may fail to elucidate elementary
mechanisms or be detailed enough to realistically validate the model. Top down
approach starts with the big picture. It breaks down from there into smaller segments.
ADVANTAGES OF TOP DOWN APPROACH
1. Your organization realizes a focused use of resources from the individual
managed application.
2. The first implementation becomes a showcase for the identity management
solution.
3. When the phases are completed for the managed application, you have
implemented a deeper, more mature implementation of the identity
management solution.
4. Operation and maintenance resources are not initially impacted as severely
as with the bottom-up approach.

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CMOS INVERTER
The below CMOS inverter circuit is the simplest CMOS logic gate which can be used
as a light switch. If the input voltage is low (0V), then the transistor (P-type) T1
conducts (switch closed) while the transistor T2 doesnt conduct (switch open).
Hence, the output of the circuit will be equal to the supply voltage (5V).

CMOS Inverter

Similarly, if the input voltage is high (5V), then the transistor (N-type) T2 conducts
(switch close) while the transistor T1 doesnt conduct (switch open). Hence, the
output of the circuit will be low (0V).
CMOS is also sometimes referred to as complementary-symmetry metaloxide
semiconductor. The words "complementary-symmetry" refer to the fact that the
typical digital design style with CMOS uses complementary and symmetrical pairs of

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p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for
logic functions. Two important characteristics of CMOS devices are high noise
immunity and low static power consumption. Significant power is only drawn while
the transistors in the CMOS device are switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of
logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all nchannel devices without p-channel devices.

Voltage Transfer Characteristics of a CMOS inverter

The important parameters of a CMOS inverter are:
1. VOH : It is the highest Voltage that can be achieved at the output when the
input voltage is low. For a CMOS inverter VOH = VDD = the power supply.
2. VOL : It is the lowest Voltage that can be achieved at the output when the
input voltage is high. For a CMOS inverter VOL = 0.
3. VIL: It is the highest voltage for which the input would be considered as
logic low.
4. VIL: It is the lowest voltage for which the input would be considered as logic
high.

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True Single-Phase Clocked Register (TSPCR)

The True Single-Phase Clocked Register (TSPCR) proposed by Yuan and Svensson
uses a single clock (without an inverse clock). The basic TSPCR is the basic singlephase positive is shown in figure below:

TSPC positive latch

For the positive latch, when CLK is high, the latch is in the transparent mode and
corresponds to two cascaded inverters; the latch is non-inverting, and propagates the
input to the output. On the other hand, when CLK = 0, both inverters are disabled, and
the latch is in hold-mode. Only the pull-up networks are still active, while the pulldown circuits are deactivated. As a result of the dual-stage approach, no signal can
ever propagate from the input of the latch to the output in this mode. A register can be
constructed by cascading positive and negative latches.
This latch is used in the implementation of Pipelining.

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COMPARATOR

In electronics,
a comparator is
a
device
that
compares
two voltages or currents and outputs a digital signal indicating which is
larger. It has two analog input terminals V+ and V_ and one binary digital
output Vo. The output is ideally

A comparator consists of a specialized high-gain differential amplifier.

They are commonly used in devices that measure and digitize analog
signals, such as analog-to-digital converters (ADCs), as well as relaxation
oscillators.
The 2-stage comparator designed is shown in the following figure:

Comparator

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ENCODER
A Digital Encoder, more commonly called a Binary Encoder takes ALL its data
inputs one at a time and then converts them into a single encoded output. So we can
say that a binary encoder, is a multi-input combinational logic circuit that converts the
logic level 1 data at its inputs into an equivalent binary code at its output.
The Priority Encoders output corresponds to the currently active input which has the
highest priority. So when an input with a higher priority is present, all other inputs
with a lower priority will be ignored.

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Y0 = D3 + D2D1
Y1 = D3 + D2
V = D3 + D2 + D1 + D0

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ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (ADC, A/D, AD, or A-to-D) is a device that

converts a continuous physical quantity (usually voltage) to a digital number that
represents the quantity's amplitude.
The conversion involves quantization of the input, so it necessarily introduces a small
amount of error. Furthermore, instead of continuously performing the conversion, an
ADC does the conversion periodically, sampling the input. The result is a sequence of
digital values that have been converted from a continuous-time and continuousamplitude analog signal to a discrete-time and discrete-amplitude digital signal.
Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way
to convert an analog signal to a digital signal. Flash ADCs are suitable for applications
requiring very large bandwidths.Its architecture can be seen below:

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Designed Flash ADC

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DIGITAL TO ANALOG CONVERTER

In electronics, a digital-to-analog converter (DAC, D/A, DA, D2A, or D-to-A) is a
function that converts digital data (usually binary) into an analog signal (current,
voltage, or electric charge).
An R2R Ladder is a simple and inexpensive way to perform digital-to-analog
conversion, using repetitive arrangements of precise resistor networks in a ladder-like
configuration. A string resistor ladder implements the non-repetitive reference
network.

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PIPELINED ADC
The pipelined analog-to-digital converter (ADC) has become the most popular ADC
architecture for sampling rates from a few megasamples per second (Msps) up to
100Msps+. Resolutions range from eight bits at the faster sample rates up to 16 bits at
the lower rates. These resolutions and sampling rates cover a wide range of
applications, including CCD imaging, ultrasonic medical imaging, digital receivers,
base stations, digital video (for example, HDTV), xDSL, cable modems, and fast
Ethernet.

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SIMULATION RESULTS
The above circuit has been implemented on SPICE to test its functionality. We begin
by simulating the CMOS inverter and achieve the voltage transfer characteristics of
output voltage against input voltage followed by the rise and fall time for the inverter.
The rise time has been calculated as 0.426 us and fall time is 0.618 us. The threshold
voltage is 2.65V.
5.0V

2.5V

0V

0V

1.0V
V(not_1:OUT)

2.0V

3.0V

4.0V

5.0V

V_V1

5.0V

2.5V

0V
0s

V(V1:+)

10us
V(not_1:OUT)

20us

30us

Time

CMOS Inverter
Characteristic

Value

Rise Time

0.426 us

Fall Time

0.618 us

Threshold Voltage

2.65V

VIH

2.5V

VIL

2.77 V

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40us

VOH

5V

VOL

0V

NMH

2.23V

NML

2.5V

The next is the simulation for the comparator where we have the plot for the input and
output voltage achieved has been represented. One of the inputs is as shown the other
terminal of input has been fixed at a constant voltage of 2.5V.
5.0V

2.5V

0V

0V

V(V2:+)

1.0V

2.0V

3.0V

4.0V

5.0V

3.0V

4.0V

5.0V

V_V2

5.0V

2.5V

0V
0V

1.0V
V(comp_1:OUT)

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2.0V
V_V2

Comparator
The below are the simulations for the three stage pipelined ADC followed by two
tables depicting the ADC and DAC conversions.

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Voltage Level

Output

5V-3.75V

11

3.75V-2.5V

10

2.5V-1.25V

01

1.25V-0V

00
Analog to Digital Converter

Digital Input

Output

00

0V

01

1.25V

10

2.5V

11

3.75V
Analog to Digital Converter

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CONCLUSION
The above presented pipelined ADC can be extended by using pipelining to greater
number of bits without affecting the accuracy or precision as each next stage is
independent of the previous stage. Instead of using standalone Flash ADC we have
used two step converters with pipelining. Two-step converters require less silicon area,
dissipate less power, have less capacitive loading, and the voltages the comparators
need to resolve are less stringent than for flash equivalents. The throughput of twostep converters approaches that of flash converters, although they do have a larger
latency. The design is top down resulting in greater control and manageability in the
design process. We have used the TSPC latch for pipelining that allows the use of a
single phase clock as well as evaluation on both the positive as well as negative level
of the clock. The above design has been implemented and verified using spice
simulations.

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Future Work
1. The positive results has allowed us to think about a comparative analysis
with other dynamic circuits.
2. We are also in the initial stages of developing a speech signal compression
algorithm and are considering of using this implementation for the initial
anolog to digital conversion.
3. There is also an initiative towards implementing this design in combination
with a digital error correction circuit to implement greater accuracy and
precision to the design.
4. We are also working on CADENCE tools for implementing the mask layout
of the proposed circuit for which we are driven towards optimising the
internal blocks of deign with fewer number of transistors.

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References

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