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Overview
APLAC high-frequency circuit simulation technology brings the benefits of
harmonic balance (HB) analysis to the design of complex, extremely nonlinear
circuits. Finely tuned and consistently enhanced for more than 15 years, it is
no wonder APLAC technology is used extensively for IC design at Nokia and
many device manufacturers throughout the world. In fact, APLAC has aided
in the design of more than 30 percent of all mobile phone RFICs. This unique
implementation of harmonic balance and transient analysis gives you extremely
fast and exceptionally accurate results using far less computer memory than
traditional microwave harmonic balance techniques.
What is APLac?
Multi-Domain Analysis APLAC’s multi-domain analysis enables the
simulation of any RF or analog circuit with a selection of analysis
methods, including DC operation point, linear frequency-domain,
time-domain, HB, phase noise, linear/nonlinear noise, and accurate
yield predictions. Each circuit can be analyzed in multiple ways simply
by altering the analysis definitions. Optimization, tuning, and a Monte
Carlo statistical feature (for design yield) are available with every
method. Leveraging AWR’s Unified Data Model™, APLAC HB and
time-domain can be driven from the same schematic, with the same
sources and the same models.
summary
The APLAC engine delivers accurate results in less time for highly
nonlinear and large-scale designs, resulting in increased productivity
and shorter design cycles.
AWR, 1960 East Grand Avenue, Suite 430, El Segundo, CA 90245, USA
Tel: +1 (310) 726-3000 Fax: +1 (310) 726-3005 www.awrcorp.com
Copyright © 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Microwave Office, Analog
Office and APLAC are registered trademarks and Unified Data Model is trademark of AWR Corporation.
DS-AP-2010.5.7