MIXED

DESIGN

MIXDES 2010, 17th International Conference "Mixed Design of Integrated Circuits and Systems", June 24-26, 2010, Wroc
aw, Poland

A Fast Method for Transistor Circuit Voltage Range

Analysis Using Linear Programming
Sebastian Hoppner, Stephan Henker, Rene Schuffny

Achim Graupner

Technische Universitat Dresden

Dresden, Germany
Emails: {hoeppner, henker, schueffn}@iee.et.tu-dresden.de

Zentrum Mikroelektronik Dresden AG

Dresden, Germany
Email: achim.graupner@zmdi.com

AbstractThis paper presents a method for fast, automated

analysis of device constraints in analog CMOS circuits. A
linearized operating point (LOP) model is proposed which allows
device constraints like saturation conditions to be formulated
as system of linear inequalities (linear program) with circuit
node voltages as free variables. The LOP model parameters are
obtained from device lookup tables (LUTs) from a single DC
simulation. The linear program is solved to obtain valid voltage
ranges of supply, input or biasing nodes. Practical examples show
that this method provides fast analysis of device constraints with
good accuracy over a wide range of CMOS technologies without
numerous, time-consuming circuit simulations. Therefore it is
well suited for analog design automation applications.
Index TermsCMOS, analog design, constraints, voltage range
analysis, linear programming

model of the circuit, where based on linearized relations

of transistor properties, node voltages are determined and
device specic constraints (e.g. saturation) are dened. This
results in a linear system of inequalities which is solved by
means of linear programming in order to quickly determine
feasible node voltage ranges without additional simulations.
The accuracy of this method is demonstrated using two circuit
examples.
II. L INEARIZED D EVICE M ODEL
A. Linearized operating point (LOP) model
OP:

LOP: G

ID

VGS,0

I. I NTRODUCTION
Automation of analog circuit design gets more and more
important to increase design efciency and to shorten time for
migration of analog circuit blocks from one semiconductor
technology to another one. Besides the desired performance
specications, the fulllment of constraints (e.g. saturation
of transistors) is important to ensure functionality, yield and
robustness of integrated circuits [1]. Optimization based sizing
techniques have been reported, that take into account constraints of devices or device groups [2]. These methods are
based on spice-level circuit simulations or macromodels of
the circuit components [3]. Furthermore, there exist rule based
design migration strategies, which allow resizing of analog
circuits to a new technology node [4], but require additional
checking of the feasibility of a given circuit topology with
respect to reduced supply voltages, which plays an important
role in modern deep submicron CMOS technologies.
In [5] and [6] a fast evaluation method of analog circuit
feasibility (i.e. the fulllment of constraints) by means of
linear programming is presented. The constraints are linearized
around an initial operating point by calculation of constraint
sensitivities with respect to circuit parameters (e.g. device
sizes) and operating parameters (e.g. supply voltage). For
this purpose multiple circuit simulations are required, where
the number of simulations increases with the number of
parameters.
In contrast to that, this work presents a fast voltage range
analysis method which requires a single DC operating point
simulation only. It employs a linearized operating point (LOP)

G
VGS

B
S

VSB

VDS

ID

kGS VSB

B
VSB

nullator

Fig. 1. MOS transistor linearized operating point (LOP) equivalent schematic

The transistor operating point (OP) is a set of terminal

voltages that denes the behavior of the device. For the
proposed analysis method it is assumed that the drain current is
constant, which is usually the case in linear analog applications
where the device currents are dened by current sources,
which are to be in saturation. For a transistor in saturation, the
drain-gate voltage VDG has little inuence on its behavior and
is therefore neglected. This results in the linearized operating
point (LOP) model shown in Fig. 1. For a given OP, the
transistor exhibits a gate-source voltage of VG VS = VGS (ID ).
This relation denes a dependency of the node voltages VS and
VG . As an approximation, the VGS is considered to be linearly
dependent from VSB for a given ID due to the body-effect [7].
VG VS = VGS,0 (ID ) + kGS (ID ) (VS VB )

(1)

This is the fundamental node voltage dependency relation

used in this analysis. Solving for source and gate voltage
respectively results in

VG VGS,0 (ID ) + kGS (ID ) VB (if S
=B)

(2)
VS =
1 + kGS

(if S=B)
VG VGS,0
VG = VS (1 + kGS ) + VGS,0 (ID ) kGS VB

*QTv`B;?i kyRy #v .2T`iK2Mi Q7 JB+`Q2H2+i`QMB+b  *QKTmi2` a+B2M+2- h2+?MB+H lMBp2`bBiv Q7 GQ/x

(3)

j38

TABLE I
E XAMPLES OF MOS

technology

supply VDD

TRANSISTOR

LOP

MODEL ACCURACY VS .

all checks performed with: L = [Lmin , 10 Lmin ], W = 20 L, typical corner, T = 27 C

Lmin [m]
type
ID [A]
VSB [V]
VDG [V]
max. err. VGS [mV]

0.600m

5.0V

0.60

0.350m

3.3V

0.35

0.180m

1.8V

0.18

0.065m

1.0V

0.07

[1, 100]
[100, 1]
[1, 100]
[100, 1]
[1, 200]
[200, 1]
[1, 200]
[200, 1]

nmos
pmos
nmos
pmos
nmos
pmos
nmos
pmos

Generally all constraints that can be formulated as linear

inequality can be considered. This includes the sizing rules of
circuit structures like current mirrors as presented in [1]. The
saturation condition is
t (VD VS ) t Vsat

1
if nmos device
t=
1 if pmos device
Vsat = Vsat,0 + ksat (ID ) VSB

(4)
(5)
(6)

with a linear approximation of Vsat vs. VSB with slope ksat .

The variable t species the transistor type.
B. Model Fitting and Accuracy Considerations
As an example, Fig. 2 shows the dependency of VGS and
Vsat from VSB for constant ID in a 0.35m CMOS technology.
The linear approximation and the assumption that the VDG
dependency can be neglected t well.

VGS [V]

1.20
1.00
0.80

simulation
linear model

Vsat [V]

0.60
0.15
0.14

0.5

1.0

1.5
VSB [V]

2.0

2.5

3.0

Fig. 2. Linear approximation of VGS and Vsat example (0.35m CMOS,

nmos, W = 10m, ID = 50A ) for VDG = [0.2V . . . 0.5V]

The 4 LOP parameters (Vsat,0 , VGS,0 , kGS , ksat ) of a device

are extracted by linear curve tting of the VGS (VSB ) and
Vsat (VSB ) characteristics for VDG = 0V. Two tting methods
are employed:
1) Linear t including the zero t error points VGS,0 =
VGS (VSB = 0) and Vsat,0 = Vsat (VSB = 0) for devices
with physically connected source and bulk nodes where
VSB = 0 is given by the circuit topology.
2) Linear regression for minimum t error over the given
VSB range. Here it is generally VGS,0
= VGS (VSB = 0)
and Vsat,0
= Vsat (VSB = 0).

j3e

[0.0, 2.5]
[2.5, 0.0]
[0.0, 1.15]
[1.15, 0.0]
[0.0, 0.9]
[0.9, 0.0]
[0.0, 0.5]
[0.5, 0.0]

[0.5, 0.5]
[0.5, 0.5]
[0.5, 0.5]
[0.5, 0.5]
[0.3, 0.5]
[0.5, 0.3]
[0.3, 0.5]
[0.5, 0.3]

51
21
34
16
11
14
24
24

(1.0%
(0.4%
(1.0%
(0.5%
(0.6%
(0.8%
(2.4%
(2.4%

VDD )
VDD )
VDD )
VDD )
VDD )
VDD )
VDD )
VDD )

max. err. Vsat [mV]

6 (0.1% VDD )
11 (0.2% VDD )
13 (0.4% VDD )
9 (0.3% VDD )
2 (0.1% VDD )
7 (0.4% VDD )
4 (0.4% VDD )
6 (0.6% VDD )

Tab. I summarizes the accuracy of the proposed LOP

model compared to Spectre simulation results (BSIM model)
for CMOS transistors in a wide range of technology nodes
and typical sizing and bias ranges for analog circuit design
applications. The transistors are biased with the drain current
ID as shown in Fig. 3(b) and the values of VGS and Vsat
from the LOP solution are compared to the simulator solution.
The maximum absolute error in the parameter given ranges is
reported. The accuracy of the LOP model approach is suitable
for fast estimation of feasible voltage ranges with respect to
constrained operating areas.
C. Lookup Table Approach
Transistor characteristics including the LOP parameters are
stored in lookup tables (LUTs) [8] which are generated once
from simulations using a circuit simulator (e.g. Spectre) and
are available as library. Thus during circuit analysis the LUTs
do not have to be generated. The stimulating sources for LUT
generation are the base dimensions of the LUT datasets and the
operating point parameters (e.g. ID , Vsat ) are multi-dimensional
variables. Two netlists are used for LUT generation as shown
in Fig. 3. In the proposed application the voltage-driven table
(Fig. 3(a)) is used to determine ID from operating point
voltages that result from an initial DC simulation of the circuit
to be analyzed.
ID = LUT1 (VGS , VDS , VSB , W, L)

simulation
linear model

0.13
0.12
0.0

S PECTRE SIMULATION RESULTS

(7)

Using these ID values, the current-driven table (Fig. 3(b)) is

used for lookup of the LOP parameters Vsat,0 , VGS,0 , kGS and
ksat , which are dened for constant drain current ID according
to the denitions in Eq. 1.
[VGS,0 , kGS , Vsat , ksat ] = LUT2 (ID , W, L)

(8)

Note that the LOP parameters are extracted for VDG = 0.

D. Other Devices
The proposed method can easily be extended to resistors
and diodes. For constant current the resistor voltage is constant
(Vres = I R). Therefore resistors and diodes can modeled as
diode-connected transistors with VSB = 0 and VDG = 0 leading
to a constant voltage offset between their terminals. Due to
the fact that the proposed method focuses on DC properties,
capacitors are not considered.

save

ID

D
G

VGS

B
VDS

W
L S

VGS,0
kGS
Vsat,0
ksat

t VGS
Vsat

Fig. 3.

VDG

ID
D
B

G W
L
VSB

VSB

(a) voltage-driven LUT1

save

(b) current-driven LUT2

Transistor characterization netlists for LUT generation

Fig. 5 and Tab. II illustrate the proposed node classication

algorithm. First, the xed nodes are dened by propagating
the LOP relations through the circuit, starting from the predened xed nodes (e.g. ground node). Every time a new
node is xed, all attached devices are analyzed as described in
Tab. II. After all xed nodes and attached devices are evaluated
the algorithm is repeated for propagation of dependent nodes.
If gate or source node of the evaluated device do not yet
have a category, they are treated as dependent nodes for
voltage calculation. The voltage relations of dependent nodes
are stored in the form

III. C IRCUIT A NALYSIS

Fig. 4 shows the ow chart of the proposed analysis method.
The circuit schematic and the initial DC operating point are
exported from a custom design environment (e.g. Cadence
DF2). The LOP is determined by table lookup.
custom design environment
Schematic

DCOP simulation

XML

XML

Read OP, lookup LOP parameters

LUT data

Classify nodes

Net dependencies
1

Optimization goal
Solve LP

Fig. 4.

where M
A , M
B and M
D are n n matrices that include the
dependency coefcients from Eq. 2 and Eq. 3 respectively and
v
= [v1 , . . . , vn ]T are (n1) node voltage vectors. Dependent
nodes depend on other dependent nodes if M
D
= 0. If all
dependencies are evaluated, i.e. there are no more unevaluated
devices, but there are uncategorized nodes remaining, one of
them is dened as free node. The according entries in matrix
M
D are moved to M
B . Then the node propagation algorithm
is started again.

Constraints

Setup LP

Results

v
dep = M
A v
xed + M
B v
free + M
D v
dep + v0
(10)

conguration

Iteration loop

4
5
6

Analysis ow chart

7
8
9

A. Node classication and linear dependency setup

A circuit contains a set of n nodes N and a set of d devices
D. Each device has an LOP which relates its terminal node
voltages by the relation Eq. 1. Based on these preconditions
the nodes are classied into three categories:
Fixed nodes Nxed N have voltages that are dened
by the LOP with respect to other xed nodes.
Free nodes Nfree N have voltages that are not dened
by the LOP (e.g. drain or bulk node in Fig. 1).
Dependent nodes Ndep N have voltages that depend
on other node voltages. Dependencies are dened by the
LOP relations according to Eq. 1.
Each is assigned to exactly one category. Each circuit contains
at least one xed node (e.g. ground node Vgnd = 0V).
nxed 1

(9)

As example, if the source and bulk nodes of an nmos

transistor are xed nodes (e.g. by ground connection) the
simulated DC OP denes a value of VGS . Therefore the gate
node of this device is a xed node as well (VG =VS +VGS ). The
drain node is not xed by this relation.

10
11
12
13
14
15

Data: netlist, list of pre-dened free or xed nodes

Result: node dependency equations
push all pre dened nodes on nodestack;
while nodestack not empty do
pop node from nodestack;
push all to node attached devices on devicestack;
while devicestack not empty do
pop device from devicestack;
if device not done then
setup node dependencies (see Tab. II);
mark device as done;
end
end
if nodestack empty then
push next uncategorized node on nodestack;
end
end
Fig. 5.

Node classication algorithm for xed and dependent nodes

When the numbers of xed (nxed ), free (nfree ) and dependent (ndep ) nodes have been determined the matrix dimensions
can be reduced. We introduce the matrices MA (ndep nxed ),
MB (ndep nfree ), MD (ndep ndep ) and the vector v0 (ndep 1)
and calculate their values by removing those entries from the
original matrices M
A to M
D respectively, which correspond
to nodes that are not of the according category. The next step
is to resolve the dependencies between dependent nodes by
solving Eq. 10 with the new matrix denitions for vdep .
vdep = (MD E)1 (MA vxed
MB vfree v0 )

(11)

j3d

TABLE II
N ODE PROPAGATION DECISION TABLE ( F : NODE FIXED , NF : NODE NOT
FIXED , C : NODE CATEGORY KNOWN , NC : NODE CATEGORY NOT KNOWN )
G

f
f
f
f
nf
nf

xed node propagation

f
already done
nf
f
x source (Eq. 2)
nf
nf (B=S)
x source and bulk (Eq. 2)
nf
nf (B
=S)
nothing done
f
f
x gate (Eq. 3)
f
nf
nothing done

action performed

c
nc
c
nc

dependent node propagation

c
already done
c
c
setup gate equation
nc
c
setup source equation
nc
nc
nothing done

with the identity matrix E. Introducing

P
= (MD E)1 MA

(12)

Q
= (MD E)1 MB

(13)

r = (MD E)

v0

(14)

leads to the linear node voltage dependency equation for all

nodes of the circuit

Q
r
vdep
P
vfree = 0 vxed + E vfree + 0
(15)
E
0
0
vxed

 
 

 

 
v
r
P
Q
Each node voltage is a linear combination of free and xed
node voltages.

where RD (. . . ), RS (. . . ) and RB (. . . ) are the matrix/vector

rows for the drain, source and bulk node of device i respectively. The variable t species the transistor type (nmos: t = 1,
pmos: t = 1).
An optimization goal is dened by the cost function vector
f = [f1 , . . . , fnfree ]T . We set fi = 1 for minimization and
fi = 1 for maximization of the voltage of free node i
respectively. Using the additional equality constraints Eq. 18,
linear relations between the free nodes can be dened. This is
useful when free nodes are connected outside the circuit (e.g.
feedback from amplier output to input) or if the degrees of
freedom for the analysis are to be limited (e.g. maximize a
free node voltage for a xed value of another free node).
This analysis method has been implemented using Matlab.
The nodes are classied and the LP is constructed as described
by Eq. 10 to Eq. 20. The settings of the cost function vector
f as well as additional equality constraints Aeq and beq are
dened by the user and the LP is solved using a linear
optimization tool. The result is a set of free node voltages
corresponding to the chosen settings. Based on these results
the optimization settings can be redened and the LP can be
solved again as shown in Fig. 4. Thus the voltages ranges can
be analyzed a without re-simulating the design. For each LP
solution the constraints and the voltage range limiting devices
are reported, which allows to identify critical circuit parts.
IV. A PPLICATION E XAMPLES
A. Simple OTA Voltage Range Analysis
1

4
1 (VDD )
0 (Vgnd )

M1

M0
5 (Vout )

B. Linear Program Setup

We dene a linear program (LP) [9] with the free node
voltages as variables in order to allow analysis of their valid
voltage ranges.
f T vfree min
A vfree b
Aeq vfree = beq

(17)
(18)

M2

(19)

bi = t [(RD (P) + (1 + ksat ) RS (P)

ksat RB (P)) vxed RD (r) + (1 + ksat ) RS (r)
ksat RB (r) + Vsat,0,i ] (20)

0
0

M5
Fig. 6.

3 (Vin )

0
M3

xed node
dependent node

and the i-th element of b reads

j33

(16)

We construct a matrix A (d nfree ) and a vector b =

[b1 , . . . , bd ]T from the constraints (Eq. 4, Eq. 6) for all d
devices. The drain and source voltages are dened by Eq. 15.
For device i the i-th row of A is
Ri (A) = t [RD (Q) (1 + ksat ) RS (Q)
+ ksat RB (Q)]

2 (Vin )

M4

free node

Simple OTA schematic

A rst example considers an OTA as shown in Fig. 6

in 0.35m CMOS technology. The initial operating point
is simulated at VDD = 3.6V and Vin = Vout = 1.8V.
The according LOP parameters are shown in Tab. IV. The
circuit contains 2 xed nodes (0, 7), 3 free nodes (1, 2, 5)
and 3 dependent nodes (3, 4, 6). Tab. III summarizes the
analysis results using the LOP method compared to Spectre
simulations.
In case 1 VDD is minimized with additional constraints on
Vin and Vout , leading to a single free dimension. Therefore
the corresponding Spectre simulation performs a single DC
sweep. The current of M4 drops at 1.7V when it enters
linear region as shown in Fig. 7. Case 2 minimizes Vin without

TABLE III
S IMPLE OTA

1
2
3
4

LOP

VS .

S PECTRE SIMULATION

Conditions

Objective

LOP model

Spectre

Error

Vin = Vout = VDD /2

Vin = Vout
VDD = 2.5V

VDD,min
Vin,min
VDD,min
Vin,max

1.73V
0.86V
1.28V
2.32V

1.69V
0.84V
1.24V
2.33V

40mV
20mV
40mV
10mV

No. of Simulations

300
300 300 300
300 300
300 300

(2.3%)
(2.4%)
(3.2%)
(0.4%)

case numbers for an accuracy of 10mV in a range from 0V to 3V for linear search of all free dimensions

additional constraints. In case 3 Vin is connected to Vout but

not related to VDD leading to two free dimensions. VDD is to be
minimized. Here a two-dimensional DC sweep is required for
the comparing Spectre simulation. In case 4 Vin is maximized
for a xed VDD = 2.5V. Fig. 8 shows plots of the circuit
constraints for two free node dimensions respectively (cases 3
and 4), comparing the Spectre simulation results (gray elds)
to the LP constraints (lines). The results are in good agreement,
but the proposed method requires only a single DC operating
point simulation and therefore is signicantly faster.

4.0
3.5
M0

3.0
Vin [V]

a Worst

VOLTAGE RANGES COMPARISION :

2.5
DCOP

2.0
1.5
M2

1.0

M4

0.5
0.0
1.0

1.5

2.0

2.5
VDD [V]

3.0

3.5

4.0

(a) additional constraint Vin = Vout , case 3

TABLE IV

3.5

L INEARIZED OPERATING POINT PARAMETER OF SIMPLE OTA

3.0

type

VGS,0 [V]

kGS

Vsat,0 [V]

ksat

M0
M1
M2
M3
M4
M5

pmos
pmos
nmos
nmos
nmos
nmos

-1.04
-1.04
0.69
0.69
0.76
0.76

-0.10
-0.10
0.22
0.22
0.22
0.22

-0.18
-0.18
0.10
0.10
0.14
0.14

0.005
0.005
0.003
0.003
0.004
0.004

2.5
Vin [V]

device

M2

2.0
1.5

M3

1.0

M4

M0

0.5
0.0
0.0

0.5

1.0

1.5

2.0

2.5

ID [uA]

Vout [V]
25.0
20.0
15.0
10.0
5.0
0.0
1.0

Fig. 7.

LIN

Spectre region change

LOP model constraint
1.5

(b) additional constraint VDD = 2.5V, case 4

ID(M4)

SAT

2.0

2.5
VDD [V]

3.0

DCOP simulation
3.5

Fig. 8. Spectre simulation results of simple OTA with DC sweep steps

of 50mV (gray elds: at least one device of the circuit is not in saturation)
compared to LOP constraints from a single DC OP simulation (lines)

4.0

OTA simulation result, ID and region of M4, case 1

B. Voltage Range Analysis for Op-amp Technology Migration

The proposed method can be used effectively for analysis
of portability of analog circuits to a new semiconductor
technology with reduced supply voltages. As an example an
op-amp shown in Fig. 9 is considered, that is migrated from
0.6m CMOS with nominal VDD = 5V to 0.18m CMOS
with 1.8V < VDD < 3.6V. First, a linear shrink of the device
geometries has been performed with a scaling factor of 0.2.
In the target technology the DC OP is simulated at VDD = 3V
from which the LOP is constructed. The circuit contains 38
devices, 3 free nodes (VDD, IP, OUT), 13 xed nodes and 14
dependent nodes. The accuracy of the LOP is determined by
calculating the maximum voltage deviation of the LOP from
the OP. It is max |VLOP,i VOP,i |nodes < 22mV. This LOP is
used for the analyses without re-simulating the design.

1) Analysis without topology variation: The LOP analysis

results are summarized in Tab. V. First, the minimum supply
voltage is determined and the limiting devices are reported.
It is VDD,min = 2.58V. Then the input and output voltage
ranges are determined for VDD = VDD,min . The maximum input
voltage is limited by device Mt and its gate voltage BIAS2.
By re-denition of BIAS2 as free node, disabling of the diode
connected bias device Md and solving the LP again, the input
voltage range is extended by 0.23V with VBIAS2 = 1.41V.
Finally, increasing of VBIAS2 is achieved by resizing Md.
As result, the given topology is not suitable for supply voltages signicantly lower than 2.5V. Automatic sizing of this
topology using the tool WiCkeD with hundreds of simulation
runs did not lead to feasible results for VDD < 2.2V. These
analysis results, as well as the bias adaption for increased input
range could be obtained from a single DC simulation only.
2) Topology changes indicated by LOP analysis: The minimum supply voltage is limited by the cascode current source
device Mc1. The proposed analysis method allows to disable

j3N

TABLE V
O P - AMP LOP ANALYSIS RESULTS

1
2
3
4
5
6
7

VDD

Conditions

Objective

Result

VDD
VDD
VDD
VDD
VDD
VDD

VDD,min
VOUT,min
VOUT,max
VIP,min
VIP,max
VIP,max
VBIAS2,max

2.58V
0.13V
2.40V
0V (GND)
0.93V
1.16V
1.41V

= 2.58V
= 2.58V
= 2.58V
= 2.58V
= 2.58V , BIAS2 free, no Md
= 2.58V , BIAS2 free, no Md

TABLE VI

1
2
3
4

Md

VDD

IP

VDD

VDD VDD

IN

OUT
IREF

all bulk pmos VDD

all bulk nmos GND

constraints for a device that limits a particular voltage range.

Re-running the analysis gives the second limiting device in
the circuit. Thus a ranking of limiting devices can be obtained
as shown in Tab. VI. Note that disabling constraints does not
lead to the exact voltage range limit when removing the device
physically from the circuit because the DC OP changes which
requires a new DC simulation for a more accurate solution.
Anyway, the ranking of the limiting devices gives useful hints
for topology modications leading to improved voltage ranges.
The Op-amp circuit topology is modied based on the results
of the LOP analysis. Modications include the removal of the
cascode devices Mt, Mc1 and Mc2 as shown in Fig. 10. The
modied circuit could be sized successfully for VDD > 1.8V.
O P - AMP LOP

VDD VDD VDD VDD

Fig. 10. Op-amp schematic with modied topology for low voltage operation

with linear programming has been presented. The feasible

voltage ranges of all circuit nodes can be checked from a
single DC operating point simulation, providing fast information about the feasibility of a sized circuit for specied
voltage ranges. The results have been compared to spice-level
simulations and show good accuracy. This method is well
suited for analog design automation where voltage ranges can
be estimated quickly like performance measures during circuit
optimization. Furthermore a large number of circuit topologies
with different parameter sets can be evaluated for voltage range
feasibility in a short period of time.
ACKNOWLEDGMENT

LIMITING DEVICES RANKING

VDD,min

limiting device

disabled devices

2.58V
2.58V
2.07V
2.06V

Mc1
Mc2
Ms1
Ms2

Mc1
Mc1, Mc2
Mc1, Mc2, Ms1

The authors thank Volker Boos from IMMS gGmbH Erfurt

Germany for support with software interfaces. This work is
supported by the German Ministry of Education and Research
BMBF under grant number 01M3086F. The authors are responsible for the content of this publication.
R EFERENCES

VDD

VDD VDD VDD VDD

VDD
Mc1

VDD

VDD VDD

Mt
BIAS2

IP

Md

IN

Ms1

Ms2

OUT

IREF
Mc2

all bulk pmos VDD

all bulk nmos GND

Fig. 9.

Op-amp schematic

The proposed analysis method provides a fast numerical

prediction of the feasibility of the given circuit topology with
respect to the supply voltage range in the target technology and
gives suggestions for topology modications without extensive
spice-level simulations.
V. C ONCLUSION
A method for voltage range analysis of transistor circuits
based on a linearized operating point (LOP) in conjunction

jNy

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