HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanChainOperationforStuckatTest

CombinationalLogic

CombinationalLogic

CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

PrimaryOutputs(PO)

ScanOut

DesignUnderTest(DUT)

ScanEnable
ScanIn

Hereisanexampledesignundertest(DUT).Ihaveshownasinglescanchain(inredcolor)inthecircuit,withScanInandScanOutports.
AssumethatallscanflipflopsarecontrolledbytheScanEnablesignal.

HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanOut

DesignUnderTest(DUT)

PrimaryOutputs(PO)

CombinationalLogic

X
CombinationalLogic

X
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

ScanEnable=1
ScanIn
100101011

Thefirstthingweshoulddoistoputthescanflipflopsintoscanmode.WedothisbyusingtheScanEnablesignal.Inthiscase,forcingScan
Enableto1enablesthescanmode.
Notethatinitiallyallthescanflopsatunknownstate(X).Forindustrialcircuits,therearearchitecturalwaystoinitializeallflipflopstoknown
statesifneeded.However,forthisparticularcase,assumethatallscanflopswereinitiallyatunknownstateX.
Wewanttoscaninthefollowingvector:100101011

HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanOut

DesignUnderTest(DUT)

PrimaryOutputs(PO)

CombinationalLogic

X
CombinationalLogic

X
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

ScanEnable=1
ScanIn
100101

Andwestartscanninginthetestvectorwewanttoapply.Inthefigureabove,youseethatthefirst3bitsarescannedin.Weshiftinasinglebit
ateachclockcycle.Usually,thescanshiftfrequencyisveryslow,muchlowerthanthefunctionalfrequencyofthecircuit.Thisfrequencyis
currentlyabout100MHzformostASICcircuits.AMDuses400MHzshiftfrequency,whichisaprettyhighvalueforthatpurpose.Ofcourse,the
higherthetestfrequency,theshorterthetesttime.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

PrimaryOutputs(PO)

CombinationalLogic

1
CombinationalLogic

1
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

ScanEnable=0
ScanIn

Atthispoint,wehaveshiftedinthecompletetestvector'100101011'.Wearedonewithshiftingin.WewilldisablescanmodebyforcingScan
Enableto0.
Notethattheshiftedintestvectoriscurrentlyappliedtothecombinationallogicpiecesthataredrivenbyscanflipflops.Itmeansthat2nd,
3rd,and4thcombinationallogicblocksarealreadyforcedtestinputs.

HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanOut

DesignUnderTest(DUT)
0

1
1
0
1
1

PrimaryOutputs(PO)

1
CombinationalLogic

1
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

0
CombinationalLogic

0
ScanEnable=0
ScanIn

Thenextstepistoforceprimaryinput(PI)valuesandmeasuretheprimaryoutput(PO)values:force_PIandmeasure_PO.
Notethatfromthepreviousstep,theshiftedintestvectorwasalreadyappliedtothecombinationallogicpiecesthataredrivenbyscanflip
flops.Itmeansthat2nd,3rd,and4thcombinationallogicblockswerealreadyforcedtestinputs.Now,thesecombinationallogicblockshave
generatedtheiroutputs.
SinceweforcedvaluestoPI,the1stcombinationalblockalsohasitsoutputsready.Furthermore,theoutputsofthe4thcombinationalblockcan
nowbeobservedfromPOs.Wewillgettheoutputvaluesofcombinationalblock4bymeasuringPOs.
Fortherestofthecombinationalblocks(1,2,and3),weneedtopushtheoutputvaluesintoscanflipflopsandthenshiftthesevaluesout.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

1
1
0
1
1

PrimaryOutputs(PO)

1
CombinationalLogic

0
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

0
CombinationalLogic

0
ScanEnable=0
ScanIn

Inordertopushtheoutputvaluesofcombinationalblocks1,2,and3intoscanflipflops,wehavetotogglethesystemclock.Oncewetogglethe
systemclock,allDflipflops(scanflipflops)willcapturethevaluesattheirDinput.
Inthefigureabove,thecaptureeventisshown.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

PrimaryOutputs(PO)

CombinationalLogic

1
CombinationalLogic

CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

ScanEnable=1
ScanIn
111100111

Now,wearereadytoshiftoutthecapturedcombinationallogicresponses.However,whiledoingthat,wewillalsoshiftinthenexttestvector.
Thenexttestvectoris'111100111'.
NotethatwehavesetScanEnablesignalbackto1toenableshifting.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut
0111

PrimaryOutputs(PO)

CombinationalLogic

1
CombinationalLogic

1
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

ScanEnable=1
ScanIn
11110

Hereisasnapshotoftheshiftoperation.Asyoucansee,wehaveshiftedout4bitsoftheprevioustestresponse,andatthesametimeshifted
in4bitsofthenewtestvectorinput.Thenewtestvectorbitsareshowninboldredinthefigureabove.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut
011000111

PrimaryOutputs(PO)

CombinationalLogic

1
CombinationalLogic

1
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

ScanEnable=1
ScanIn

Atthispoint,wehavecompletelyscannedout(shiftedout)thetestresponsefortheprevioustestvector,andalsoscannedin(shiftedin)the
newtestvectorinput.
Theprocesscontinuesinthiswayuntilallthetestvectorsareapplied.
Note:Onpage5,Imentionedforce_PIandmeasure_PO.Actually,forindustrialcircuits,force_PIandmeasure_POisnotdone.Thisisbecause
primaryinputsandoutputsareconnectedtoveryslowpads,andthesepadsarenottestedbystructuraltest.Youmayrealizethatinthiscase
the1stand4thcombinationalblockscannotbetested:1stblockcannotbetestedbecausewecannotapplyinputstoit(force_PI).4thblock
cannot be tested because we cannot check its output (measure_PO). This is usually not a problem because the circuits are surrounded by
wrapperscanflipflops.Thismeansthatthereisactuallynologicbeforethefirstlevelofscanflipflopsorafterthelastlevelofscanflipflops.
So,thecompleteDUTiscoveredbyscanflipflops.

HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanChainOperationforDelayTest
Scanoperationfordelaytestisverysimilartostuckattest.Themaindifferenceisthatdelaytestneedstwoinputsinsteadofone.Thefirstinput
isalwaysthescannedinvector.Thesecondinputcanbegeneratedintwodifferentways.Eachwayhasitsownname:(1)LaunchonCapture
(LOC)orbroadsidedelaytest,(2)Launchonshift(LOS)orskewedloaddelaytest.NowIwillshowhoweachofthesemethodsworks...

(1)LaunchonCapture(Broadside)
ScanOut

DesignUnderTest(DUT)
0

PrimaryOutputs(PO)

1
CombinationalLogic

1
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

0
CombinationalLogic

0
ScanEnable=0
ScanIn

Thisisthesamefigurethatisshownonpage5.Assumethatalltheprocessuntilthispointisthesameasstuckattest.Youscannedinthetest
vector, forced the PIs, and they created some output responses for combinational blocks. This is step 1. You have already applied your first
vectorforthedelaytest.Guesswhatisthesecondvector?Thesecondvectorwilltheoutputresponsesofthecombinationalblocks.Eachblock
willgeneratethe2ndtestvectorforthenextstage.Sincethereisnostagebeforethe1stone,youneedapplyforce_PIonemoretime.

10

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

1 0

0 0

1
1
0
1
1

PrimaryOutputs(PO)

1 1

1
CombinationalLogic

1 0

1
CombinationalLogic

0 0

CombinationalLogic

PrimaryInputs(PI)

1 0

0
CombinationalLogic

1 1

1 0
ScanEnable=0
ScanIn

Ofcourse,inordertopushtheoutputresponsesofcombinationalblocksintoscanflipflops,weneedtotogglesystemclock.Oncewetoggle
thesystemclock(andapplythesecondPIforce),wewillgeneratethesecondtestvectorforthedelaytest,andeachcombinationalcircuitinput
will see an input state transition. The transition on scan flipflop outputs (which are inputs to the next stage combinational block) will be as
follows(startingfromtheclosesttoscaninflop):100101110>010010111
Thesecondinputvectorwillgenerateoutputresponsesjustlikethefirstone.And,youneedtocapturetheseresponsesjustlikewedidbefore,
by toggling the system clock. However, now there is a difference: You have to toggle the system clock at the real operating frequency: This
meansthattheperiodbetweenthefirstclocktoggleandsecondclocktoggleshouldbeequaltofunctionalclockperiod.Inthisway,youwill
capturethedelaytestresponsesatthefunctionalfrequency.

11

HowdoesScanWork?

PreparedbyMahmutYilmaz

HereisatimingdiagramoftheLOCprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):

Asyoucanseeabove,weshiftthetestvectorusingaslowclockfrequency.Then,wesetscanenableto0anddisablescanmode.Inthenext
step, we toggle the clock first time to launch a transition in combinational blocks. After that, we toggle the clock again (at the functional
frequency)tocapturethefinalresponsesofthecombinationalblocks.Thelaunch&captureeventshappenatfunctionalfrequency.Finally,we
shiftedoutthecapturedresponsesusingtheslowclockfrequency.

12

HowdoesScanWork?

PreparedbyMahmutYilmaz

(2)LaunchonShift(SkewedLoad)
ScanOut

DesignUnderTest(DUT)
0

PrimaryOutputs(PO)

1
CombinationalLogic

1
CombinationalLogic

CombinationalLogic

PrimaryInputs(PI)

0
CombinationalLogic

0
ScanEnable=1
ScanIn

Thisisthesamefigurethatisshownonpage5and10.So,westartasusual:Assumethatalltheprocessuntilthispointisthesameasstuckat
test.Youscannedinthetestvector,forcedthePIs,andtheycreatedsomeoutputresponsesforcombinationalblocks.ForLOS,wedon'tcare
abouttheseinitialoutputresponses.Thisisstep1.Youhavealreadyappliedyourfirstvectorforthedelaytest.Sincethereisnostagebefore
the1stone,youneedapplyforce_PIonemoretime.NotethatScanEnablesignalisstillatactivevalue1.Thisisbecausewehavenotyetdone
withshifting.Weneedtoshiftonemoretimetocreatethesecondtestvectorforthedelaytest.

13

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

1 0

0 0

PrimaryOutputs(PO)

1 1

1
CombinationalLogic

1 0

1
CombinationalLogic

0 0

CombinationalLogic

PrimaryInputs(PI)

1 0

0
CombinationalLogic

1 1

1 0
ScanEnable=1
ScanIn 0

Notethatasmentionedinthepreviouspage,thefirstvectorofthedelaytestis(startingfromtheclosesttoscaninflop):100101110
Thesecondtestvectorisgeneratedbyshiftingonemoretime,andinsertingonemorebitfromScanIn,2ndvectoris:010010101
Justafteryoushiftthelastbit(andlaunchedatransitionbyapplyingthesecondvector),youhavetoforceScanEnableto0,andalsotogglethe
systemclockatthefunctionalfrequency.Thelasttoggleofthesystemclockwillcapturethedelaytestresponses.Finally,youwillscanoutthe
responsesasusual.

14

HowdoesScanWork?

PreparedbyMahmutYilmaz

HereisatimingdiagramoftheLOSprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):

Asyoucanseeabove,weshiftthetestvectorusingaslowclockfrequencyuntilthelastbit.ThelastshiftedbitcreatestheLaunchevent.Then,
before we toggle the system clock to capture responses, we set scan enable to 0 and disable scan mode. This has to happen very fast since
Launch & Capture event happen at high frequency. In the next step, we toggle the clock again to capture the final responses of the
combinationalblocks.Finally,weshiftedoutthecapturedresponsesusingtheslowclockfrequency.
YoucanseethatweneedtohaveaveryfastScanEnablesignalinordertouseLOS.ScanEnableshouldbeabletoswitchfrom1to0withina
veryshorttime.ThisisusuallyadifficultprocessbecauseScanEnableisnotdesignedtooperateathighfrequencies.Duetothisreason,many
industrialdesignsuseLOCinsteadofLOS.(TherearesomedesignsthatuseLOS.ThereareworkaroundstofastScanEnablesignalrequirement,
butIwillnotgointodetailsfornow.)

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