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Ahmed Hemani

Sources:
Synopsys Documentation

Logic Synthesis 5
FSM and Retiming

Multi Cycle Paths


Timing path that is not expected to propagate a signal in one cycle
FF2

FF1

FF3

Input
Logic

Q
FF

Logic

Logic

FF

Q
FF

Logic
g

Clk
Two Clock Periods

This input
changes
once every
2nd cycle

FF4
D

FF5
Q

Large Logic

FF

Q
FF

Multi-Cycle Path

set_multicycle_path 2 -from FF4 -to FF5

To undo a set_multicycle_path command


use reset_path or reset_design.

False Paths
You can exclude false paths from an Static Timing Analysis run.
False paths are considered unconstrained.
Top
A

U3
Alpha

U1
Beta
U5
Gamma

False Path
Reset

U4
Alpha

U2
Delta

Clk

set_false_path -reset_path -from { "Reset" }

Pipelining a fully manual approach


Increases the throughput of designs to meet high timing constraints.
REG

REG

Original design
Op1

Too low throughput

Op2

Op3

30 ns
Go get better performance
- symbolical!

REG

REG

Op1

HDL Add some registers

Op2

REG

REG

Op3

30 ns
REG

Distribute the registers evenly


over the operators

Note:

REG

R EG

REG

Op1

Op2

Op3

10 ns

10 ns

10 ns

This approach will create an overall larger latency due to the extra
registers, but the through-put will increase!

Re-timing a semi-automatic approach


Increases the throughput of designs to meet high timing constraints.
REG

REG

Original design
Op1 - e.g. multiplier

Too bad through-put


Go get better performance

30 ns
REG

HDL:
Add some registers

REG

REG

REG

Op1 - e.g. multiplier


In Synopsys:
Set your timing constraints
Compile your design
dc> balance
balance_registers
registers

30 ns
REG

The balance_registers will try


to distribute the registers
evenly over the operators

Note:

REG

R EG

REG

Op1.1

Op1.2

Op1.3

10 ns

10 ns

10 ns

This approach will create an overall larger delay due to the extra registers
but the through-put will increase!

Re-timing - Limitations
Only works on mapped/compiled designs
No Set or Reset on the registers allowed
1

If Re-time was possible

Reset

Reset

Loop-backs not possible to Re-time


y(n)
R EG

x(n+1)

REG

Op1

Not possible to move


inside loop

Re-timing registered outputs


How to get the output registers right?
Original

Desire - We want to keep the output registers


Three possibilities:

R EG4

O 1
Op1

1. Group the extra together in the HDL


- Separate Component
or Separate Process + group -hdl in DC
2. Group the combinatorial logic and the
extra registers manually in synopsys
dc> group {REG2 REG3 Op1} \
-design_name Op1_ret
dc> current_design Op1_ret
Set the timing constraints
dc> balance_registers
3. Put a dont_touch attribute on the last register
in Design Compiler after the timing
constraints are set and the design is compiled
dc> set_dont_touch {REG4}
dc> balance_registers

Registers Added

REG2

REG3

REG4

Op1

Registers Added

REG2

Op1.1

REG3

Op1.2

R EG 4

Op1.3

Finite State Machines


Standard Mealy Machine:
ENTITY FSM IS
PORT( Clk
Toggle
Op
END FSM;

: IN BIT;
: IN BIT;
: OUT BIT);

ARCHITECTURE FSM_behave OF FSM IS

Output
Mealy Machine

Output
p
Register

TYPE STATE_TYPE IS (ZERO, ONE);


SIGNAL current_state : STATE_TYPE;
SIGNAL next_state
: STATE_TYPE;

Input
BEGIN

next_state

logic
seq_logic : PROCESS(Clk)
BEGIN
IF (ClkEVENT and Clk = 1) then
current_state <= next_state;
END IF;
END PROCESS;

State
Register

state

comb_logic : PROCESS (current_state, Toggle)


BEGIN
Op1 <= 0;
next_state <= ONE;
CASE current_state IS
WHEN ONE =>
IF (Toggle = 0) THEN
...

Combinatorial logic

Sequential logic

Synthesis of Finite State Machines


Idea - Make Synopsys aware of that the logic represents an FSM
Output
Standard Mealy Machine:
ENTITY FSM IS
PORT( Clk
Toggle
Op
END FSM;

y Machine
Mealy

: IN BIT;
: IN BIT;
: OUT BIT);

Input

next_state

logic

Output
Register

State
Register

ARCHITECTURE FSM_behave OF FSM IS


TYPE STATE_TYPE IS (ZERO, ONE);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state
: STATE_TYPE;

state
Order is important!

ATTRIBUTE STATE_VECTOR : STRING;


ATTRIBUTE STATE_VECTOR OF FSM_behave: ARCHITECTURE IS "current_state";

Dedicated Synopsys Attributes


Used to identify state-related
logic during state encoding
extraction

BEGIN
seq_logic : PROCESS(Clk)
BEGIN

Synthesis flow of FSMs in Synopsys


Extract

VHDL

Compile

State
T bl
Tables

Gates

Change
StateState
Encodings

FSM compile

Extraction of the state-vector in a design where the


state-vector is the only sequential elements
dc>
dc>
dc>
dc>
dc>

analyze -f vhdl fsm.vhdl


elaborate fsm
replace_synthetic \* Lighter version of compile *\
extract
report -fsm

Synthesis Flow of FSMs in Synopsys

Extraction of the state-vector in a design where the state-vector is not the only
sequential elements
dc>
dc>
d
dc>
dc>
dc>
dc>
dc>

analyze -f vhdl state_vector.vhdl


elaborate fsm -arch fsm_behave
group -fsm
f
-design_name
d i
extracted_fsm
t
t d f
current_design = extracted_fsm
replace_synthetic
extract
report -fsm

Extraction of the state-vector in a design where the state-vector attribute is not set
in the HDL
Existing Registers
U1:FLIP_FLOP p
port map
p (NEXT_STATE[0], CLK, STATE[0]);
U2:FLIP_FLOP port map (NEXT_STATE[1], CLK, STATE[1]);

How to give the register the state attributes


set_fsm_state_vector { U1, U2 }
set_fsm_encoding {"S0=2#00", "S1=2#01", "S2=2#10", "S3=2#11" }

Use the script above for the rest

Synthesis flow of FSMs in Synopsys


Extract

VHDL

Compile

State
Tables

Gates

Change
StateEncodings

FSM compile

How to set the encoding of the fsm to one-hot and perform an FSM compile
The script was extracted from command-window after graphical interface manipulations :(
dc>
dc>
dc>
dc>
dc>
dc>
dc>

set_fsm_order { S0 S1 S2 S3 }
set_fsm_encoding { }
set_fsm_encoding_style one_hot
set_fsm_order { S0 S1 S2 S3 }
set_fsm_encoding { "S0=2#1000"
"S0=2#1000"S2=2#0100
"S0=2#1000"
"S0=2#1000"}
S0=2#0001 S1=2#0010
S3=2#1000

set_fsm_minimize true
compile -map_effort medium

For more info : Design Compiler Reference Manual:


Optimization and Timing Analysis, Chapter 4