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Authors:
Vijay Chobisa
Product Marketing Manager, Mentor Graphics Corporation
vijay_chobisa@mentor.com
Mentor Graphics Corporation
Charley Selvidge
R&D Director, Mentor Graphics Corporation
charley_selvidge@mentor.com
Mentor Graphics Corporation
www.mentor.com
INTRODUCTION
Emulation vendors are facing challenges of delivering
faster runtime performance, addressing capacity needs,
supporting different stimulus sources/methodologies,
and offering simulation like ease-of-use and debug.
It is possible to have test stimulus come from in-circuit
target systems (hardware testbenches) or alternatively,
from abstract software-based testbenches using C/C++
/SystemC/SystemVerilog. Providing flexibility where
users can use multiple stimulus methodologies in the
same project or on the same model using single
emulator platform is a real differentiator. As verification
moves to a higher level of abstraction, hardwareassisted verification tools are required to handle
verification environments designed using these
advanced methodologies.
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Veloce SoC is designed to accept multiple asynchronous clocks to support environments that have
interfaces using asynchronous clocks. If the user wants
to have an independent evaluation capability for distinct
clock domains, then its required to give each clock
domain its own communication resources, which are
synchronized to that clock domain. The communication
network inside the Veloce SoC is extremely flexible
and can be programmed to a fine level of granularity
in order to move signals in and out from the chip for a
distinct clock domain. The flexible communication
network enables Veloce to accurately model asynchronous
environments and behaviors.
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FASTER COMPILES
Its useful to understand that designers do not compile
the design many times a day. They compile the design,
run various tests, report bugs to the RTL designer, and
then recompile the design when new RTL is ready.
Generally, designers spend more time running and
debugging designs than actually compiling the design.
A typical scenario would be the verification team finds
a bug, reports the bug to the designer(s) for the RTL
fix, and then runs the compile once the RTL is fixed.
Usually the time needed to fix the RTL is longer than
the compile, run, and debug. It is not uncommon for
new RTL to be released to the verification team once
every week or two. This highlights that compiling is
infrequent, and having very fast compiles does not
necessarily influence productivity to the level that it
gets advertised.
PREDICTABLE COMPILES
Compile predictability means multiple compiles on
the same database delivers the exact same results and
behavior; compile speed and predictability are equally
important. One attribute of compile predictability is
setup and hold issues. Any emulator, whether its
FPGA-based or processor-based, must contain compute
elements that perform logic functions and storage
elements, which store state data. Setup and hold issues
are not functions of whether its a FPGA-based solution
or processor-based solution. Its a function of how the
user chooses to use compute and storage resources in
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Veloce has both hard virtual wires and soft virtual wires
for network connectivity. Hard virtual wires are the
fixed baseline interconnect network designed directly
in the silicon. The soft virtual wire technique is an ability
to flexibly extend the network in order to optimize
overall capacity of the chips by using some of the
compute resources. For interconnect dominant designs,
hard virtual wire interconnect resources are not sufficient;
therefore, Veloce uses soft virtual wires to augment
connectivity. This doubles the interconnect network and
delivers improvements in overall capacity utilization.
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Users need hardware flexible enough to initiate computations based on various edges, and software sophisticated
enough to recognize what actions are associated with
DEBUG
One aspect of debug productivity is how easily a user
can use the debugging infrastructure provided. Another
aspect is how long it takes to get the data to start the
debug. In applications where users can control the
clocks, the Veloce standard visibility model gives full
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VISIBILITY
Time to visibility is another aspect of debug productivity.
If the user wants to provide a full visibility of arbitrary
signals, it is extremely challenging to do this in a
resource efficient way. Veloce delivers a software
technique called Software State Replay (SSR), which
re-computes all data for a chip from a limited amount
of per chip storage data. Typically, in any debugging
process, the user does not need to look at the whole
design and the entire simulation time. One looks at
subsets of time and space (signals), so having a
mechanism to be able to flexibly run soft computation
on a subset of time and space is a way to potentially
give access to a large amount of time for all of the
design. This feature reduces the time required to access
the suspected problem segment that needs debugging.
Veloces selective upload in time and space feature
accelerates time to visibility. The user selects a set of
signals and the time window of a test and during
runtime, debug data is exported from emulator.
Veloce visibility system is architected for flexible timeto-visibility data capture to accelerate the debugging
process. Distributed SSR visibility computation per
chip is well-suited for the evolution of the computer
industry. The SSR has a set of independent computations for each chip which can be distributed across
many CPUs or cores. The On-Demand visibility further
accelerates time-to-visibility by running reconstruction
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CONCLUSION
Veloce is a high-performance, high-capacity platform
with a small footprint. Its unique architecture gives
users flexibility to build verification environments using
either a hardware stimulus, a software stimulus, or a
combination of the two.
Because Veloce is standards compliant, it fosters interoperability with software simulators. Veloce accurately
models the users design into the emulator, irrespective
of whether its a single clock domain or a multi-clock
domain design.
Finally, Veloces dedicated debug/visibility infrastructure
and simulation-like debug make it an easy-to-use
verification platform.
Copyright 2009 Mentor Graphics Corporation. This document contains information that is proprietary to Mentor Graphics Corporation and may
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MGC 05-09
5819: 080926