Date: 17-05-2013

UNIVERSITY OF ENGINEERING
AND TECHNOLOGY, TAXILA

DEPARTMENT OF ELECTRICAL ENGINEERING

TITLE: Register File Design

LAB:

GROUP:

B2

SUBJECT: Computer Organization

SUBMITTED TO: Sir Tahir Muhammad
SUBMITTED BY: Ameer Hamza
REGISTRATION NUMBER:

2011-EE-197

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Lab-08

2011-EE-197

Task-1: Design Of A 4-Bit Register Using Given D-Flip Flop Code

Verilog Code:
/* Subject: Computer Organization
Name: Ameer Hamza
Registration Number: 2011-EE-197
Group: B2
Lab Number: 8
Description: Register File Design
*/
//Using Behavorial Modeling for D-Flip Flop Design
module DFF(OUT,IN,RST,CLK);
parameter n=4;
output [n-1:0]OUT;
input [n-1:0]IN;
input RST;
input CLK;
reg [n-1:0]OUT;
always @(posedge CLK)
begin
if (RST)
OUT=0;
else
OUT=IN;
end

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endmodule
//Define module for 2x1 Mux
module MUX_2x1(Q,S,D0,D1);
//Declare I/O ports
output Q;
input S,D0,D1;
//Instantiate logic gate primitives
not X0(S0,S);
and X1(W0,S0,D0);
and X2(W1,S,D1);
or X3(Q,W0,W1);
endmodule
//Define module for 2x1 Quad Mux
module Q_MUX_2x1(Q,S,D0,D1);
//Declare I/O ports
output [3:0]Q;
input [3:0]D0,D1;input S;
//Instantiate 2x1 Mux four times
MUX_2x1 X0(Q[0],S,D0[0],D1[0]);
MUX_2x1 X1(Q[1],S,D0[1],D1[1]);
MUX_2x1 X2(Q[2],S,D0[2],D1[2]);
MUX_2x1 X3(Q[3],S,D0[3],D1[3]);
endmodule
//Define module for combinational circuit (Register)
module CC(A,IN,LD,CLK,RST);
//Declare I/O ports
output [3:0]A;
input [3:0]IN;input LD,CLK,RST;
//Declare internal nets

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wire [3:0]W;
//Instantiate 2x1 Quad Mux
Q_MUX_2x1 X0(W,LD,A,IN);
//Instantiate D-Flip Flop
DFF X1(A,W,RST,CLK);
endmodule
//Define stimulus/test module
module TEST();
//Declare I/O variables
reg [3:0]IN;reg LD,CLK,RST;
wire [3:0]A;
//Instantiate combinational circuit (Register)
CC X0(A,IN,LD,CLK,RST);
//Use always block & initiate clock from '0' & stimulate inputs
always #5 CLK=~CLK;
initial
begin
CLK=0;IN=4'd7;LD=1;RST=0;
#10 IN=4'd7;LD=1;RST=1;
#10 IN=4'd7;LD=0;RST=0;
#10 IN=4'd7;LD=1;RST=0;
end
endmodule
Waveform:

2011-EE-197

17-05-2013

Lab-08
Task-2: Design Of A Register File Using Four 4-Bit Registers

Verilog Code:
/* Subject: Computer Organization
Name: Ameer Hamza
Registration Number: 2011-EE-197
Group: B2
Lab Number: 8
Description: Register File Design
*/
//Using Behavorial Modeling for D-Flip Flop Design
module DFF(OUT,IN,RST,CLK);
parameter n=4;
output [n-1:0]OUT;
input [n-1:0]IN;
input RST;

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input CLK;
reg [n-1:0]OUT;
always @(posedge CLK)
begin
if (RST)
OUT=0;
else
OUT=IN;
end
endmodule
//Define module for 2x1 Mux
module MUX_2x1(Q,S,D0,D1);
//Declare I/O ports
output Q;
input S,D0,D1;
//Instantiate logic gate primitives
not X0(S0,S);
and X1(W0,S0,D0);
and X2(W1,S,D1);
or X3(Q,W0,W1);
endmodule
//Define module for 2x1 Quad Mux
module Q_MUX_2x1(Q,S,D0,D1);
//Declare I/O ports
output [3:0]Q;
input [3:0]D0,D1;input S;
//Instantiate 2x1 Mux four times
MUX_2x1 X0(Q[0],S,D0[0],D1[0]);
MUX_2x1 X1(Q[1],S,D0[1],D1[1]);

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MUX_2x1 X2(Q[2],S,D0[2],D1[2]);
MUX_2x1 X3(Q[3],S,D0[3],D1[3]);
endmodule
//Define module for combinational circuit (Register)
module CC(A,IN,LD,CLK,RST);
//Declare I/O ports
output [3:0]A;
input [3:0]IN;input LD,CLK,RST;
//Declare internal nets
wire [3:0]W;
//Instantiate 2x1 Quad Mux
Q_MUX_2x1 X0(W,LD,A,IN);
//Instantiate D-Flip Flop
DFF X1(A,W,RST,CLK);
endmodule
//Define module for Registers Hierarchy
module REG(R0_OUT,R1_OUT,R2_OUT,R3_OUT,DATA,LD,CLK,RST);
//Declare I/O ports
output [3:0]R0_OUT,R1_OUT,R2_OUT,R3_OUT;
input [3:0]DATA,LD;input CLK,RST;
//Instantiate combinational circuit (Register) four times
CC X0(R0_OUT,DATA,LD[0],CLK,RST);
CC X1(R1_OUT,DATA,LD[1],CLK,RST);
CC X2(R2_OUT,DATA,LD[2],CLK,RST);
CC X3(R3_OUT,DATA,LD[3],CLK,RST);
endmodule
//Define module for 2x4 Decoder
module DEC_2x4(D,I);
//Declare I/O ports

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output [3:0]D;
input [1:0]I;
//Instantiate logic gate primitives
and X0(D[0],~I[0],~I[1]);
and X1(D[1],I[0],~I[1]);
and X2(D[2],~I[0],I[1]);
and X3(D[3],I[0],I[1]);
endmodule
//Define module for 4x1 Mux
module MUX_4x1(Q,I0,I1,I2,I3,S);
//Declare I/O ports
output Q;
input I0,I1,I2,I3;input [1:0]S;
//Declare internal nets
wire [3:0]W;
//Instantiate logic gate primitives
and X0(W[0],I0,~S[0],~S[1]);
and X1(W[1],I1,S[0],~S[1]);
and X2(W[2],I2,~S[0],S[1]);
and X3(W[3],I3,S[0],S[1]);
or X4(Q,W[0],W[1],W[2],W[3]);
endmodule
//Define module for 4x1 Quad Mux
module Q_MUX_4x1(Q,I0,I1,I2,I3,S);
//Declare I/O ports
output [3:0]Q;
input [3:0]I0,I1,I2,I3;input [1:0]S;
//Instantiate 4x1 Mux four times
MUX_4x1 X0(Q[0],I0[0],I1[0],I2[0],I3[0],S);

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MUX_4x1 X1(Q[1],I0[1],I1[1],I2[1],I3[1],S);
MUX_4x1 X2(Q[2],I0[2],I1[2],I2[2],I3[2],S);
MUX_4x1 X3(Q[3],I0[3],I1[3],I2[3],I3[3],S);
endmodule
//Define module for Register File
module REG_FILE(A_DATA,B_DATA,AS,BS,DS,LD_EN,D_DATA,CLK,RST);
//Declare I/O ports
output [3:0]A_DATA,B_DATA;
input [1:0]AS,BS,DS;input LD_EN,CLK,RST;input [3:0]D_DATA;
//Declare internal nets
wire [3:0]DEC_OUT,LOAD,R0_OUT,R1_OUT,R2_OUT,R3_OUT;
//Instantiate 2x4 Decoder
DEC_2x4 X0(DEC_OUT,DS);
//Instantiate logic gate primitives
and X1(LOAD[0],LD_EN,DEC_OUT[0]);
and X2(LOAD[1],LD_EN,DEC_OUT[1]);
and X3(LOAD[2],LD_EN,DEC_OUT[2]);
and X4(LOAD[3],LD_EN,DEC_OUT[3]);
//Instantiate Registers Hierarchy
REG X5(R0_OUT,R1_OUT,R2_OUT,R3_OUT,D_DATA,LOAD,CLK,RST);
//Instantiate 4x1 Quad Mux two times
Q_MUX_4x1 X6(A_DATA,R0_OUT,R1_OUT,R2_OUT,R3_OUT,AS);
Q_MUX_4x1 X7(B_DATA,R0_OUT,R1_OUT,R2_OUT,R3_OUT,BS);
endmodule
//Define stimulus/test module
module TEST();
//Declare I/O variables
reg [1:0]AS,BS,DS;reg LD_EN,CLK,RST;reg [3:0]D_DATA;
wire [3:0]A_DATA,B_DATA;

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//Instantiate Register File

REG_FILE X0(A_DATA,B_DATA,AS,BS,DS,LD_EN,D_DATA,CLK,RST);
//Use always block for clock
always #5 CLK=~CLK;
//Monitor signal values & stimulate inputs (Starting clock at '0')
initial
begin
//>>>>>Loading all registers with 4'd0<<<<<
CLK=0;D_DATA=4'd7;DS=2'd0;AS=2'd0;BS=2'd0;LD_EN=1;RST=1;
//>>>>>Loading R0 with 4'd7 & getting output at R0 in both muxes<<<<<
#10 D_DATA=4'd7;DS=2'd0;AS=2'd0;BS=2'd0;LD_EN=1;RST=0;
//>>>>>Loading R1 with 4'd7 & getting output at R1 in both muxes<<<<<
#10 D_DATA=4'd7;DS=2'd1;AS=2'd1;BS=2'd1;LD_EN=1;RST=0;
//>>>>>Loading R2 with 4'd7 & getting output at R2 in both muxes<<<<<
#10 D_DATA=4'd7;DS=2'd2;AS=2'd2;BS=2'd2;LD_EN=1;RST=0;
//>>>>>Loading R3 with 4'd7 & getting output at R3 in both muxes<<<<<
#10 D_DATA=4'd7;DS=2'd3;AS=2'd3;BS=2'd3;LD_EN=1;RST=0;
//>>>>>Again loading all registers with 4'd0<<<<<
#10 D_DATA=4'd7;DS=2'd0;AS=2'd0;BS=2'd0;LD_EN=1;RST=1;
//>>>>>Loading R0 with 4'd7 & getting output at R0 and R1<<<<<
#10 D_DATA=4'd7;DS=2'd0;AS=2'd0;BS=2'd1;LD_EN=1;RST=0;
//>>>>>Loading R1 with 4'd7 & getting output at R2 and R1<<<<<
#10 D_DATA=4'd7;DS=2'd1;AS=2'd2;BS=2'd1;LD_EN=1;RST=0;
//>>>>>Loading R2 with 4'd7 & getting output at R2 and R3<<<<<
#10 D_DATA=4'd7;DS=2'd2;AS=2'd2;BS=2'd3;LD_EN=1;RST=0;
//>>>>>Loading R3 with 4'd7 & getting output at R0 and R3<<<<<
#10 D_DATA=4'd7;DS=2'd3;AS=2'd0;BS=2'd3;LD_EN=1;RST=0;
end
endmodule

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Waveform:

Lab-08

2011-EE-197