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Investigations on Dodecagonal Space Vector

Generation for Induction Motor Drives

Presented by
Anandarup Das
CEDT, IISc, Bangalore

Flow of presentation

Motivation for the present research.


Schemes to be presented

Hybrid space vector PWM strategy in linear and over-modulation region


involving hexagonal and dodecagonal space vector diagrams.

Development of two concentric dodecagons using conventional 3-level


inverters with capacitor balancing.

Further refinement of the above space vector structure into multiple 12-sided
polygons with conventional 3-level inverters.
Modulation strategies and PWM timing calculation of the above schemes.
Discussion on experimental verification

Steady state operation.

Transient results with motor accelerated upto rated speed with open-loop V/f
control

Harmonic performance of phase voltage and phase current under these


conditions
Conclusion

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Motivation for the present research


Multilevel inverters are popular for high power drives because of low
switching losses and low harmonic distortion in the output voltage.
In many multilevel inverter fed high power drives, the switching frequency
of the inverter is limited because of large dv/dt stress on the devices and the
motor and higher switching losses.
However, with low switching frequency, lower order harmonics e.g. 5th and
7th order can be a considerable percentage of the total current, in particular
during over-modulation and 6-step operation.
So a trade-off is required to maintain the quality of the inverter output
voltage without resorting to higher switching frequency. In this regard, a
dodecagonal space vector diagram is very desirable that eliminates all the 5th
and 7th order harmonics from the phase voltage, leaving the next set of
harmonics at (12n1), n=integer.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Evolution of space vector structures (Hexagonal and 12-sided)


Hexagonal space vectors.

2-level
3-level

5-level

12-sided polygonal space vectors.


5

3
2

6
7

1
8

12

9 10 11

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Proposed research schemes


In the proposed work, a multilevel inverter topology is described which
produces hexagonal space vector diagrams in lower-modulation region and a
dodecagonal space vector structure in the higher modulation region.
In another scheme, a multilevel voltage space vector structure with vectors
on the dodecagon is generated by feeding an open-end winding IM drive by
two three level inverters.
In a third scheme, a high resolution PWM technique is proposed involving
multiple dodecagonal space vector structures, that can generate highly
sinusoidal voltages at a reduced switching frequency.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Part-1
A Combination of Hexagonal and
Dodecagonal Voltage Space Vector Diagram
for Induction Motor Drives

Evolution of space vector structures (Hexagonal and 12-sided)


Hexagonal space vectors.

2-level
3-level

5-level

12-sided polygonal space vectors.

1
8

12

9 10 11

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Voltage space vector diagram of the proposed scheme


End of linear modulation

Consists of four concentric hexagonal


diagrams with different radii (0.366kVdc ,
0.634kVdc , 1kVdc and 1.366kVdc).

Operates in the inner hexagons at lower


voltage to retain the advantages of
multilevel inverter like low switching
frequency.
At higher voltage, the outermost
hexagon and the 12-sided polygonal space
vector structure is used resulting in highly
suppressed 5th and 7th order harmonics.

OE: 1.225kVdc

The leads to 12-step operation at rated


voltage operation, leading to the complete
elimination of 6n1 harmonics. (n=odd)
from the phase voltage.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Inverter Topology

Consists of three cascaded 2-level inverters

Two inverters are supplied with a dc bus of


0.366kVdc while the third one is supplied with
a dc bus of 0.634kVdc.

C
D

Switch status for different levels of pole voltage

R-phase
B
O
Pole voltage of overall inverter-vAO
Pole voltage of INV3- vBO
Pole voltage of INV2-vAB
Pole voltage of INV1-vCD

Pole voltage

Level

S11

S21

S31

1.366kVdc

1.0kVdc

0.366kVdc

0Vdc

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Transformer connection for generation of 12-sided


polygonal voltage space vector
Asymmetric DC-links are easily realized by a combination of star-delta
transformers, since 0.634kVdc=3 x 0.366kVdc.

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10

Comparison with hexagonal space vector structure

Radius of dodecagon

The modulation index (m), is defined as the ratio of


the length of the reference vector to the length of the
radius of the dodecagon. m = 0.966 in linear
modulation and m =1 at 12-step operation.
Here, the radius of the dodecagon is 1.225kVdc.Thus
the maximum fundamental phase voltage available from
this space vector diagram is 0.806kVdc (in 12-step).
It is known that, the maximum fundamental voltage
available from a conventional hexagonal space vector
diagram in 6-step mode is 0.637Vdc and equal to
0.577Vdc at the end of linear modulation.
For comparison purpose, if the maximum fundamental
voltage available in 6-step mode and 12-step mode are
made equal to 0.637Vdc, then k = 0.637/0.806=0.789.

radius= 1.225kVdc

For k = 0.789, the maximum phase voltage available


here in linear modulation is 0.615Vdc and equal to
0.637Vdc in 12-step mode of operation. There is hence
an increase in linear modulation range.

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11

Modulating waveform

The modulating waveform for phase-A for 35Hz operation (linear


modulation range) is shown.
The modulating waveform is synchronized with the start of the sector
(sampling interval is always a multiple of twelve).

Because of asymmetric voltage levels, three asymmetric synchronized


triangles are used; their amplitudes are in the ratio 1:3:1.
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12

Switching sequence analysis


Three pole voltages are shown for a 60
degree interval at 35Hz operation.
Level shifted SVPWM is used here.

In A phase the voltage level fluctuate


between levels 3 and 2 , and in C
phase the voltage level fluctuates
between levels 1 and 0 .
The sequence in which the switches
are operated are as follows:
(200),

(210), (211), (311), (321), (311), (211),


(210), (211), (311), (321), (211), (221),
(321), (221), (210), (220), (221), (321),
(331), (221), (220), where the numbers in

brackets indicate the level of voltage.

This sequence corresponds to 2


samples per sector. There are altogether
12 sectors spanning from 00 to 300, 300
to 600 and so on.
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13

Experimental Setup
A digital signal processor (DSP), TMS320LF2812 is used for experimental
verification.

For different levels of output in the pole voltage, three carriers are required.
However, it is difficult to synthesize three carrier waves in the DSP, as such only
one carrier is used and the modulating wave is appropriately scaled and level
shifted.
A 3.7kW induction motor was fed by the proposed inverter operating under
open loop constant V/f control at no load. The motor was made to run under
no load in order to show the effect of changing PWM patterns of the generated
voltage on the motor current, particularly during transient conditions.
In order to keep the overall switching frequency within 1 KHz, number of
samples is decided as follow:
Upto 20 Hz operation: 4 samples per sector.
20 Hz-40 Hz: 2 samples per sector.
Beyond 40 Hz: 1 sample per sector-extending up to final 12-step mode.
Individual inverters are switched less than half of the total cycle.

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14

Experimental results-Operation at 10 Hz
Normalized harmonic spectrum of
Phase current
Phase voltage

Phase voltage

Phase current

Phase voltage and current waveforms

Overall inverter

INV3
INV2
INV1

Pole voltage waveforms

Switching happens within the innermost


[Space Vector]
hexagon space vectors.
As seen from the pole voltage waveforms,
only the lower inverter is switched while the
other two inverters are off, hence the
[Inverter Topology]
switching loss is low.
Four samples are taken in each sector, so
INV3 switching frequency is
(12x4X10=480Hz). The first carrier band
harmonics also reside around 48 times
fundamental.

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15

Experimental results-Operation at 30 Hz
Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage

Phase current
Phase voltage and current waveforms

Overall inverter

[Space Vector]

INV2
INV2 switches
INV3
INV1
Pole voltage waveforms

The space vectors that are switched


lie on the boundaries of the second
and third hexagon from the center.

Number of samples are reduced


from four to two, thus switching
frequency is (fs=12X2x30=720Hz).
INV3 and INV1 are switched about
1/3rd of the total cycle, while INV2
is switched about 20% of the cycle.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

[Inverter Topology]

16

Operation at 47 Hz ( end of linear modulation range)


Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage

Phase current
Phase voltage and current waveforms
Overall inverter

INV2
INV3
INV1

One sample is taken at the start of


a sector, so switching frequency is
only around (12X47=564Hz).
The space vectors that are
switched lie between the outer
hexagon and the 12-sided
polygon.
[Space Vector]

Pole voltage waveforms


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17

Operation at 50 Hz ( 12-step operation)


Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage

Phase current

Phase voltage and current waveforms


Overall inverter
INV2

INV3
INV1

Complete elimination of 6n1


harmonics (n=odd) from the phase
voltage.
One sample is taken at the start of a
sector (fs=12X1x50=600Hz).
Each inverter is switched only once in
a cycle.

Pole voltage waveforms


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Inverter Topology

18

Input current at 50 Hz ( 12-step operation)


Phase voltage
Phase current

Input phase
voltage

Input line
current

The input current to the inverter is not peaky in nature, because of the
presence of the star-delta transformers.

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

19

Motor acceleration with open loop V/f Control

Phase
voltage

Phase
current
Transition of motor phase voltage and current
from 24 samples to 12 samples per cycle at 40Hz

Transition of motor phase voltage and current


from outermost hexagon to 12-step operation.

Because of the suppression of the 5th and 7th order harmonics, the motor current
changes smoothly during the transition when the number of samples per sector is
reduced from two to one at 40Hz operation.
As the speed of the motor is further increased, the inverter switching states pass
through the inner hexagons and ultimately the phase voltage becomes a 12-step
waveform.
Under all operating conditions, the carrier is synchronized with the start of the
sector.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

20

Total Harmonic Distortion upto 100th harmonic


Harmonic performance of phase voltage and current
10Hz

30 Hz

48.25 Hz

50Hz

Voltage THD

57.59%

27.51%

14.67%

17.54%

Voltage WTHD

0.81%

0.7%

0.97%

1.04%

100

THD

V
n2

V1

Vn


n2 n
WTHD
V1
100

Current THD

12.31%

10.59%

15.6%

19.54%

Current WTHD

0.28%

0.45%

1.2%

1.5%

2
n

It is seen that voltage WTHD is quite low for all the operating conditions, as
such the torque pulsation and harmonic heating in the machine is minimized.

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21

Comparison with conventional structures

A simplified comparative study is made between the proposed topology and


the existing multilevel inverter configurations viz. 3-level NPC and 4-level NPC
inverters used for induction motor drives.
The conduction and switching losses incurred in the inverter, and motor
phase voltage harmonic distortions are numerically calculated by computer
simulation for comparison.
A linear turn-on and turn-off switching profile is used for loss calculation.
Losses incurred in snubber circuits, protection circuits, gate drives and due to
leakage currents are neglected.
A 2.3kV, 373kW induction motor is driven by a 3-level NPC, 4-level NPC and
the proposed inverter. The inverter drives the induction motor under full load
condition at around 0.85 p.f. lagging. Numbers of samples in a cycle are taken
as 24.

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22

Loss comparison with conventional structures

unit

Phase
voltage
WTHD

IGBT
Switching
loss

IGBT
Conduction
loss

Conduction
loss in antiparallel
diodes

Clamping
diode
conducti
on loss

Total
Loss

40 Hz

Linear modulation

3-level NPC

0.68

95

2180

272

240

2787

4-level NPC

0.46

61

2400

414

350

3225

Proposed Inv

0.46

96

1884

306

2286

48 Hz

Over modulation

3-level NPC

1.22

27

2370

165

130

2692

4-level NPC

0.89

20

2616

243

169

3049

Proposed Inv

0.55

25

1995

207

2227

50 Hz

Square wave mode of operation

3-level NPC

4.64

2511

184

2701

4-level NPC

4.64

12

2730

258

3000

Proposed Inv

1.04

10

2034

180

2224

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23

Observations

The phase voltage WTHD for the proposed inverter shows considerable
improvement, particularly at higher modulation indices and the 12-step
mode of operation, because of the suppression or elimination of the 6n1
(n=odd) harmonics.
Conduction losses are more dominant than switching losses for IGBT made
inverters. As such, presence of the clamping diodes in NPC inverters
increases the total losses of the inverter. The proposed inverter does not
have any clamping diode and is devoid of any such losses. The switching
losses also remain low for the proposed inverter.
It is seen that the conduction losses in the proposed inverter are always less
than the conventional inverters. This is because in the proposed inverter, for
any level of pole voltage output, two current carrying switches remain in
conduction. This is not always the case in NPC inverters; e.g. for a four level
inverter, at higher modulation indices, three switches per phase carry the
phase load current when the total dc bus voltage is obtained at the pole.
Conduction losses in the proposed inverter are further less in overmodulation region because of the fact that the r.m.s. current in the inverter
is less compared to conventional NPC inverters, due to the suppression or
elimination of the 6n1 (n=odd) harmonics.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

24

Synopsis

A multilevel inverter topology is described which produces hexagonal


space vector structures in lower-modulation region and a dodecagonal
space vector structure in the higher modulation region.

In the extreme modulation range, voltage vectors at the vertices of the


outer dodecagon and the vertices from the outer most hexagon is used
for PWM control, resulting in highly suppressed 5th and 7th order
harmonics thereby improving the harmonic profile of the motor current.
This leads to the 12-step operation at 50Hz where all the 5th and 7th order
harmonics are completely eliminated.

At the same time, the linear range of modulation extends upto 96.6% of
base speed. Because of this, and the high degree of suppression of lower
order harmonics, smooth acceleration of the motor upto rated speed is
possible.

Apart from this, the switching frequency of the multilevel inverter output
is always limited within 1 kHz. The middle inverter ( high voltage inverter)
devices are switched less than 25% of the output fundamental switching
period.
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25

Part-II
Generation of Multilevel Dodecagonal Space
Vector Diagram

Evolution of space vector structures (Hexagonal and 12-sided)


Hexagonal space vectors.

2-level
3-level

5-level

12-sided polygonal space vectors.

1
8

12

9 10 11

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27

Multilevel dodecagonal space vector diagram

This is an extension of the single


dodecagonal space vector
structure into a multilevel
dodecagonal structure.
Compared to conventional
dodecagonal space vector
structure, the device ratings and
dv/dt stress on them are
reduced to half.
The switching frequency is also
reduced to maintain the same
output voltage quality.
Here the added advantage is the
complete elimination of 6n1
harmonics, n=odd, from the
phase voltage throughout the
modulation index.
The linear modulation range is
also extended compared to the
hexagonal structure.

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28

Multilevel 12-sided polygonal space vector structure

Consists of two concentric


dodecagonal space vector
structures.
Unlike conventional
hexagonal multilevel
structure, here the subsectors are isosceles
triangles rather than
equilateral triangles.
Each sector is thus divided
into four sub-sectors as
shown.

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29

Inverter Structure

In order to realize the proposed space vector structure, two conventional


three level NPC inverters are used to feed an open ended induction motor.
The two inverters are fed from asymmetrical dc voltage sources which can be
obtained from the mains with the help of star-delta transformers and
uncontrolled rectifiers.
Because of capacitor voltage balancing of the NPC inverters, only two dc
sources are used.
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30

Switching state combination for realizing space vector 16

INV1 produces vector X(220) while INV2 produces vector Y(022).


When they are combined, the resultant vector Z(220, 022) is produced.
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31

Timing calculation for dodecagonal space vector locations


Here, the timings for which adjacent vectors are switched are obtained as,

Vref sin
6
*T ;
V1T1
s

sin
6

V2T2

Vref sin

sin
6
T0 Ts T1 T2 ;

* Ts ;

This is similar to conventional space vector PWM.


However, this requires calculation of sine values through a look-up table,
which takes unnecessary memory and time in a DSP.
A better algorithm has been generated which can calculate the timings by
sampling six reference rotating phasor.

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32

Timing relation among different space vectors


V2, T2

V4, T2

V1, T0
V1, T1
V1, T1
Point Switched
for

Point

Switched
for

V1

T1

V1

T1= 2T1-TS

V2

T2

V4

T2 = 2T2

T0

V1

T0 = 2T0

Instead of vectors on the


vertices of the sector, three
nearest enclosing vectors are
now switched. This is done to
achieve multilevel switching.
The time durations for which
the original vectors need to be
switched is modified. The new
timing durations are achieved by
volt-second balance.
The timing relation can be
extended to other sub-sectors.

Note:

T0 >= 0.
T1+T2+T0= T1+T2+ T0=TS.

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33

Capacitor balancing scheme

The inner dodecagonal


space vectors (points 1-12)
have four multiplicities which
are complementary in nature
in terms of capacitor
balancing.
The outer dodecagonal
space vectors ( points 1336) either do not cause any
capacitor unbalancing, or
have complementary states
to maintain capacitor
balancing.

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34

Inner 12-sided polygon-switching multiplicities for point-1

C2 is discharged, C4 is charged.

C2 is discharged, C3 is charged.

C1 is discharged, C4 is charged.

C1 is discharged, C3 is charged.

The four switching multiplicities are complementary in nature in terms of capacitor balancing.
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35

Outer 12-sided polygon-switching multiplicities

Point-13, two multiplicities

C4 is discharged, C1 & C2 are

C3 is discharged, C1 & C2 are

undisturbed.

undisturbed.

Point-36: no multiplicity, no
capacitor disturbance

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Point-14: no multiplicity, no
capacitor disturbance

36

Experimental results-15 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage

Pole voltagehigh voltage


inverter
Pole voltage-low
voltage inverter

Phase current

Phase current

Four samples are taken in each sector and switching takes place entirely in
the inner 12-sided polygon.
The phase voltage harmonics reside at 15x12x4=720 Hz, which is 48 times
the fundamental. However, the switching frequency of the pole voltage of
INV1 is (24x15=) 360Hz, while that of INV2 is (32x15=) 480Hz.
The higher voltage inverter switches about 50% of the cycle.
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37

Experimental results-23 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage

Pole voltagehigh voltage


inverter
Pole voltage-low
voltage inverter

Phase current

Phase current

Three samples are taken in each sector and switching takes place at the
boundary the inner 12-sided polygon. All the 6n1 harmonics, n=odd, are
absent from the phase voltage, while the rest are highly suppressed.
The switching frequencies of the pole voltage of INV1 and INV2 are
respectively (18x23=) 414Hz and (24x23=) 552Hz, with output phase voltage
switching frequency at 828Hz (=23x12x3).
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38

Experimental results-40 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltagehigh voltage
inverter
Pole voltage-low
voltage inverter

Phase current

Phase current

Two samples are taken in each sector and switching takes place between the
inner and outer dodecagons.
This is also seen in the phase voltage waveform, since the outer envelope of the
waveform at lower frequency becomes the inner envelope at higher frequency.
The harmonic spectrum of the phase voltage and current shows the absence of
peaky harmonics throughout the range.
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39

Experimental results-48 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage

Pole voltagehigh voltage


inverter
Pole voltage-low
voltage inverter

Phase current

Phase current

This is the end of the linear modulation of operation.


Here the number of samples per sector is two, as such the switching
frequency sidebands reside around 24 times the fundamental. The switching
frequency of the pole voltages of INV1 and INV2 is respectively (48x12=)
576Hz and (48x16=) 768Hz, with an output phase voltage switching
frequency of 1152Hz (48x12x2).
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40

Experimental results-49.9 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltagehigh voltage
inverter

Phase current

Pole voltage-low
voltage inverter
Phase current

At the end of end over-modulation region, 24 samples are taken in a sector,


corresponding to the vertices of the polygon.

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41

Experimental results-50 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltagehigh voltage
inverter

Phase current

Pole voltage-low
voltage inverter
Phase current

This is the 12-step operation, where one sample is taken at the start of a
sector. The phase voltage and current is completely devoid of any 5th and 7th
order harmonics.

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42

Total Harmonic Distortion upto 100th harmonic


Harmonic performance of phase voltage and current
Voltage
THD

Voltage
WTHD

Current
THD

Current
WTHD

15Hz

75.4%

1.48%

24.49%

0.56%

23Hz

21.2%

0.54%

9.19%

0.48%

40Hz

24.85%

0.71%

12.08%

0.65%

48Hz

9.67%

0.33%

5.52%

0.26%

49.9Hz

7.26%

0.28%

4.68%

0.24%

50Hz

17.54%

1.04%

19.54%

1.5%

100

THD

2
n

n2

V1

Vn


n2 n
WTHD
V1
100

It is seen that voltage WTHD is quite low for all the operating conditions, as
such the torque pulsation and harmonic heating in the machine is minimized.

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43

Acceleration of the motor

Phase
voltage
Phase
current
Transition of motor phase voltage and current
from inner to outer 12-sided polygon

Transition of motor phase voltage and current


from over-modulation to 12-step operation.

In both the cases, the motor current changes smoothly as the motor
accelerates. This happens because of the use synchronized PWM and total
elimination of 6n1 harmonics, n=odd, from the phase voltage throughout
the modulation index.

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44

Experimental Results-capacitor unbalancing at 20 Hz

Vc1, Vc2
Deliberate unbalancing

Controller action taken

Capacitor unbalance is
done at steady state
with the motor running
at 20 Hz speed.
Both side capacitors are
deliberately unbalanced
and after some time
controller action is
taken.

Vc3, Vc4

C1,C2 : higher voltage side capacitors


C3,C4 : lower voltage side capacitors
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45

Experimental Results-capacitor unbalancing at 40Hz

Controller action taken

Vc1, Vc2

Deliberate unbalancing
Vc3, Vc4

Both the sides are made


unbalanced at the same
time and are seen to
come back to the
balanced state.
Compared to the 20 Hz
case, it requires more
time to restore voltage
balance, since the
number of multiplicities
in the outer polygon is
less.

C1,C2 : higher voltage side capacitors


C3,C4 : lower voltage side capacitors
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46

Synopsis

An improved space vector diagram is proposed here that is composed of


of two concentric dodecagons. It reduces the device rating and the dv/dt
stress on the devices to half compared to existing 12-sided schemes.

The entire space vector diagram is divided into smaller sized isosceles
triangles. PWM switching on these smaller triangles reduces the inverter
switching frequency without compromising on the output voltage quality.

The proposed topology is realized by feeding an open-end induction


motor with two conventional 3-level NPC inverters, where, the high
voltage inverter always switches at nearly half the output phase voltage
switching frequency.

Additionally, the mechanism for capacitor balancing, using switching state


redundancies is also proposed for the full modulation range

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47

Part-III
A Voltage Space Vector Diagram Formed By
Six Concentric Dodecagons

Evolution of space vector structures (Hexagonal and 12-sided)


Hexagonal space vectors.

2-level
3-level

5-level

12-sided polygonal space vectors.

1
8

12

9 10 11

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Space Vector Structure


The space vector diagram consists of
six concentric dodecagonal structures
- A, B, C, D, E and F.
These are grouped as type-1 and
type-2 dodecagons, where type-2
dodecagons (A, C and E) lead type-1
dodecagons (B, D and F) by 150.

The radii of these polygons are in


the ratio r1: r2: r3: r4: r5: r6 =
1: cos (/12): cos (2/12):
cos (3/12) :cos (4/12) :cos (5/12).
The entire space vector diagram is
divided into 12 sectors each of width
300.

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Power Circuit of the Inverter

The power circuit of the inverter consists of 2 three level NPC inverters
feeding an open end induction motor.
These two inverters are fed from isolated dc voltage sources having voltage
ratio of 1:0.366. This ratio of voltages is obtained from a combination of star
delta transformers since 1:0.366= (3+1):1.

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Realization of space vector 27

Point 27 can have two switching combinations- (110,002) or (221,002).


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PWM timing calculations

PWM timing calculations are done separately for type-1 and type-2 dodecagons.

Later they are used to find a uniform timing relation.


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[movie]

56

PWM timing calculations type-2 polygon

V4, T2

V2, T2 Instead of switching points V and


1
V2, the same reference vector VR can
be realized by switching V3 and V4,
but with different time durations.
This will reduce the instantaneous
error between the reference vector
and the switching vectors, causing
multilevel operation of the inverter.

V3, T1
V1, T1
Point Switched
for

Point

Switched
for

V1

T1

V3(=k V1)

T1=T1/k

V2

T2

V4(=k V2)

T2=T2/k

T0

T0

Note:

k =V3/ V1=V2/ V4 is a fraction.


T1+T2+T0= T1+T2+ T0=TS.
provided

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T0 0

57

PWM timing calculations type-2 polygon


V2, T2

V4, T2

V3, T1

V1, T1

The same relation can be extended to the type-2 polygon.

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PWM timing calculations for both types of polygons

Points O,K and J are from type-1 polygon, while point F is on type-2 polygon.
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PWM timing calculations for both types of polygons


T2

r4
r5
T0
T1

Point Switched
for

Point

Switched
for

T0

T0 = T0 / (1-k1)

T1

T1=T1- T0 . k1/2

T2

T2=T2- T0 . k1/2

k1 =

(radius of inner dodecagon)


(radius of outer dodecagon).cos( 12 )

T1+T2+T0= T1+T2+ T0=TS.

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60

Experimental verification
A 3.7kW induction motor was fed by the proposed inverter under experimental
condition, operating under open loop constant V/f control at no load. The
motor was made to run under no load in order to show the effect of changing
PWM patterns of the generated voltage on the motor current.
In order to limit the switching frequency of the inverter, number of samples is
decided as follow:
Upto 10 Hz operation: 8 samples per sector.
10 Hz-30 Hz: 4 samples per sector.
30Hz-12step operation: 2 samples per sector leading to final 12-step mode.
The samples are always taken synchronized with the start of the sector.
A digital signal processor (DSP), TMS320LF2812 is used for experimental
verification. The DSP is used for calculating the PWM timing durations. The
actual gating signals to drive all the devices are generated using a SPARTAN
XC3S200 FPGA. The FPGA stores the look-up table for the switching state
combination of both the inverters for a particular space vector point.

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Experimental results-10 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltagehigh voltage
inverter
Pole voltage-low
voltage inverter

Phase current

Phase current

Switching happens within the innermost dodecagonal space vectors.


Here, the number of samples per sector is taken as 8, as such the voltage and
current harmonics reside around (12x8=) 96 times the fundamental.
Individual devices of INV1 and INV2 are respectively switched at (10x16=)
160 Hz and (10x48=) 480 Hz.
INV1 is switched only 1/3rd of a cycle, thereby the switching loss is less.
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Experimental results-20 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltagehigh voltage
inverter
Pole voltage-low
voltage inverter

Phase current

Phase current

Switching happens within the first and second dodecagonal space vectors.
4 samples are taken in a sector, so the first band of carrier harmonics
reside around 48 times the fundamental.
Because of the multilevel structure, all the harmonics are highly
suppressed.
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Operation at 24.5 Hz

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Experimental results-24.5 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage

Pole voltage- high


voltage inverter

Phase current

Pole voltage-low
voltage inverter
Phase current

Here the reference vector passes through the boundary of E dodecagon. As


such, switching happens sometimes among points on the D and E
dodecagons, while at other times among E and F dodecagons.
The high voltage inverter switches about 20% of the cycle, thus the switching
losses are minimized.
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67

Experimental results-46 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage

Pole voltage- high


voltage inverter

Phase current

Pole voltage-low
voltage inverter
Phase current

Two samples per sector are taken here.


The phase voltage waveform of phase A distinctly shows the presence of 20
steps in a cycle, although 24 vectors are switched altogether.
The phase voltage harmonics reside at (24x45=) 1080 Hz, while individual
devices of INV1 and INV2 switch at (5x45=) 225 Hz and (15x 45=) 675 Hz.
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20-steps in phase voltage at Operation at 46 Hz

Vectors numbered 37, 48, 50 and 60 switched at the positive peak of the
phase-A waveform have same projection on A-phase axis.
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69

Experimental results-49.9 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage

Pole voltage- high


voltage inverter

Phase current

Pole voltage-low
voltage inverter
Phase current

The phase voltage waveform of phase A shows the 20 steps in a cycle.


The switching vectors involved are located on the vertices of the A and B
dodecagons, because of very small zero periods in a cycle.

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20-steps in phase voltage at 49.9 Hz

Vectors numbered 49, 61 and 72 switched at the positive peak of the phase-A
waveform have same projection on A-phase axis.
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Experimental results-50 Hz operation


Normalized harmonic spectrum of
Phase voltage
Phase voltage

Pole voltage- high


voltage inverter

Phase current

Pole voltage-low
voltage inverter
Phase current

This is the 12-step operation of the inverter, when maximum fundamental


voltage is available.
Under this condition, INV1 and INV2 are switched 3 and 12 times respectively
in a cycle.
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Input current drawn from the grid

Motor phase voltage


Motor phase
current

Normalized harmonic spectrum of


input current

Grid side voltage


input current

Because of the presence of the star-delta transformer at the input that forms
the dc bus ratio, the input current is more sinusoidal than what is observed in a
single transformer supplying an uncontrolled rectifier

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Motor acceleration with open loop V/f Control

Phase
voltage

Phase
current
Transition of motor phase voltage and current
from 20 Hz to 30Hz

Transition of motor phase voltage and current


from over-modulation to 12-step operation.

In the first case, the reference vector starts from inside dodecagon E, crosses
through the boundary of it and finally settles below the D dodecagon.
In the second case, the number of samples per sector is changed from 2 to 1 at
12-step operation.

Correct calculation of the PWM timings and complete elimination of the 5th and 7th
order harmonics ensure that the motor current changes smoothly during the
transition.
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Comparison with a 5-level space vector diagram

unit

Phase
voltage
THD

Phase
voltage
WTHD

Phase
current
THD

Phase
Current
WTHD

20 Hz
5-level Inv

28.76

0.68

10.73

0.54

Proposed Inv

22.26

0.51

8.53

0.42

24.5 Hz
5-level Inv

19.78

0.54

9.85

0.52

Proposed Inv

16.24

0.42

7.14

0.43

46 Hz
5-level Inv

19.91

0.77

16.05

0.89

Proposed Inv

15.69

0.57

12.62

0.62

49.9 Hz

5-level Inv

15.3

1.31

18.8

3.07

Proposed Inv

7.26

0.28

4.68

0.24

50 Hz
5-level Inv

30.54

4.64

52.47

9.55

Proposed Inv

17.54

1.04

19.54

1.5

The harmonic distortion is less


in the proposed scheme.
This is more prominent in the
higher modulation indices
where the number of samples
per sector is less, thus the
switching frequency harmonics
containing 5th and 7th order
harmonics in the 5-level
scheme come closer to the
fundamental.
Because of the total
elimination of the these
harmonics from the phase
voltage in the present case, the
ripple content in the phase
voltage will be less.

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Harmonic performance in terms of flux ripple

The rms value of the flux ripple is calculated and plotted above under constant
V/f ratio and 24 samples in a fundamental period.
It shows that for most of the operating conditions, the flux ripple is around 1%
of the fundamental flux impressed on the machine, and thus restricts the
torque ripple in the machine.

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76

Synopsis

A new space vector diagram for induction motor drive is proposed, which
divides the space vector plane into six concentric dodecagons.

Here the space vector diagram is characterized by alternately placed type-1


and type-2 dodecagons which become closer to each other at higher radii. As
such the harmonics in the phase voltage are reduced.

Apart from this, the known benefits of dodecagonal space vector diagram
like the complete elimination of all 6n1 harmonics, (n=odd) from phase
voltage and the extension of linear modulation range, are also retained here.

The high voltage inverter having a voltage of about 3 times the lower one, is
switched almost 1/3rd compared to the low voltage inverter.

A comparison with 5-level inverter topology is also given which shows that
the present scheme produces less harmonic distortion in the phase voltage.

Because of the use of star-delta transformers for having the dc bus in the
ratio 1:0.366, the input current has lesser harmonics compared to the case
when a single transformer supplies the inverter.
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77

Conclusion

Different dodecagonal space vector diagrams are proposed in this work.

In one of the schemes, the space vector diagram consists of two concentric
dodecagons, with the radius of the outer one twice the inner one. This has the
benefit of reducing the device rating and dv/dt stress on the devices.

This is then further refined to distribute six dodecagons in the space vector
diagram. Switching on these closely spaced dodecagons will highly reduce the
harmonic content in the phase voltage, apart from totally eliminating all the 5th
and 7th order harmonics from the phase voltage.

In another work, a 4-level inverter with asymmetric dc links is used to generate


hexagonal space vector diagrams at lower modulation indices and a dodecagonal
space vector structure at higher modulation index finally leading to 12-step
operation of the inverter. This structure thus, incorporates the advantages of both
hexagonal and dodecagonal space vector diagrams.

With increased linear modulation range, less switching frequency and improved
harmonic spectrum, the proposed concepts may be considered as an interesting
addition to the field of multilevel inverters for high/medium voltage high power
applications.
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Papers out of this work

Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, "A
Combination of Hexagonal and 12-sided Polygonal Voltage Space Vector PWM control for
IM Drives Using Cascaded Two Level Inverters", IEEE Trans. On Industrial
Electronics, vol. 56, no. 5, May 2009, pp. 1657-1664.
Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, "A Pulse
Width Modulated Control of Induction Motor Drive Using Multilevel 12- sided Polygonal
Voltage Space Vectors", IEEE Trans. on Industrial Electronics, vol. 56, no. 7, July
2009, pp. 2441-2449.
Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, "A High
Resolution Pulse Width Modulation Technique Using Concentric Multilevel Dodecagonal
Voltage Space Vector Structures", Proc. of ISIE 2009, Jul. 2009. (Best paper award
in the conference).
Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar,
"Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor
Drive Using Conventional Three Level Inverters", Proc. of EPE 2009, Sep 2009, pp 1-8.
Anandarup Das, K. Sivakumar, Gopal Mondal and K. Gopakumar, "A Multilevel Inverter
with Hexagonal and 12-sided Polygonal Space Vector Structure for Induction Motor
Drive", Proc. of IECON 2008, Nov 2008, pp 1077-1082.
Anandarup Das and K. Gopakumar "A Voltage Space Vector Diagram Formed By Six
Concentric Dodecagons for Induction Motor Drives", communicated to IEEE Trans. on
Power Electronics.
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