Confidential

Mixed Signal Verification - Connectivity

RAK
By: Amar Dwarka
Date: 5/22/2013

Mixed Signal Verification Connectivity RAK

Audience: Engineers who want to understand how mixed signal
connectivity is handled in Cadence Verification flows and how to
control it if desired

Pre-requisite: Familiarity with either digital or analog simulation,

preferred to have completed Behavioral Modeling and Mixed Signal

Simulation and Debug RAKs

Goals:
Learn how connectivity is automatically handled in Cadence flows at the
interface of Logical, Electrical, and RNM nets
Learn what coercion is and how it benefits MS verification
Learn what IE Card is and how can be used to customize mixed signal
connectivity

2013 Cadence Design Systems, Inc. All rights reserved.

Table of Contents
Discipline Resolution (DR)

Basic Domain/Discipline Explanation

Discipline Resolution (DR) Explanation
Default Discipline Resolution
Detailed Discipline Resolution
No Discipline Resolution

Coercion

Basic Coercion Explanation

Coercion Enhancements
Coercion Example
rnm_coerce capability

Block Based Discipline Resolution (BDR)

IE Card
Scope Assignments
Parameter Assignments

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Confidential

Discipline Resolution

The Analog/Digital Domain Problem

MS simulation needs to take place across two incompatible domains:
discrete and continuous.
Analog signals are continuous. Digital signals are discrete.
The analog world exists in shades of gray. The digital world is black and
white.

Analog
domain

Digital
domain

Analog-toDigital
domain
boundary

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Analog
domain
Digital-toAnalog
domain
boundary

Domain Disciplines the Basics

A Verilog-AMS language declaration construct used to define domain
ownership: continuous or discrete.
Electrical discipline
Belonging to the continuous
domain
Specifies natures for
potential and flow of
conservative signals

Natures
6

Logic discipline
Belonging to the discrete
domain
Digital 4-state logic signals
(0,1,X,Z)
Wreal is a wire-real which
represents a real-valued
physical connection

electrical (continuous)

logic (discrete)

discipline electrical

discipline logic

domain continuous;
potential Voltage;
flow Current;
enddiscipline

domain discrete;
enddiscipline

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The Discipline Resolution Process

The goal of the discipline resolution process is to try and resolve all
domain-less nets to a specific domain discipline.
Algorithms are well defined in the Verilog-AMS LRM standard
The general process of discipline resolution (DR) is the following:
1. Domain-less nets are coerced into the electrical discipline
depending upon the leaf-level analog block where they are
connected
2. Any remaining domain-less nets, after the DR process, are
assigned to the default logic discipline
Two algorithms for discipline resolution are available: default and
detailed.
The algorithms can be invoked using the irun disres option and
occurs during elaboration.
-disres default | detailed |none

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Resolving Disciplines on Domain-less Nets

Consider the following hypothetical hierarchy of three levels with
domain-less nets:
Net 1

Net 1

Domain-less
nets

Port boundary

Net 2

Net 3
Net 3

Net 2
Port boundary
Net 4

Net 5

Net 6

D
Digital blocks

Net 4

Analog

Implicitly and explicitly declared

disciplines
8

Net 6

Net 5

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Digital

Analog

Discipline Resolution: Default

A single bottom-up traversal
Electrical disciplines
propagate up
Analog wins conflict
Connect Module
(Interconnect Element IE)
is auto inserted on
boundaries with conflicts
Invoked by default

Net 1

IE
Port boundary

Net 2

Net 3

Port boundary
Net 6

Net 4

D
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Digital

Net 5

Analog

Discipline Resolution: Detailed

Analog discipline propagates up
and then down the hierarchy
analog wins any conflict
Connect Modules (Interconnect
Element IE) are inserted on
boundaries with conflicts
Invoked with:

Net 1

Port boundary
IE

irun disres detailed

Net 2

Net 3

Port boundary
Net 6

Net 4

D
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Digital

Net 5

Analog

Discipline Resolution: None

Can be used when there is
a clear boundary between
analog and digital and you
want to turn DR process off.
This also can save
elaboration time as the DR
algorithm is not executed
but instead using the user
input to resolve domainless
entities.
The user input defining
these domainless entities
has to be explicit
Invoked with:

Net 1
Port boundary

Net 2

Net 3

Port boundary
Net 6

Net 4

Net 5

irun disres none

D
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Digital

Analog

Confidential

Coercion

Coercion
Coercion is the process by which a Verilog wire can
become a wreal net because of its hierarchical connections.
Note: Be aware that wreal coercion takes place before port
compatibility checking, so once the type of the port is fully known,
the port compatibility rules in Port Connections apply.

Please note that a wreal wire that is used in any behavioral

context should be declared explicitly as wreal type. This
ensures that the object used in the behavioral code do have
a well-defined type. The coercion mechanism is intended to
be used for pure interconnect wires only.

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Coercion Enhancements
When a wire/interconnect is connected to a net of the type
wreal, SV real, or VHDL real, it is coerced to wreal as well.
Such coercion can occur across multiple hierarchical levels.
The coercion process allows a seamless connection of
devices without worrying about the interconnects and their
types. This offers tremendous value in terms of model
portability across various design configurations.
In a different configuration, interconnect might be used to
connect electrical ports - this works seamlessly without any
change in the source code.

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Coercion Example
Uses wires as type-less interconnects
Allows different model abstractions to be reused in same
hierarchy
wires

Sub1

Source
Source
(model)
(circuit)
electrical
wreal

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top

Sub2
Sink
Sink
(model)
(circuit)
wreal
electrical

Coercion Example
The wire named w at the top level will be coerced to
wreal because the leaf-level port r is wreal.
// Hierarchy
`include "disciplines.vams"
module top();
wire w;
sub1 I1 (w);
sub2 I2 (w);
endmodule
module sub1(foo);
output foo;
source I1 (foo);
endmodule
module sub2(foo);
input foo;
sink
I3 (foo);
endmodule

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// Leaf-level blocks
`include "disciplines.vams
module source(r);
output r;
wreal r;
real realnumber;
initial begin
#1 realnumber = `wrealXState;
#1 realnumber = `wrealZState;
#1 realnumber = 2.2;
#1 realnumber = 1.1;
#1 $stop;
end
assign r = realnumber;
endmodule
module sink (r);
input r;
wreal r;
always @(r) begin
$display(" real value = %f", r);
end
endmodule

Support for Disabling Wreal Coercion Added

rnm_coerce has been added that enables you to turn off
wreal coercion:
on a specific instance and instances under it.
for instances whose master is a specific module and instances under
the module.
on specific nets.

Note: The -rnm_coerce option replaces the -wreal_coerce

option, which will be removed in a future release.

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Coercion -rnm_coerce
-rnm_coerce default | none| detailed | off scopeType-scopePossible values are:
none - disable wreal coercion. (traversal similar to disres none)
detailed - enable wreal coercion. (traversal similar to disres detailed)
default - enable global coercion with default resolution. (traversal similar to disres default)
off scopeType scope- disable local coercion in scope, coercion in other scope is ON.
If you are a digital-centric user running an AMS simulation that requires only the digital
solver, it is recommended to specify -rnm_coerce none.
Example:
rnm_coerce "off inst-top.dcinst-"
All the net of instance top.dcinst and its children will not be coerced to wreal; top level and
other instances will be coerced as normal.

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Confidential

Block Based Discipline Resolution

Block-Based Discipline Resolution (BDR)

Disciplines (both digital and electrical) can also be set implicitly on
design objects such as a library, cell, instance, or net using a forced
block-based discipline option as an irun argument.
This overrides any discipline coercion assignments that will be made
during the normal discipline resolution process (DR).
This option affects any domain-less nets or ports within and below
the specified scope.
Useful for designs using
Multiple-supplies to control connect module placement
Hard-defined analog/digital boundaries where DR process can be
turned off to speed up elaboration
Wreal number modeling with distinguishable wreal types

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Block-Based Discipline Resolution (BDR)

(continued)

The syntax for the -setdiscipline (-setd) option is:

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setd
setd
setd
setd
setd
setd
setd
setd
setd

"NET-hierarchical_net_name- discipline_name"
"INSTTERM-hierarchical_port_name- discipline_name"
"INST-hierarchical_instance_name- discipline_name"
"CELLTERM-lib_name.cell_name.port_name- discipline_name"
"CELLTERM-cell_name.port_name- discipline_name"
"CELL-lib_name.cell_name:view_name- discipline_name"
"CELL-lib_name.cell_name- discipline_name"
"CELL-cell_name- discipline_name"
"LIB-lib_name- discipline_name"

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Block-Based Discipline Resolution (BDR)

Using the irun -setdiscipline
option allows different default
disciplines to be applied to
different blocks, as shown in this
example:
Initially all the nets are Domainless nets

TOP

(continued)

Net 1

MID
Net 2

Net 3

irun -discipline logic

-setd inst-TOP.MID.Ana_Leaf- electrical
-setd inst-TOP.MID.Dig_leaf- logic_2V

Net 4

Net 5

Net 6

D1

D2

A1

Dig_leaf

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Ana_leaf

Confidential

IE card

AMSD Block IE Card

The ie statement specifies interface element parameters, optionally for
a particular design unit.
If you do not specify a design unit, the elaborator applies the parameter
settings to all interface elements globally.
You can use an ie statement to automate the process of creating a
custom discipline and connect rule.
The software applies the custom discipline to domainless nets in your
design. So, if you have digital modules with undeclared port disciplines,
you can use an ie statement to specify a discrete discipline for
domainless nets and the elaborator will insert the appropriate connect
module automatically.
The syntax for an ie statement is as follows:
ie vsup=supplyValue | [connrules=connrulesValue] [scope=scopeValue]
[parameter=value]

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AMSD Block IE Card, Scope Assignments

If you do not specify a scope assignment, the scope is
global. Valid scope=scopeValue assignments are as follows

scope

Definition

inst

Full hierarchical path to an instance to which you want to apply the specified interface element
parameters. If you specify more than one instance, you must separate each instance with a
space and enclose the string in double quotation marks.

cell

Specification of a cell to which you want to apply the specified interface element parameters. If
you specify more than one cell, you must separate each cell with a space and enclose the
string in double quotation marks.

instport

Full hierarchical path to one or more names of instance ports to which you want to apply the
specified interface element parameters. If you specify more than one name, you must
separate each name with a space and enclose the string in double quotation marks. For
example:
ie vsup=1.2 instport="a b c"

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AMSD Block IE Card, Scope Assignments

scope

Definition

cellport

One or more cell port names to which you want to apply the specified interface element
parameters. If you specify more than one cell port, you must separate each cell port name
with a space and enclose the string in double quotation marks.

net

One or more net names to which you want to apply the specified interface element
parameters. If you specify more than one name, you must separate each name with a space
and enclose the string in double quotation marks.

cellupport

One or more cell port names. The software applies the interface element parameters to upperlevel connections (ports or nets) to the specified cell port or ports. If you specify more than
one name, you must separate each name with a space and enclose the string in double
quotation marks.

lib

Logical name for library of design units to which you want to apply the specified interface
element parameters

You can use the wildcard character(s) in the scope name to specify more than one scope at a time. For example:
ie vsup=1.2 cellport="top.*_vdddig*"
could match top.jbb_vdddig_1, top.jbb_vdddig_2, top.jbc_vdddig_1, top.jbc_vdddig_2, and so on.
Note: For hierarchical-related specifications, that is, inst, instport, and net, wild cards do not match across the hierarchical
levels unless the wildcard is specified at the end of the string. For example, "a.*.d" would match "a.b.d", but not
"a.b.c.d". However, "a.*" could match "a.b" and "a.b.c.d".

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AMSD Block IE Card, Parameter Assignments

The software uses any parameter assignments you specify
to customize the connect rules. Any customizations you
specify apply to domainless nets only. Valid
parameter=value assignments for the ie statement are as
follows:
Parameter

Definition

vthi

Voltage value above which the simulator assigns a logical 1. The simulator determines the default value
from the connect rule.

vtlo

Voltage value below which the simulator assigns a logical 0. The simulator determines the default value
from the connect rule.

vx

Final real number for logical x. The simulator determines the default value from the connect rule.

tr

Rise time for analog transition, from vtlo to vthi or vx. Default Value: 0.2 ns

rlo

Output resistance for L2E when digital input is 0. Default Value: 200 Ohms

rhi

Output resistance for L2E when digital input is 1. Default Value: 200 Ohms

rx

Output resistance for L2E when digital input is x. Default Value: 40 Ohms

rz

Output resistance for L2E when digital input is z. Default Value: 10M Ohms

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AMSD Block IE Card, Parameter Assignments

Parameter

Definition

txdel

Controls the amount of wait time before a digital port is driven to x for the connectmodules E2L, E2L_2,
L2E, Bidir, and Bidir_2.
Measured in nano seconds.
Default Value: Four times the tr parameter. If the tr parameter is not specified for the ie statement, the
simulator uses the default tr value 0.2n and calculates the default txdel value as 0.8n.
Example:
amsd {
ie vsup=1.8 txdel=0.9n
}

mode

Specifies the type of connect module insertion in the ie card. You can assign two values to this
parameter:
merged - This is the default value. The merged value instructs the elaborator to insert a single merged
connectmodule for all the nets that are connected to the same port and require the same
connectmodule.
split - The split value instructs the elaborator to insert a separate connectmodule for every net
connected to the same port, irrespective of whether or not they require the same connectmodule.

vpso

Converts the PSO X state to a user-supplied voltage in AMS-CPF.

vdelta

Voltage delta value ranging from 0 to vsup. Default Value: vsup/64

vtol

Voltage tolerance value ranging from 0 to vdelta. Default Value: vdelta/4

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AMSD Block IE Card, Parameter Assignments

Parameter

Definition

connrules

Connect rule to build using the vsup=supplyValue you specify.

Valid Values:
basic

Build the "basic" connect rule

full

Build the "full" connect rule

inhconn_full

Build inheritance-based connect rule.

The connect rule defined using the inhconn_full
argument can inherit supply voltage automatically.
The default supply is cds_globals.\vdd! and
cds_globals.\vss!
You can use this argument instead of using the
vsup parameter to specify the supply voltage.
However, if both vsup and connrules=inhconn_full
exist in the same ie card, an error is reported. For
example:
ie vsup=1.8 connrules = inhconn_full

full_fast

Build the "full-fast" connect rule

Default Value: full_fast

Note: You can find the set of connect rule files that Cadence provides--including the "basic", "full", "inhconnfull", and "fullfast" connect rules--in
your_install_dir/tools/affirma_ams/etc/connect_lib

See your_install_dir/tools/affirma_ams/etc/connect_lib/README for detailed information about them.

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AMSD Block IE Card, Parameter Assignments

Parameter

Definition

discipline

Used as the discipline name corresponding to the ie card. If this parameter is not specified, the
discipline name is auto-generated.
In the example below, the discipline name corresponding to the ie card in the first ie statement will be
logic1_8 instead of the auto-generated discipline name ddiscrete_1_8. However, because the discipline
parameter is not used with the second and third ie statements, the corresponding discipline names for
these ie cards will be ddiscrete_3_3 and ddiscrete_4_5.
amsd {
ie vsup=1.8 discipline=logic1_8 rx=25
ie vsup=3.3 rlo=125
ie vsup=4.5 tr=0.4n
}
The discipline parameter can take only discrete discipline values. In the example below, the discipline
value is not discrete and therefore it is not supported.
ie vsup=1.8 instport="top.sub.pin" discipline="electrical
For continuous disciplines, use the elaboration -setdiscipline option instead. For example:
-setdiscipline "instterm-top.sub.pin- electrical"

Note: Unlike in a connectmap card, the discipline parameter in an ie card can accept only a single discipline value.

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