PhaseLockedLoopIntegratedCircuit

ScottBuchanan
JonathanBonello

SeniorProject

ELECTRICALENGINEERINGDEPARTMENT

CaliforniaPolytechnicStateUniversity

SanLuisObispo

2015

TableofContents

I.ListofTablesandFigures............................................................................................................2
II.Abstract.......................................................................................................................................4
III.Acknowledgements....................................................................................................................5

IV.Introduction................................................................................................................................5

V.TechnicalAspectsofPLLs.......................................................................................................10

VI.Requirements/Specifications....................................................................................................14

VII.PhaseFrequencyDetector......................................................................................................15

VIII.ChargePumpandLowPassFilter23

IX.VoltageControlledOscillator..................................................................................................31

X.FinalImplementation....41

XI.Conclusion...46

XII.References..47

Appendices
A. AppendixA:SeniorProjectAnalysis................................................................................48

ListofTablesandFigures
Tables
I.ListofAcronymsandsymbolsUsedinTransferFunctionAnalysis.............12
II.PLLRequirementsandSpecifications...14

Figures
I.BasicPLLCircuitStructure.........................................................................................................6
II.GainBlockvs.IntegratorBlock................................................................................................11
III.XORgate.................................................................................................................................15
IV.XORphasedetectoroutput......................................................................................................15
V.PFDHighestLevelBlockDiagram..........................................................................................16
VI.PFDBlockDiagram................................................................................................................16
VII.MasterSlaveDFlipFlop.......................................................................................................17
VII.FinalDFlipFlopSchematic...................................................................................................17
IX.Sampleinputclockwithsampleresettrigger..........................................................................18
X.InputleadingReference............................................................................................................19
XI.ReferenceLeadingInput..........................................................................................................19
XII.DFlipFlopattransistorlevel.................................................................................................20
XIII.DFlipFlopSimulation.........................................................................................................20
XIV.PFDSchematic.....................................................................................................................21
XV.PFDSimulation......................................................................................................................22
XVI.OriginalChargePumpSchematic.........................................................................................23
XVII.FinalizedChargePumpSchematic......................................................................................24
XVIII.LowPassFilterSchematic.................................................................................................25
XIX.ChargePumpwithLowPassFilterSchematic.....................................................................27
XX.ChargePumpandLowPassFilterSimulation......................................................................28
2

XXI.InputSignalof50MHz........................................................................................................29
XXII.InputSignalof100MHz.....................................................................................................29
XXIII.InputSignalof200MHz....................................................................................................29
XXIV.InputSignalof100MHzchangedto200MHzafter500nsec.........................................30
XXV.SimpleRingOscillatorCircuitBlockDiagram..................................................................31
XXVI.CurrentStarvingTopologyUtilizinganNMOS...............................................................32
XXVII.TransistorI
vsV
plot220/180nmW/Lratio.................................................................33
ds
ds
XVIII.TransistorI
vsV
plot330/270nmW/Lratio..................................................................34
ds
ds
XXIX.TransistorI
vsV
plot440/360nmW/Lratio..................................................................34
ds
ds
XXX.ControlVoltageversusFrequencyforthe660n/540nW/LRatio......................................35
XXXI.ControlVoltageversusFrequencywithanNMOSControl..............................................36
XXXII.NineInvertersinSerieswithPMOSControlforCurrentMirror.....................................37
XXXIII.ControlVoltagevs.FrequencyreplacingNMOScontrolwithPMOS660n/540n.38
XXXIV.ControlVoltagevs.FrequencyreplacingNMOScontrolwithPMOS540n/660n........38
XXXV.FrequencyChangingasControlVoltageChanges...........................................................39
XXXVI.PLLBlockDiagram........................................................................................................41
XXXVII.InputSignalof100MHz...............................................................................................42
XXXVIII.InputSignalof200MHz..............................................................................................43
XXXIX.InputSignalof50MHz..................................................................................................43
XL.InputSignalof100200MHz.................................................................................................44
XLI.LayoutofthePLL.................................................................................................................45

Abstract
Thisprojectfocusesonthedesignandsimulationofaphaselockedloop(PLL)integrated
circuit.APLLisanadvancedtopicandrequiresknowledgeofcontrolsystems,analogand
digitaldesign,aswellascommunicationbasicstofullyunderstand.APLLoftenconsistsofa
phasedetector,lowpassfilter,andavoltagecontrolledoscillator(VCO).Thisprojectdelves
intoeachindividualblockofthefullcircuitandgivescarefulconsiderationtoeach,exploring
thedifferentdesigntechniquesusedtocompleteaPLLdesign.Althoughthisparticularcircuit
couldbeusedforanumberofdifferentapplications,thisprojectfocusesonthedesignofaPLL
forsimpleclockgeneration.

Acknowledgements
WewouldliketothankProfessorTinaSmilksteinforsigningonasourprojectadvisor,aswell
astheentireCaliforniaPolytechnicStateUniversityElectricalEngineeringDepartment.Their
supportandinsightwerecrucialinthedevelopmentofthisproject.

Introduction
Phaselockedloops(PLLs)canbefoundinmanydifferenttypesofcircuitsnowadays.Their
applicationsrangefromavarietyofuses.Fromsynchronizationofclocksignals,demodulation,
clockrecovery,jitterandnoisereduction,anddeskewing,thelistofdifferentfieldstowhich
PLLoperationcanbeappliedisextensive.APLLoperatesbycomparingacertainoperating
frequencywiththecircuitclockfrequencyandsubsequentlyadjustingitsoutputtomatchthe
input.Itisanalogoustoacarscruisecontrolsystem[2].Asthecarexceedsthespeedspecified
bytheuser,thesystemslowsitdown.Ifthecarsspeeddropsbelowthespecifiedlevel,thecar
speedsup.Tofullyunderstandhowthisoperationoccurs,thebasicstructureofaPLLmustbe
describedandexamined.

Figure1:BasicPLLCircuitStructure

TherearegenerallythreecomponentsthatcanbefoundinanytypeofPLLregardlessofits
application.Thesepartsincludeaphasedetector,alowpassfilter,andfinallyavoltage
controlledoscillator(VCO)asdepictedin
Figure1
.Eachofthesecomponentshasadifferent
anduniquefunctionrequiredforthePLLtooperatecorrectly.Firstandforemost,thephase
detectorplaysacrucialroleinthesystemoperationandcanbecategorizedintotwoareas:a

phaseonlydetector,orafrequencyandphasedetector(phasefrequencydetectororPFD).A
phaseonlydetectorisjustthat,itisonlyabletodetectthephasedifferencebetweentwo
differentsignalsofthesamefrequency.Afrequencyandphasedetectorhowever,isableto
comparethefrequencyoftwodifferentincomingsignals(onefromtheinputandonefromthe
feedbackofthesystem)anddetectsthephasedifferencebetweenthetwo[1].Thisphaseand
frequencydifferenceisthentranslatedintoanerrorvoltagewhichispassedontothenext
stage.DuetothespecificapplicationofthePLLbeingexploredinthisdocument,thelatterof
thesetwotypesofdetectors(phasefrequencydetector)willbefocusedon.Asfaras
implementationanddesignofthephasedetectorisconcerned,therearemanyavenuesof
approach.Thiswillbediscussedinthelaterdesignspecificsportionofthisdocument.

BecauseaPFDisbeingused,achargepump(notshownin
Figure1
)mustbeimplementedas
well.AchargepumpsimplyinputstheoutputfromthePFD,anddependingonthatoutput,
pumpscurrentinoroutofthecircuitblockafterit(inthiscase,thelowpassfilter).Thiswill
bedonebyeithercompletingthecircuitconnectiontotherailorground,sourcingcurrent,or
dissipatingit.Thisvariationincurrentthatthelowpassfilterseeschangesthevoltageatthe
outputofthefilterandplaysacrucialroleindeterminingthecontrolvoltagefortheVCO.Refer
tothechargepumpdesigndetailsinthedesignsectionofthisreportforamoredetailedanalysis
ofhowthisoperates.

Afterthechargepumpisthelooplowpassfilter.Asthenamesuggests,itfiltersoutundesirable
signalsandnoisecomingfromthephasedetector.Theloopfilterisaveryimportantblockof

thePLL.Thisisduetoanumberofreasons,butmostimportantly,theloopfilterisresponsible
inalargepartformanyofthecharacteristicsofthePLL.Morespecifically,itiswhat
determinesthestabilityofthesystem,howquicklythePLLrespondstofrequencychanges,and
howeffectivelyitremovessignalswithunwantedfrequenciesfromenteringtheVCO.For
example,ifthePLLwantstochangefrequenciesquickly,thecutofffrequencyatwhichsignals
arentabletopassthroughanymorecannotbetoolow.Thisisbecausealowcutofffrequency
correspondstoslowercircuitoperation.Athighercutofffrequencies,thecircuitmayoperate
faster,yetunwantedfrequenciesmaypassthroughthepassband.Inaddition,caremustbe
takentoensurethefilterisstable,asthecontrarycouldprovedetrimentaltothecircuitoperation.
Anunstablesystemwillproduceunwantedoscillationsthatwilldisruptanefficientandaccurate
readingofthesignaldrivingtheVCO[1].Thesearejustatasteoftheconsiderationswhichwill
needtobetakenintoaccountwhiledesigninganeffectivefilter.

Lastly,theVCOiswhatproducesthesecondsignalwhichwillbecomparedtotheinputsignal.
Asthenamesuggests,itiscontrolledbythevoltagesignalstemmingfromthephasedetector
afterithasbeenpassedthroughthefilter.TheVCOdesigncanvarygreatlydependingonthe
needforthecircuit.Whetherdesigningalownoise,lowpower,orjustabasicoscillator,the
specificationscanvarygreatly.Forthisproject,abasicringVCOwithaslightemphasison
noisereductionwillbedeveloped.

WiththefundamentalsofPLLscoveredandasolidunderstandingofwhatproblemstheyare
abletoaddress,thegoalsandprocessofthisspecificprojectcanbeexplainedindetail.The

ultimategoalofthisprojectistodesignandsimulateaPLLICinordertogainabetter
understandingofhowthecircuitoperatesandwhatdetailsneedtobetakenintoconsideration
duringdesign.ThisprojectfocusesonageneraldesigntoillustratePLLoperationinsteadof
focusingonahighlyspecificandspecializedapplication.Thedetailsregardingthespecifications
ofthisPLLwillbecoveredintherequirementssectionsofthisdocument.Ideally,thisproject
wouldbetakentothetapeoutstage,andthePLLICwouldactuallybefabricated.Upon
examiningthetapeoutschedulingwithregardstothedesignprocessbeingusedhowever,itwas
determinedthatthisisnotarealisticgoal.Duetothislimitation,theendgoalwillbetousethe
CadenceVirtuosoLayoutSuitetodesignthecircuitandtestitthroughmultiplesimulations.
Whatthiswillresultin,isalayoutwhichcouldbesenttofabricationcompaniesforeventual
tapeout.

TechnicalAspectsofPLLs
WithageneralbackgroundofPLLsgivenabove,amoreindepthdescriptioncanbegiven,
explainingthedifferenttechnicalfactorstotakeintoconsiderationwhiledesigningaPLL
system.Thissectionwilldelveintosomespecificsandcharacteristicsofthedifferentpartsofa
PLLwhicharecrucialtofullyunderstandthedesignprocess.

Firstandforemost,twocommonPLLcharacteristicsareitstypeandorder.APLLstypeis
giveninreferencetohowmanyintegratorsarepresentinthesystem,whereasaPLLsorder
referstothenumberofpolesthatthesystemhas.InaPLL,aVCOisconsideredanintegratoras
itprovidesavoltagetophaserelationship.BecausetheVCOisanintegralpartofthePLL,all
PLLsareataminimumtype1.TypeIIPLLshaveanotherintegratorintheloopfiltertransfer
function[3].TypeIIsaremuchmorecommoninindustryforanumberofreasons.

AlthoughType1PLLshaveafewadvantageoverTypeIIPLLs,suchaslowersettlingtimes
(thetimeittakesforthePLLsystemtostablychangefromonefrequencytothenewfrequency)
[4],TypeIIPLLsaregenerallypreferred.Althoughlowersettlingtimemeansfastersystem
operation,TypeIIPLLshaveanadvantageinthatthewaytheDCsignallevelshiftsisnt
directlydependantontheinputtothegainblock.Byusinganintegratorintheloopfilter,the
outputcanbearbitrarilysettoaDClevelthatisntlimitedbytheinputtothefilter[3].Referto
Figure2
belowforanillustrationofthispoint.

10


Figure2:GainBlockvs.IntegratorBlock[3]
Ascanbeseenabove,theoutputoftheGainBlockisconstrainedtoacertainDClevelthatin
manycasesmaynothaveenoughrangetoencompassthatoftheVCOinput.Tofixthisissue,
otheramplifyingcircuitsmighthavetobeimplementedwhichwouldresultinmoretransistors
andahighercircuitcost.Essentially,aloopfiltercontaininganintegrator(AtypeIIPLL)
providesbettercontroloftheloop.

AnotherimportantconcepttounderstandisthefrequencyrangeandbandwidthofthePLLloop.
Thefrequencyrangeissimplythat:therangeoffrequenciesoverwhichthePLLcanreliably
lockandholditsstateat.Theloopbandwidthisrelatedtothenaturalfrequencyoftheloopand
isthefrequencyatwhichthePLLwillstarttoloselockwhenthereferencechanges.ThisPLL
characteristicislargelydeterminedbythelowpassfilterspecificationsandvalues.

InordertobetterunderstandtheeffectthatthelowpassfilterhasonthePLLsystemasawhole,
thetransferfunctioncharacteristicsofthePLLloopsystemwillbeexplained.Therearea
numberofacronymsandsymbolsusedwhicharelistedin
Table1
below.

11

Table1:ListofAcronymsandsymbolsUsedinTransferFunctionAnalysis

DampingFactorofSystem

NaturalFrequency

StabilizingZeroFrequency

K
VCO

VCOGaininHz/V

I
CP

ChargePumpCurrent

FeedbackDivisor(1forthiscircuit)

C
1

LargeLowPassFilterCapacitor

R
LPF

LargeLowPassFilterResistor

Tounderstandhowtheloopfilteraffectstheentiresystemtransferfunctionasawhole,the
generalclosedlooptransferfunctionforasystemmustbederived.Thiscanisrepresentedbelow
in
Equation1
.

[1]

In
Equation1,
G(S)istheopenlooptransferfunctionandisgivenby
Equation2
[2].

[2]

In
Equation2
ItscleartoseethattheopenloopgainisaffectedbyF(S)whichinturnaffectsthe
entiretransferfunctionofthecompletesystem.F(S),thelowpassfiltertransferfunctiondepends
onwhattypeoffilterischosen,andthevalueschosenforitscomponents.
12


[3]

[4]

[5]

Equations3,4,and5,
illustratehowthevalueschosenbythelowpassfilterreallyaffectcertain
PLLcharacteristics.ThevaluesoftheCapacitorandResistorofthelowpassfilterdeterminethe
naturalfrequency,stabilizingzerofrequency,andconsequentlythebandwidthoftheloop.In
addition,thedampingfactorisdependantonthesecomponentvalues[2].Thecalculationsfor
thesecomponentswillbeperformedintheLowPassFilterdesignsectiononcethetopologyof
thefilterhasbeenexplained.

13

Requirements/Specifications
Withmanyofthefollowingtermsdepictedin
Table2
describedintheprevioussection,this
PLLsspecificationsareasfollows:

Table2:PLLRequirementsandSpecifications

Specifications
Value

InputSignalType
LVCMOS

Type
II

Order
2nd

OutputSignalType
LVCMOS

LoopBandwidth
<100MHz

OutputFrequencyRange
50230MHz

ReferenceVoltage
1.8V

NumberofInputs
1

NumberofOutputs
1

SettlingTime
<500ns

DampingFactor
0.9<
<1.1

ChargePumpCurrentDrive
<25A

InputClockDutyCycle
50%

ThisPLLwasdesignedwiththesespecificationsinmind,andthroughoutthedesignsection,it
willbeverifiedthatthespecificationsweremet.

14

PhaseFrequencyDetector
Design
Aphasedetectorcircuitisonethatdetectsthephasedifferencebetweentwoinputsignals.
OriginallyanXORgatewasusedasthephasedetectorblockbecauseofitssimpleandeasyto
implementdesignasshownbelowin
Figure3
.

Figure3:XORgate[7]
Itwasabletoproduceapulseoneithertherisingorfallingedgeofasignalwhichaccurately
depictsthedifferenceinphasebetweenthetwosignalsasshownbelowin
Figure4
.

Figure4:XORphasedetectoroutput[7]
HoweverthemainproblemwiththeXORgatewasthatitcanonlydetectthephasedifference
butnotanydifferenceinfrequenciesbetweentheinputsignals.Itwasthendecidedthata
frequencyphasedetectorwouldhavetobeusedinthisPLLdesign.Aphasefrequencydetector
detectsthedifferenceinthephaseandfrequencybetweenthetwoinputsignals.
15


Figure5:PFDHighestLevelBlockDiagram
ItoutputsasignalfromeithertheUPorDOWNoutputtothechargepumpdependingonwhich
inputsignalisleadingtheotherasshownabovein
Figure5
.ThePFDiscomprisedoftwoD
FlipFlopsandanANDgateconnectedtotheresetofeachflipflopasshownin
Figure6
.

Figure6:PFDBlockDiagram[2]
FortheDFlipFlopsadesignhadtobechosentomakesurethePFDoperatedaspredicted.
WithmanydifferentpossibledesignsavailableforDFlipFlopsaMasterSlavetopologywas
foundtobethebestforthisimplementation.Itprovidedacircuitthatwouldntcontaina
possiblefloatingnodeatwhichthevaluecouldbehighorlow.

16


Figure7:MasterSlaveDFlipFlop
Theinitialdesignoftheflipflopshownin
Figure7
didntcontainaresetfunctionsoonehadto
beaddedtoachievethedesiredresponse.Thedesignshownin
Figure8
wasthefinalized
schematicthatwaschosen.

Figure8:FinalDFlipFlopSchematic
Withtheasynchronousresetimplementedin
Figure8
theexpectedresponseisthatwhenthe
resetgoeshightheoutputgoeslowuntilthenextclockrisingedgeatanytime.Dependingon
whethertheclockishighorlowwhentheresetistriggered,theMasterorSlaveloopwilloutput
theexpectedvalue.Ifresetistriggeredwhenclockishighthetransmissiongatebetweenthe
MasterandSlavewillbeonandtheNANDgateintheMasterloopdeterminestheoutput.Ifthe

17

resetistriggeredwhentheclockislowthetransmissiongatebetweentheMasterandSlavewill
beoffandtheNANDgateintheSlaveloopdeterminestheoutput.Ifresetstayshighforlong
enoughfortheclocksignaltogofromlowtohighorhightolowtheflipflopwillstilloperateas
intendedbecausetheMasterandSlaveloopscanholdthelastvalueused.

Figure9:Sampleinputclockwithsampleresettrigger

AftertheDFlipFlopsweredesignedthefunctionalityofthePFDwastested.Lookingat
Figure
9
UPandDOWNaretriggeredontherisingedgeofeachinputsignalandwhenbotharelogic
highthentheresetistriggeredandbothgolowuntilthenextrisingedge.Thiswillideallycause
UPandDOWNtoneverbebothhighatthesametime.TheUPandDOWNsignalswillthen
feedintotheinputofthechargepump.

LookingatthepossibletestcasesforthePFDtherearetwomainonesthatcanbeanalyzed.The
firstiswheretheInputisleadingtheReferenceandthesecondbeingtheReferenceleadingthe
Input.

18


Figure10:InputleadingReference

Figure11:ReferenceLeadingInput

ThedifferenceinphasecanbeobservedintheUPandDOWNoutputs.In
Figure10
wherethe
InputisleadingtheReferencetheUPoutputwillcauseforthesystemtospeedupsothatthe
Referencesignalcancatchup.In
Figure11
wheretheReferenceisleadingtheInputtheDOWN
outputwillcauseforthesystemtoslowdownsothattheReferencecanmatchtheInput.

19

Simulation

Figure12:DFlipFlopattransistorlevel

WhendesigningtheDFlipFloptheW/Lratioofcertaintransistorshadtobechangedtomake
surethatitoperatedcorrectly.Atnode4in
Figure12
abovetheinverterrequiredalargerW/L,
1m/180nm,ratiobecausethetransmissiongatewaspullingtomuchcurrenttotheground
causingforlessvoltagetobeoutputted.FortheothertransistorstheminimumW/L,220nm/180
nm,wasusedtomakeittheflipflopoperatedasfastaspossible.

Figure13:DFlipFlopSimulation
20


Theflipflopwastestedbytriggeringtheresetatfourpoints,whentheclockishigh,whenthe
clockislow,attherisingedgeoftheclock,andatthefallingedgeoftheclockshownin
Figure
13
.Withtheresettriggeredtheoutput,Q,waslookedattomakesureitwashighattherising
edgeoftheclockandwentlowatanypointwhentheresetishighandstayedlowuntilthenext
risingedge.FromthesimulationitwasobservedthattheDFlipFlopwasoperatingcorrectlyso
itwasthenimplementedintothePFD.

Figure14:PFDSchematic

WhendesigningtheANDgatein
Figure14
theW/LratiooftheNMOStransistorsintheNAND
gatehadtobeincreased.Theresetoriginallystayedlogichighafteritwastriggeredbecausethe
valueofresetwasntgoinglowenoughafterthePFDwasreset.SothewidthsoftheNMOS
transistorsintheNANDgatewereincreasedsothattheresetwouldgoallthewaydowntologic
low.AlsoaftertestingthePFDitwasobservedthatattheUPandDOWNoutputdidntgivea

21

cleansignalsotwoinverterswereaddedtomakesurethesignalgoesallthewayfromrailto
rail.

Figure15:PFDSimulation

In
Figure15
theInputsignalisleadingtheReference,orVCO,signalsoasexpectedtheUP
outputistriggeredhighuntiltherisingedgeoftheReference.WhenboththeUPandDOWN
signalsgohighthereisadelayofapproximately300psuntiltheybothgobackdowntoground.
This300psdelayisusedtodetectsmallchangesinphasebetweentheInputandReference[2].

22

ChargePumpandLowPassFilter
Design
AchargepumpcircuittakesintheUPandDOWNoutputpulsesfromthePFDandchangesitto
asingleDCvoltage.Atthestartofthedesignprocessasimpleschematicwasusedforthe
ChargePumptoseeifthebasicoperationoftheblockcouldbeverifiedshownbelowin
Figure
16
.

Figure16:OriginalChargePumpSchematic
Inthisdesignthetwocurrentcontrolledswitcheswerecreatedusingcurrentmirrorsconnected
toabiasingcurrent,thecurrentthroughboththeUPandDOWNsignalshavetobethesameto
preventmismatching.DependingontheUPorDOWNinputtheChargePumpwouldeither
pumpcurrentintothelowpassfilterordraincurrentout.WhentheInputisleadingthe
ReferencetheUPsignalwillbetriggeredandcurrentwillflowintothelowpassfilterincreasing
Vcontrol.WhentheReferenceisleadingtheInputtheDOWNsignalwillbetriggeredand
currentwillsinkoutofthelowpassfilterdecreasingVcontrol.Thisdesignhowevercausedfor

23

averyinconsistentcontrolvoltagetobeoutputtedandinmanycasesdidntoperateasintended.
Anewdesignforthechargepumpshownbelowin
Figure17
wasimplementedtoideallygetrid
oftheinconsistenciesattheoutput.

Figure17:FinalizedChargePumpSchematic

Thisdesignaccomplishedthatgoal.WiththeUPandDOWNinputsbeingfedintotransistors
locatedattherailstheoutputwasmuchlesssusceptibletonoise[2].Thevaluesoftheresistors
werealsosettovaluesthatwouldcausethecurrentsthroughUPandDOWNtobematched.
AlsotheW/Lratioformanyofthetransistorshadtobegreatlyincreasedtolowerthesensitivity
ofthesystem.

24

LowPassFilter
Thelowpassfilterwasimplementedwiththetopologyseenin
Figure
18.Itwasdeterminedthat
aTypeII2ndorderpassivefiltershouldbeutilizedduetoitssimplenature.

Figure18:LowPassFilterSchematic
Thetransferfunctionofthisparticularloopfilterisgivenby
Equation6
andfurthersimplified
by
Equation7
.Forstabilityreasons,andtopreventintroducinganewpoleintothesystem,C2is
chosentobe10timessmallerthanC1.BecauseitissignificantlysmallerthanC1,thestabilityof
theloopisntaffected,anditcanbeignoredforcalculationpurposes.

[6]

[7]

25

Bypluggingintheloopfiltertransferfunctioninto
Equations1and2
,weobtain:

[8]

Equation8
depictsthefinalgeneraltransferfunctionofthissystem.Utilizingtheformulas
introducedin
Equations3and5
,sufficientvaluesforthelowpassfilterwerecalculated.By
selectinga100kiloohmresistorforR1,andaC1valueof128fF,wewereabletoobtaina
naturalfrequencyof177Mrad/secandadampingfactorof1.13,whichiswithinthedesired
specifiedrange.Theloopbandwidthwascalculatedfromthenaturalfrequencytobe75.8MHz,
whichfallsunderthespecifiedloopbandwidthof100MHz.

26

Simulation

Figure19:ChargePumpwithLowPassFilterSchematic

ThesizingoftransistorsintheChargePumpwasmuchmoredifficultthanintheotherblocks.
TheW/Lratioofthediodeconnectedtransistorsin
Figure19
hadtobemuchlargerthanthe
transistorsconnectedtotheirbasestopreventchannelwidthmodulationaswellasmakingsure
thecurrentmirrorwasabletopassenoughcurrenttokeepthetransistorsintheirrequiredareaof
operation.ThetransistorsattherailsalsohadalargerW/Lratiotohelpwiththesystems
sensitivitytonoise[2].

27


Figure20:ChargePumpandLowPassFilterSimulation

Asshownin
Figure20
abovetheDOWNsignalhasamuchhighdutycyclethantheUPsignal
sotheChargePumpissinkingcurrentoutofthelowpassfilterandVcontrolisdecreasingover
time.ThecurrentthroughtheUPandDOWNinputswassetto23Aandthecapacitorsinthe
lowpassfilterweresetto128fFsothechangeinvoltagewas.01797V/nsec, CI =

dV
dt

OncetheChargePumpsfunctionallywasshowntobeoperatingcorrectlysampleInputsignals
werethensentthroughthePFDtoverifythattheoutputoftheChargePump,thecontrolvoltage,
wouldbeabletolocktoaDCvoltage.Referto
Figures21,22,23,and24,
forsimulationsofthe
outputofthelowpassfilter.Ineachcasethesettlingnatureofeachsignalisclearlyvisible.The
blipsseenonthesignalsarecausedbytheUPandDOWNswitchingactionofthePFD.This
occurswhentheyarebothonatthesametime.

28


Figure21:InputSignalof50MHz

Figure22:InputSignalof100MHz

Figure23:InputSignalof200MHz
29


Figure24:InputSignalof100MHzchangedto200MHzafter500nsec
UsingtheInputsignalshownabovein
Figure24
,thesettlingtimewasfoundtobe
approximately450nsecwhichmeetsourspecificationoflessthan500nsec.

30

VoltageControlledOscillator
Design
Asdiscussedbefore,theVCOisresponsibleforprovidingthefrequencyatwhichthePhase
LockedLoopoperatesat.Thefrequencyisvariable,dependingonthelevelofthevoltagebeing
senttoitscontrolterminal.Dependingonthedesign,thefrequencywilleitherincreaseor
decreaseasthecontrolvoltageisraised.ForthepurposesofthisVCOdesignandteststage,the
controlvoltagewassimulatedtodeterminetheoscillatorgainandKVCOcharacteristics,aswell
asitsoperablelinearrange.Thiswillbeexplainedinmoredetailinlatersections.

TherewereanumberofdifferentoptionsforthedesignoftheVCO,butultimatelyaring
oscillatorwaschosen.ThistypeofVCOemploysanoddnumberofinvertersconnectedtoeach
otherinaloop(See
Figure25)
.

Figure25:SimpleRingOscillatorCircuitBlockDiagram

Ateveryrunthroughthesystem,eachnodeoscillatesbetweena1and0duetotheinverting
action.Thisproducesawaveformatacertainfrequencyattheoutputofthecircuit.This

31

frequencyisdeterminedbyf=1/2Nt
,wherefisthefrequency,Nisthenumberofinverter
d
stages,andt
isthetimedelaycharacteristicoftheinverterbeingused.
d

Toimplementavariablefrequencysystemcontrolledbyanexternalvoltage,acurrentstarving
NMOSwasplacedatthebottomnodeofeachinverterasdepictedin
Figure26
below
.

Figure26:CurrentStarvingTopologyUtilizinganNMOS

Figure26
showsaninverterchainwiththePMOSsourcetiedtotherailandtheNMOSsource
tiedtoground,withtheirgatesanddrainsconnectedtoeachother.TheNMOSatthebottomof
eachinverterservesasthecurrentstarver.ThecontrolvoltageissenttothegateofthisNMOS
andcancontroltheamountofcurrentflowingthroughthechain.This,inturn,affectsthe
frequencyoftheloop.

32

ForthepurposesofthisPLLdesign,alowfrequencyspecificationwaschosen.Inthiscase,
about50MHztoabout250MHzwiththeleaststeepKVCOcurvewasdesired.Withthisin
mind,thefirststepinachievingthesedesigngoalswastodosometransistorcharacterizationto
determineanoptimalsizingratioforthelengthandwidthsofthefieldeffecttransistor(FET)
channels.

WithinCadence,asimpleNMOSwaslaidoutandthedrainsourcecurrent(I
)vsdrainsource
ds
voltage(V
)plotswereobtainedforagatesourcevoltage(V
)ofabout0.7volts.Thechannel
ds
gs
lengthandwidthswerethenvariedtoobservetheeffectsthatitmighthaveontheI
vsV
plot.
ds
ds
Referto
Figures27,28,and29
foranexample.

Figure27:TransistorI
vsV
plot220/180nmW/Lratio
ds
ds

33


Figure28:TransistorI
vsV
plot330/270nmW/Lratio
ds
ds

Figure29:TransistorI
vsV
plot440/360nmW/Lratio
ds
ds

Ascanbeobservedfromtheabovefigures,asthechannelwidthsandlengthsareincreased,the
morethecurveflattensouttowardsthehigherendofV
.Thegoalofthisexercisewastoobtain
ds
thetransistorchannelwidthandlengthvaluesthatwouldmaximizeourKVCOlinearrange.
Thatbeingsaid,thereisastarkdifferencebetweenthecurvaturedepictedin
Figures27and29,
butitwasfoundthatathigherwidthandlengthsizes,thecurvaturedifferenceisnegligible.At

34

thispointthedeterminingfactorforthetransistorchannelsizeswouldbetheaffectithasonthe
frequencyofthesystemasawhole.Recallfromearlierthatthetwomainmethodsforchanging
thefrequencyofaringoscillatorinvolvechangingthenumberofinvertersintheloop,and/or
changingthechannelandwidthlengthsofthetransistors,modifyingtheircapacitance,andthus
affectingthetimethatittakesforthenodestooscillatebetween1and0.Inthisparticularcase,a
W/Lvalueof660/540nm,inadditiontoa9inverterstring,wasusedtoobtainourdesired
frequency.

Simulation
Withthisdesign,thefrequencyincreasedasthecontrolvoltagewasincreased.Inordertoobtain
theVCOgain,anexcelgraphwasgeneratedbyplottingthefrequencyversuscontrolvoltage.
Theresultingplotcanbeseenin
Figure30.

Figure30:ControlVoltageversusFrequencyforthe660n/540nW/LRatio

35

In
Figure30
,thelinearportionofthegraphcontainstheusablefrequenciesatwhichtheVCO
willoperateproperly.ItisthetuningrangewithinwhichtheVCOmustoperate.TheKVCO
couldbedeterminedbyfindingtheslopeofthislinearportion.Inthiscase,thetuningrangewas
roughlybetween25MHzto285MHz,encompassingacontrolvoltagerangeofabout0.5Vto1V
(0.5Vrange).Thisisaboutathirdofourfullvoltagerangeof01.8V.Wedidntwanttolimit
ourinputvoltagerangetoafractionofourrailandsosetabouttomodifythedesigninorderto
maketheKVCOslopeasshallowaspossible.

Thefirstmodificationcameintheformofacurrentmirrorcontrolsystemthatwouldbe
mirroredwithallthecurrentstarvingNMOStransistorsbelowtheinverterring.Thecontrol
voltagewouldbesentsolelytothegateofanNchanneldeviceconnectedtothedrainofthe
currentmirror.Oncethesameanalysiswasperformedonthiscircuit,thefollowingexcelplot
wasobtained.

36

Figure31:ControlVoltageversusFrequencywithanNMOSControl

In
Figure31,
itcanbenoticedthattheKVCOofthecircuithasbecomeslightlyshallower.The
linearportionofthisgraphextendsfromabout1.1Vto1.7V.Thisisaveryslightdifferentfrom
theprevious0.5Vdifference.

OnemorechangewasmadetothedesigninordertodecreasethesteepnessoftheKVCO
Characteristic.Simplyput,theNMOSconnectedtotherailwasreplacedwithaPChannel
device(see
Figure32
).Withsomemodificationstothechannellengthandwidthratio,this
allowsthecontrolvoltagetopullallthewaydownto0Vandprovidedamuchmorelinear
KVCOcharacteristic(see
Figure34)
.
Figure33
depictsthedifferencethatjustchangingthe
NMOStoaPMOSmade,whereas
Figure34
depictsthefinalplotoncetheW/Lvalueshadbeen
changedtothedesiredspecifications.

Figure32:NineInvertersinSerieswithPMOSControlforCurrentMirror
37

Figure33:ControlVoltagevs.FrequencywhenreplacingNMOScontrolwithPMOS660n/540n

Figure34:ControlVoltagevs.FrequencywhenreplacingNMOScontrolwithPMOS540n/660n

38

In
Figure34
itcanbenoticedthatalmosttheentirerangeofcontrolvoltagevaluesisusablein
thislinearrange.Thevoltagecanbevariedfrom0Vto1.4Vwhilestillmaintaininglinearity.
Thisresultsinachangeoffrequencyfromabout235MHzto2MHz,wellwithinthedesired
frequencyrange.

TheonlydifferencebetweenthisdesignandtheoneincorporatingtheNMOSisthatthe
frequencynowdecreasesinsteadofincreasingasthecontrolvoltageisraised.Thischangein
directionshouldntmatterandcanberesolvedeasilybyswitchingtheinputterminalstothe
phasefrequencydetector.ThefinalproductofthisdesignisaVCOthatchangesfrequency
linearlyfrom2MHzto235MHzovertherangeof0to1.4volts.Referto
Figure35
foran
illustrationofthis.

Figure35:FrequencyChangingasControlVoltageChanges

39

The1Vspikeseenattherailsathighfrequenciesisduetothecapacitancescharginguptoabove
andbelowrails.Asmallcapacitorcouldbeplacedbetweenthepowerandgroundrailstonegate
thiseffect,butitwasdeterminedunnecessaryforthepurposesofthisdesignascapacitorstakea
largeamountofspaceonthechiplayout.

ThefinalstepfortheVCOimplementationistocalculatetheKVCOvaluewhichisassimpleas
obtainingtheslopefromthecontrolvoltageversusfrequencyplotdepictedin
Figure34
.The
linearrangeextendsfrom0Vtoabout1.3V.Withthatinmind,thenegativeslopeiscalculatedto
be174.7MHz/V.

40

FinalImplementation
AftereachthedesignandverificationofeachblockwascompletedthewholePLLwas
connectedtogethersothefunctionalitycouldbetested.

Figure36:PLLBlockDiagram
Whenconnectingalloftheblockstogether,shownabovein
Figure36
,thePFDsUPand
DOWNoutputsweretiedtotheChargePumpsDOWNandUPinputsrespectively.Thiswas
becauseofthechoicetouseaPMOSdrivenVCO.SincetheVCOisdrivenusingaPMOS
insteadofaNMOSasthecontrolvoltagedecreasesthefrequencyincreases.Becausesofthisfor
theReferencesignaloutputtedfromtheVCOtospeedup,thecontrolvoltagewouldhavetobe
lowered.ForthistohappentheDOWNsignalattheinputoftheChargePumpwouldhaveto
havealargerdutycyclethantheUPinput.SoassumingthattheInputsignalisatahigher
frequencythantheReferencesignalthePFDwilloutputahigherdutycyclesignalfromtheUP
outputwhichisthenfedintotheDOWNinputoftheChargePumpincreasingthefrequencyof
theReferencesignal.ThetwoinvertersconnectedtotheoutputofthePLLwereaddedtomake
therisingandfallingedgesmoreprecise.InthefiguresbelowtheblueVCOsignalrepresentsthe
outputoftheVCOandthegreenOutputsignalrepresentsthesamesignalafterhavingpassed
throughbothinverters.
41


FortestingthePLLthefrequencyrangechosentotestwasboundbytheVCOsregionof
operation.ItwasfoundthattheVCOcouldoperatefrom50235MHzsothosefrequencieswere
usedattheboundariesoftheoperationofthePLL.

Figure37:InputSignalof100MHz
Thefirsttestwasa100MHzsignalthatwasusedasasortofmidpointtomakesurethePLL
wasoperatingcorrectlybeforewetriedfrequenciesclosertotheboundaries.From
Figure37
it
canbeobservedthatafterapproximately200nsecthePLLoutputisabletolatchontotheinput
signal.

42


Figure38:InputSignalof200MHz
Similartothe100MHzcasethesettlingtimeisalsoabout200nsecbutat200MHztheoutput
signaldoesntgotoafullystablestateasthereisstillsomerippleobservedshownabovein
Figure38
.

Figure39:InputSignalof50MHz
Thesettlingtimeforthe50MHzin
Figure39
wasalsocloseto200nsecbuttheoutputwas
muchmorestablethanthe200MHzsignal.
43


Figure40:InputSignalof100200MHz
Thefinaltestcasewasonewherethefrequencywaschangedfrom100MHzto150MHzafter
300nsec,whichwashopefullyenoughtimeforthesystemtolockatbothfrequencyinputs.It
wasobservedthatthePLLwasabletolockatbothfrequenciesshownin
Figure40.

44


Figure41:LayoutofthePLL
ThelayoutofthePLL,shownabovein
Figure41
,wasoriginallyagoaltobecompletedbut
becauseofmanydifferentproblemsusingtheLayouttoolsinCadencewewerentableto.The
AutoRoutingtoolwasonlyabletomakeapproximately70%oftheconnectionsandtherewere
hundredsofDRCerrorsassociatedwithit.Thisgaveuslimitedoptionsonhowtocompletethis
objective.EachDRCerrorcouldhavebeendealtwithonebyoneorthewholePLLcouldhave
beenmanuallyroutedbutduetotimeconstraintsneitheroftheseoptionsseemedrealistic.

45

Conclusion
Overall,designingaPLLgaveusagreatopportunitytogothroughtheentiredesignprocessof
anIC.Byresearching,designing,andtestingthePLLwewereabletoreviewandexpandon
manydifferenttopicsthathavebeenlearnedthroughoutourcollegecareer.SincePLLdesign
requiresknowledgeofcontrolsystems,analog,digitalcircuitryandcommunications,thisproject
servedasaperfectmeanstoexercisethisknowledgeinarealworldapplication.Alsobyusing
CadencesVirtuososoftwarewewereabletogainexperienceusingadesigntoolthatisusedin
industry.Itwasunfortunatethatwewerenotabletotakethisprojecttothetapeoutstage,but
thedesignprocesstooklongerthananticipatedandthelayoutwasprovingtobemore
challengingduetoprogramrestraints.Inanycase,thedesignandschematicworkproved
challenginginitsownrightandprovideduswithanopportunitytoapproachadesignoriented
projectwithmanydifferentoptions.

46

References
1. Poole,Ian.2014.PLLPhaseLockedLoopTutorial.[Online]Available:
http://www.radioelectronics.com/info/rftechnologydesign/pllsynthesizers/phaselocke
dlooptutorial.php
2. Fischette,Dennis.2004.PracticalPhaseLockedLoopDesign.ISCCTutorial.[Online]
Available:
www.delroy.com/
PLL
_dir/ISSCC2004/
PLL
TutorialISSCC2004.ppt
3. Fischette,Dennis.2009.FirstTime,EveryTimePracticalTipsforPhaseLockedLoop
Design.[Online]Available:
http://www.delroy.com/PLL_dir/tutorial/PLL_tutorial_slides.pdf
4. Perrott,Michael.2005.PLLDesignUsingthePLLDesignAssistantProgram.[Online]
Available:
http://cppsim.com/Manuals/pll_manual.pdf
5. 2006.SettlingTimeMeasurementsofaPLLChip.[Online]Available:
http://www.ni.com/whitepaper/4856/en/
6. IEEE(2013November)IEECodeofEthics[Online]Available:
http://www.ieee.org/about/corporate/governance/p78.html
7.eee.2014.PhaseDetector
.[Online]Available:
http://eeeguide.com/phasedetector/

47

AppendixA:SeniorProjectAnalysis

ProjectTitle:
PhaseLockedLoopIntegratedCircuit
Students:
JonathanBonelloandScottBuchanan
Advisor:
ProfessorTinaSmilkstein

1. SummaryofFunctionalRequirements
ThisprojectfocusesonthedesignandapplicationofaPhaseLockedLoop(PLL).The
PLLwillconsistofanumberofcomponents,mostnotablyavoltagecontrolledoscillator,
phasefrequencydetector,chargepump,andloopfilter.Thedesignofthisprojectwill
focusaroundthesefourcomponents,andtheprocessbehindthem.
2. PrimaryConstraints
Thelargestchallengesassociatedwiththisprojectwillcomefromalackofknowledge
aboutPLLlayoutanddesign.Alargeamountofpersonalresearchwillneedtobedone
tounderstandPLLoperationanddesigntechniquesinsideandout,especiallysincePLLs
havenotbeencoveredintheElectricalEngineeringcourseworktakenuptothisdate.On
topofthis,theCadenceVirtuosoLayoutSuitewillneedtobelearned.Itwilltakea
numberofweekstobecomeproficientatthissoftware,anditisonlyuntilthenthat
significantprogresswillbeabletobemadeonthisproject.
3. Economic

48

Asfarasourowneconomicdetailsareconcerned,themonetarycostofthisprojectwill
belittletonone.OnlinesourcesaswellasbooksandjournalsonPLLdesigncanallbe
referencedfornocharge.Inadditiontothis,therewillbenobillofphysicalmaterialsas
theCadencesoftwarewillbeusedtodesignandsimulatetheintegratedcircuit.This
processwillmostlikelynotcarryoverintotapeoutandsotherewillbenomaterialcosts
associatedwiththat.However,ifthiswereacircuitdesigncompanycreatingthischip,
thecostswouldbesignificantlylarger.TheCadencesoftwareinandofitselfcosts
upwardsof$250,000.Acompanywantingtousethissoftwarecommerciallywouldbe
subjecttothesecosts.Inaddition,thefabricationandtestingprocesscouldcostan
extensiveamount.

Asfarastimeisconcerned,thedevelopmenttimewassplitupasfollows:thefallterm
includedpreliminaryVCO,andPhaseFrequencyDetectordesignaswellastakingthe
timetolearnmoreabouttheCadencesoftwareandPLLdesigntechniques.Thewinter
termwasfocusedaroundpolishingourexistingdesignsanddesigningaloopfiltertohelp
thePLLmeetthespecificationslisted.Springterminvolvedfinalsystemimplementation
andfinalcompilingofallthedocumentationregardingtheproject.
4. IfManufacturedonaCommercialBasis
SincethisICisbeingdesignedtobeaddedtomultipletypeofsystemsitwillbeavailable
forpurchaseseparately.Ifitweremanufacturedinmassthepriceperunitwoulddrop
considerablyandwemightseethePLLpricedroptoaroundthreeorfourdollarsper
49

chip.Inthiscase,aprofitoffivedollarscouldbemadeperchip.Iftheneedforsucha
PLLbeginstoincrease,sincetechnologyisalwaystrendingtowardfasterandmore
accurateoperatingspeeds,thenmoreofthisproductcanbesold.Understandably,the
manufacturingofthisproductwouldtakeanumberofyearstopayoffthecostsofthe
Cadencesoftwareandtestingprocedures.
5. Environmental
Theonlyenvironmentalconcernswouldbethoseassociatedwithpoweringthe
computersthatwillberunningthesimulationsaswellasthefabricationprocess.The
fabricationprocessinvolvedusesmanyraremetalsandsilicon.Itinvolvesmany
chemicalswhichcanalsobeharmfultotheenvironmentifdisposedofimproperly.On
topofthisthereis,ofcourse,thecostofelectricitytorunthefabricationmachines.This
hasanimpactontheenvironment.Asfarasourprojectisconcerned,ifthetapeout
stageisnotreached,noneofthesewillbeofanyimmediateconcern.
6. Manufacturability
Asfarasmanufacturingisconcerned,apartnershipwithamanufacturingcompany
woulddefinitelyneedtobeformed.Tryingtofabricatethischipwithouttheaidofa
largefacilitydedicatedtowardsthatpurposewouldbeunreasonable.Itwouldsimplybe
tooexpensive.Ontopofthis,ourchipisbeingdevelopedintheIBM180nmcmrf7sF
process.Thefabricationcompanywepickwouldneedtosupportthisprocess.Giventhat
therearemanyofthesecompanies,thisshouldntbeanissue.Complicationsmayarise

50

iffacilitiesneedtobeshutdownforanynumberofreasons,butingeneralthereisawide
rangeofavailableoptionsformanufacturing.
7. Sustainability
Therearenotmanysustainabilityconcernstiedtothisproject.Oncethechiphasbeen
fabricatedandisinstalledontheboardlevel,verylittletonoupkeepisrequiredtoensure
properoperation.Theonlyimpactthisproductwillhaveonsustainableuseofresources
isthatofelectricityuse.Withthisinmind,upgradestoimproveitssustainabilityfeature
wouldbealongthelinesofminimalpoweruse/lowpoweroperation.Thiswould
minimizetheelectricitybeingusedwhilerunningthisproduct.Attemptingtoupgrade
thechiptoimplementthisfeaturewouldbeanextensiveprocessandwouldrequire
redesignofthecircuitsinvolved,andmoretestingtoensureitoperatesasintended.
8. Ethical
Toexaminetheethicalissuesrelatedtothisproject,thepertinentIEEEcodeofethics
willbecited.Thecodestatesthatitisimperativethattheengineerisabletoseek,
accept,andofferhonestcriticismoftechnicalwork,toacknowledgeandcorrecterrors,
andtocreditproperlythecontributionsofothers[6].Thisisanissuecommonly
encounteredamongstudentsandisonethatwillbeadheredtothroughoutthedurationof
thisproject.Ifaprojectmemberfailstoaccepthonestcriticismofhis/hertechnical
work,seriousproblemsregardingthecircuitsfunctionalitycouldarise,resultingin
productdefect,andsubsequently,lossofrevenueforthecompanyproducingit.
Dependingontheapplicationoftheproductbeingused,livescouldbeputatriskaswell.
51

Althoughtheriskoflossoflifeshouldnotbeaconcernforthisproject,thisethicalcode
willstillneedtobefollowed.

Oneotherpillarofthecodeofethicsthatespeciallyappliestothisprojectisthe
agreementtoassistcolleaguesandcoworkersintheirprofessionaldevelopmentandto
supporttheminfollowingthiscodeofethics[6].Throughoutthisproject,Scottand
Jonathanwillbehelpingeachothergrowprofessionally.Whetheritskeepingeachother
accountableforthetechnicalworkwedo,orbeinghonestinstatingclaimsabout
estimateswewillensureouractionsareconsistentwiththeotherpillarsintheIEEEcode
ofethics.
9. HealthandSafety
Thischipwillhavealmostnoriskassociatedwithitonceithasbeenmanufacturedand
installedontheboardlevel.Thereisnoworryofelectricalshockasthepowerthatruns
thechipisnotenoughtocausedamagetothehumanbody.Duringmanufacturing
howevertheremaybetheusualsafetyconcernssurroundingoperationanduseofthe
equipmentusedtofabricate.
10. SocialandPolitical
Asfarassocialissuesareconcerned,again,thefabricationandmanufacturingprocesses
willmakethemostimpact.Dependingonwherethechipwillbefabricated,the
companythatacquiresthejobwillhavemorework,stimulatingthelocaleconomy.

52

WhetherthisisintheUnitedStatesorabroad,thiswillbeaneffecttoconsider.
Stakeholdersincludetheabovementionedfabricationcompanyandthecompaniesthat
utilizesuchPLLs.Regardingtheactualproductitself,itsimplementationintomany
differentapplicationsmightcauseanimpactonsocietyasPLLsareusedinallmanners
ofapplications.However,thiseffectwillbeextremelydifficulttorecognize
immediately,andisnotexclusivelytiedtotheproductionofourchip.
11. Development
Duringthisdevelopmentprocess,ScottandIwererequiredtolearnandbecome
proficientattheCadenceVirtuosoLayoutSuite.Thisnecessitatedustotakeacourse
andcompleteanumberoftutorials.Beinganindustrygradesoftwareprogram,thiswas
notatrivialtask.Ontopofthis,areviewofcircuitdesigntechniquesaswellabroad
understandingofPLLswasrequired.Onlyuntilthesetwoaspectswerecombinedwere
weabletobegintheactualdesigncycle.Duringthistime,carewastakentoensure
propercircuitoperationthroughextensivesimulationandtesting.Inaddition,thedesign
wasbeingconstantlycheckedagainstthesystemrequirementsspecifiedintheproject
document.

53